Construction Analysis
Atmel AT89C2051 & AT89S8252 Microcontrollers
a
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miconductor
In
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Since 1964
n Servi g the G lo b
Report Number: SCA 9706-543
®
15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925 e-mail:
[email protected] Internet: http://www.ice-corp.com/ice
INDEX TO TEXT TITLE
PAGE
INTRODUCTION MAJOR FINDINGS
1 1
TECHNOLOGY DESCRIPTION Assembly Die Process and Design
2 2-4
ANALYSIS RESULTS I Assembly
5
ANALYSIS RESULTS II Die process
6-8
ANALYSIS PROCEDURE
9
TABLES Overall Quality Evaluation Package Markings Wirebond Strength Die Material Horizontal Dimensions Vertical Dimensions
10 11 11 12 13 14
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INTRODUCTION This report describes a construction analysis of the Atmel AT89C2051 and the AT89S8252 8-Bit Microcontrollers. Ten AT89C2051 devices encapsulated in 20-pin Dual-In-line Packages (DIPs) and two AT89S8252 devices in 40-pin Dual-In-line Packages were used for the analysis. The AT89C2051 devices were date coded 9642 and the AT89S8252 had a date code of 9709. MAJOR FINDINGS Questionable Items:1 • Metal 1 aluminum thinning up to 90 percent2 at some contact edges on the AT89C2051 (Figure 13). Special Features: None. Noteworthy Items: • Both devices are of similar structure; however, there are distinct differences. The Flash cell design is the same on both devices; however, the cell of the AT89S8252 is smaller. The AT89S8252 also has an EEPROM memory. Cell design is identical and the only distinction between the Flash and the EEPROM memory appears to be the method in which the cells are erased. The other significant difference is that the AT89S8252 employs a second metal layer which is used sparsely, mainly to connect circuit blocks.
1These items present possible quality or reliability concerns.
They should be discussed with the manufacturer to determine their possible impact on the intended application.
2Seriousness
depends on design margins.
-1-
TECHNOLOGY DESCRIPTION Assembly (AT89C2051 device only unless indicated): • 20-pin plastic Dual-In-line Package (DIP). • 40-pin plastic Dual-In-line Package (DIP) AT89S8252. • External leads plated with tin-lead (SnPb) and internally spot-plated with silver (Ag). • A silver-epoxy die attach was employed on both die. • Die coat was not employed on either die. • Lead-locking provisions (holes) were present at all pins. • Multiple wirebonds were used at Vcc and GND pins to provide extra currentcarrying capacity. A bonding wire was connected from ground to the paddle for biasing purposes. • Thermosonic wirebonding using 1.2 mil O.D. gold wire. • Dicing was by sawing (full depth) on both die. Die Process and Design • Note: Process description is same on both devices except where noted. • Fabrication process: CMOS process employing twin-wells, on a P-substrate. • Final passivation: Two thick layers of silicon-dioxide.
-2-
TECHNOLOGY DESCRIPTION (continued) • Metallization: Single level metallization was used on the AT89C2051 device. No cap was used; however a titanium-nitride barrier was employed. The metal was defined by a standard dry etch. Two levels of metallization were used on the AT89S8252 device. Metal 2 employed a titanium-nitride barrier and metal 1 employed a titanium-nitride cap and barrier. Metal 2 was sparsely used and appeared to mainly connect circuit blocks together. • Interlevel dielectric (AT89S8252 device only): The dielectric consisted of two layers of glass. The first layer appeared to have been subjected to an etchback. • Pre-metal: A single layer of reflow glass over grown oxides. The glass appeared to have been reflowed following the contact cuts. • Polysilicon: Two layers of standard poly silicon were employed. Poly 2 was used to form all gates on the die and word lines and program lines in the EEPROM arrays. Poly 1 was used exclusively in the EEPROM arrays where it formed the floating gates. • Diffusions: Standard implanted N+ and P+ diffusions formed the sources/drains of transistors. No sidewall spacers were present on the gates and no evidence of LDD structures was found. • Isolation: LOCOS, a step was noted in the local oxide at the well boundary indicating a twin-well process was employed. • Wells: Twin-wells in an P substrate. • Fuses: No fuses were employed on this device. • Buried contacts: No buried contacts were used.
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TECHNOLOGY DESCRIPTION (continued) • SRAM: The memory cell consisted of a 6T SRAM design. Metal 1 formed the bit lines and distributed Vcc and GND. Poly 2 formed the word lines, storage gates and pull-up devices. • EEPROM: The memory cell design consisted of a poly 2 word line and program line and a poly 1 floating gate. Metal one formed the bit lines. Programming is achieved through ultra-thin tunnel oxide windows. Interpoly dielectric consisted of an ONO dielectric. Both of the devices AT89S8252 and AT89C2051 have the same layout design for both EEPROM (AT89S8252 only) and Flash memory. However, the cell size of the AT89S8252 was about half the size of the cell on the AT89C2051. On the AT89S8252 both EEPROM and Flash had the same design on the AT89S8252 device, but the way the cells are erased distinguishes the two types. • MROM: An MROM cell array was employed on both devices. The cell was programmed by the metal 1 layer. No detailed analysis of this memory was performed since structures are the same as the peripheral circuits.
-4-
ANALYSIS RESULTS I Assembly:
Figures 1 - 4
Questionable Items:1 None. Special Features: None. General Items: • Overall package quality: Good. No significant defects were found on the external or internal portions of the packages on both die. No voids or cracks were noted in the plastic package on both die. • Wirebonding: Thermosonic ball bond method using 1.2 mil gold wire. Bonds were well formed and placement was good. All bond pull strengths were normal and no bond lifts occurred (see page 11). • Die attach: Silver-epoxy of normal quality. No problems were found. • Die dicing: Die separation was by sawing (full depth) and showed normal quality workmanship. No large chips or cracks were present at the die surface.
1These items present possible quality or reliability concerns.
They should be discussed with the manufacturer to determine their possible impact on the intended application.
-5-
ANALYSIS RESULTS II Die Process and Design:
Figures 5 - 31
Questionable Items:1 • Metal 1 aluminum thinning up to 90 percent2 at some contact edges on the AT89C2051 (Figure 13). Special Features: None. Noteworthy Items: • Both devices are of similar structure; however, there are distinct differences. The Flash cell design is the same on both devices; however, the cell of the AT89S8252 is smaller. The AT89S8252 also has an EEPROM memory. Cell design is identical and the only distinction between the Flash and the EEPROM memory appears to be the method in which the cells are erased. The other significant difference is that the AT89S8252 employs a second metal which is used sparsely, mainly to connect circuit blocks. General Items: • Fabrication process: CMOS process employing twin-wells in a P substrate. All Pchannel devices were formed in N-wells. All N-channel devices were formed in Pwells. No epi was employed on these devices. • Design implementation: Die layout was clean. Alignment was good at all levels. 1These items present possible quality or reliability concerns.
They should be discussed with the manufacturer to determine their possible impact on the intended application.
2Seriousness
depends on design margins.
-6-
ANALYSIS RESULTS II (continued) • Surface defects: No contamination, processing defects or tool marks were found. • Final passivation: Two thick layers of silicon-dioxide. • Metallization: A single level metallization was used on the AT89C2051 device. No cap was used; however a titanium-nitride barrier was employed. Two levels of metallization were used on the AT89S8252 device. Metal 2 employed a titaniumnitride barrier and metal 1 employed a titanium-nitride cap and barrier. Metal 2 was used mainly to connect circuit blocks together. • Metal patterning: The metal layers were defined by standard dry etch. Metal completely surrounded all contacts. Standard contacts were employed (no plugs). • Metal defects: No notching or voiding was found. No silicon nodules were observed following removal of the aluminum layers. • Metal step coverage: Metal 1 aluminum thinning was up to 90 percent thinning (Figure 13) at some contacts. The amount of thinning is excessive a manufacturer’s design specifications should be verified (AT89C2051 only). • Contacts: Contacts were overetched slightly into the substrate and polysilicon; however, no problems are foreseen. • Interlevel dielectric (AT89S8252 device only): The dielectric consisted of two layers of glass. The first layer appeared to have been subjected to an etchback. No problems were noted. • Pre-metal: A single layer of reflow glass over grown oxides. The glass was reflowed following the contact cuts. No problems were found.
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ANALYSIS RESULTS II (continued) • Polysilicon: Two layers of standard polysilicon were employed. Poly 2 was used to form all gates on the die and word lines and program lines in the EEPROM array. Poly 1 was used exclusively in the EEPROM array where it formed the floating gates. • Isolation: Local oxide (LOCOS). No problems were present at the birdsbeaks or elsewhere. A step was present in the local oxide at the well boundaries. • Diffusions: Standard implanted N+ and P+ diffusions formed the sources/drains of transistors. No sidewall spacers were used and no evidence of LDD structures were found. • Wells: Twin-wells in an P substrate. • Fuses: No fuses were employed on this device. • Buried contacts: No buried contacts were used. • SRAM: The memory cell consisted of a 6T SRAM design. Metal 1 formed the bit lines and distributed Vcc and GND. Poly 2 formed the word lines, storage gates and pull-up devices. • EEPROM: The memory cell design consisted of a poly 2 word line and program line and a poly 1 floating gate. Metal one formed the bit lines. Programming is achieved through ultra-thin tunnel oxide windows. Interpoly dielectric consisted of an ONO dielectric. Both of the devices AT89S8252 and AT89C2051 have the same layout design for both EEPROM (AT89S8252 only) and Flash memory. However, the cell size of the AT89S8252 was about half the size of the cell on the AT89C2051. On the AT89S8252 both EEPROM and Flash had the same design. The way the cells are erased distinguishes the two types. • MROM: An MROM cell array was employed on both devices. The cell was programmed through metal 1 layer. No detailed analysis of this memory was performed since structures are the same as peripheral circuits.
-8-
PROCEDURE The devices were subjected to the following analysis procedures: External inspection Decapsulation Optical inspection Wirepull test SEM of passivation and assembly features Passivation removal and inspect metal Aluminum removal Delayer to poly and inspect Die sectioning (90° for SEM)* Measure horizontal dimensions Measure vertical dimensions Die material analysis
*Delineation of cross-sections is by silicon etch unless otherwise indicated.
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OVERALL QUALITY EVALUATION: Overall Rating: Normal DETAIL OF EVALUATION Package integrity
G
Package markings
G
Die placement
G
Wirebond placement
G
Wire spacing
G
Wirebond quality
G
Die attach quality
N
Dicing quality
N
Dicing method
Sawn (full depth)
Wirebond method
Thermosonic ball bonds using 1.2 mil gold wire.
Die surface integrity: Toolmarks (absence) Particles (absence) Contamination (absence) Process defects (absence) General workmanship Passivation integrity Metal definition Metal integrity Metal registration Contact coverage Contact registration
G G G G G G G NP* G G G
*Metal 1 aluminum thinning up to 90 percent. G = Good, P = Poor, N = Normal, NP = Normal/Poor
- 10 -
PACKAGE MARKINGS AT89C2051 TOP
BOTTOM
(Logo) AT89C2051 9642 12PC
6C203-1 9056F 1-F 6C9642
AT89S8252 TOP
BOTTOM
(Logo) AT89S8252 24PC 9709
6D0412-2 19552H 1 KOREA 6D9706
WIREBOND STRENGTH (AT89C2051)
Wire material: 1.2 mil diameter gold Die pad material: aluminum Sample #
1
# of wires pulled: Bond lifts: Force to break - high: - low: - avg.: - std. dev.:
15 0 19.0g 14.0g 16.1g 1.7
- 11 -
DIE MATERIALS Passivation:
Two layers of silicon-dioxide.
Metal 2 (AT89S8252 device only):
Aluminum with a titanium-nitride barrier.
Metal 1:
Aluminum with a titanium-nitride barrier. Metal 1 also employed a titanium-nitride cap on the AT89S8252 device.
Interlevel dielectric (AT89S8252 device only):
Two layers of silicon-dioxide.
Pre-metal dielectric:
BPSG glass.
- 12 -
HORIZONTAL DIMENSIONS
Note: All dimensions taken from the AT89C2051 device, except where noted. Die size:
4.7 x 3.8mm (187.5 x 152 mils) 6.1 x 5.2mm (240 x 206 mils) AT89S8252 18mm2 (28,500 mils2)
Die area:
31.7mm2 (49,440 mils2) AT89S8252 Min pad size:
0.1 x 0.11mm (4 x 4.5 mils)
Min pad window:
0.11 x 0.13mm (4.5 x 5 mils)
Min pad space:
6.7 mils
Min pad-to-metal:
12.5 microns
Min metal width:
2 microns
Min metal space:
1.5 micron
Min metal pitch:
3.6 microns
Min contact:
1.1 micron
Min poly width:
1.2 micron
Min gate length* - (N-channel):
1.2 micron
- (P-channel):
1.5 micron
Cell size (SRAM on AT89C2051):
474 microns2
Cell pitch (SRAM on AT89C2051):
22.3 x 21.3 microns
Cell size (EEPROM - AT89C2051):
32.5 microns2
Cell pitch (EEPROM - AT89C2051):
8.5 x 3.5 microns
Cell size (EEPROM - AT89S8252):
16.4 microns2
Cell pitch (EEPROM - AT89S8252):
6.3 x 2.6 microns
*Physical gate length.
- 13 -
VERTICAL DIMENSIONS Note: All dimensions taken from the AT89C2051 device, except where noted. Die thickness:
0.3 mm (11.5 mils)
Layers Passivation 2: Passivation 1: Metal 2 (AT89S8252) - aluminum: - barrier: Metal 1 (AT89C2051)- aluminum: - barrier: Interlevel dielectric (AT89S8252): Pre-metal dielectric: Oxide on poly 2: Poly 1: Poly 2: Local oxide: N+ S/D diffusion: P+ S/D diffusion: N-well:
0.8 micron 0.6 micron 1.0 micron 0.06 micron (approx.) 0.7 micron 0.06 micron (approx.) 1.3 micron (average) 0.55 micron (average) 0.15 micron 0.25 micron 0.4 micron 0.8 micron 0.4 micron 0.3 micron 5 microns (approx.)
- 14 -
INDEX TO FIGURES AT89C2051 PACKAGE PHOTOS AND X-RAY
Figures 1 - 2
PACKAGE ASSEMBLY
Figures 3 - 4
DIE LAYOUT AND IDENTIFICATION
Figures 5 - 7
PHYSICAL DIE STRUCTURES
Figures 8 - 19
MEMORY CELL STRUCTURES
Figures 20- 30
COLOR PROCESS DRAWING
Figure 31
AT89S8252 PACKAGE PHOTOS
Figure 32
DIE LAYOUT AND IDENTIFICATION
Figures 33 - 34
PHYSICAL DIE STRUCTURES
Figures 35 - 36
MEMORY CELL STRUCTURES
Figures 37 - 42
- ii -
Atmel AT89C2051
Integrated Circuit Engineering Corporation
RST
1
20
(RXD) P3.0
2
19
VCC P1.7
(TXD) P3.1
3
18
P1.6
XTAL2
4
17
P1.5
XTAL1
5
16
P1.4
(INT0) P3.2
6
15
P1.3
(INT1) P3.3
7
14
P1.2
(T0) P3.4
8
13
P1.1 (AIN1)
(T1) P3.5
9
12
P1.0 (AIN0)
10
11
P3.7
GND
Figure 1. Package photographs and pinout of the Atmel AT89C2051. Mag. 3x.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PIN 1
Figure 2. X-ray views of the package. Mag. 4x.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
Au
BOND PAD
Mag. 570x
Au
LEADFRAME
Mag. 500x Figure 3. SEM views of typical wirebonds. 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
DIE ATTACH ETCHED DURING DECAPSULATION PADDLE
Mag. 150x
EDGE OF PASSIVATION
Mag. 1100x Figure 4. SEM views illustrating die corner and edge seal. 60°
Atmel AT89C2051
Integrated Circuit Engineering Corporation
Figure 5. Whole die photograph of the Atmel AT89C2051. Mag. 44x.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
Figure 6. Optical views illustrating markings on the die surface. Mag. 320x.
Integrated Circuit Engineering Corporation
Figure 7. Optical views of die corners. Mag. 100x.
Atmel AT89C2051
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION 2 PASSIVATION 1
METAL
POLY GATE LOCAL OXIDE
PRE-METAL DIELECTRIC N+ S/D
silicon etch, Mag. 13,000x
PASSIVATION 2
PASSIVATION 1
PRE-METAL DIELECTRIC POLY
METAL
glass etch, Mag. 21,000x Figure 8. SEM section views of general structure.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
Mag. 3200x
Mag. 7500x Figure 9. Perspective SEM views illustrating overlay passivation coverage. 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION METAL
Mag. 6500x
PASSIVATION 2
PASSIVATION 1 ALUMINUM
BARRIER
Mag. 13,000x Figure 10. SEM section views illustrating metal line profiles.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
CONTACTS
METAL
POLY
POLY
Mag. 1600x
METAL
RESIDUAL GLASS
Mag. 3200x Figure 11. Topological SEM views illustrating metal patterning. 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
METAL
Mag. 3700x
ALUMINUM
BARRIER
Mag. 13,000x Figure 12. SEM views illustrating metal coverage. 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PRE-METAL DIELECTRIC
PASSIVATION 1
METAL
N+
Mag. 26,000x
PASSIVATION 2
PASSIVATION 1
METAL
90% THINNING POLY
LOCOS
Mag. 17,600x Figure 13. SEM section views illustrating metal contacts.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
POLY
Mag. 2400x
POLY
POLY GATE
POLY GATE
Mag. 4700x Figure 14. SEM views illustrating poly patterning. 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
POLY
Mag. 4400x N+
P+
POLY
POLY
Figure 15. SEM views illustrating poly coverage. 60°.
Mag. 20,000x
Mag. 20,000x
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION 2
PASSIVATION 1
METAL
N+ S/D
P SUBSTRATE
Mag. 13,000x
ALUMINUM BARRIER
PRE-METAL DIELECTRIC POLY GATE
N+ S/D GATE OXIDE
Mag. 26,000x Figure 16. SEM section views illustrating N-channel transistor.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION 2
PASSIVATION 1 METAL
P+ S/D
Mag. 13,000x
PRE-METAL DIELECTRIC
POLY GATE
P+ S/D
GATE OXIDE
Mag. 26,000x Figure 17. SEM section views illustrating P-channel transistor.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
N-WELL
P SUBSTRATE
Mag. 800x
PASSIVATION 2 PASSIVATION 1 METAL
PRE-METAL DIELECTRIC LOCAL OXIDE
STEP AT WELL BOUNDRY
Mag. 13,000x Figure 18. SEM section views illustrating well structure.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION 2 PASSIVATION 1
METAL
PRE-METAL DIELECTRIC
POLY
LOCAL OXIDE
Mag. 20,800x
PRE-METAL DIELECTRIC
POLY LOCAL OXIDE
BIRDSBEAK
Mag. 36,600x Figure 19. SEM section view illustrating birdsbeak.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT LINES
metal
POLY WORD LINES
unlayered Figure 20. Topological SEM views illustrating 6T SRAM array. Mag. 810x, 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
metal
POLY WORD LINES
unlayered Figure 21. Perspective SEM views illustrating 6T SRAM array. Mag. 1600x, 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT LINES
metal
POLY WORD LINES
unlayered Figure 22. Perspective SEM views illustrating 6T SRAM array. Mag. 3240x, 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
VCC
BIT
metal GND
BIT
VCC
2 3
1
unlayered GND
6
5 4
WORD
4P BIT
2P 6N
1N 5N
BIT
3N
Figure 23. Perspective SEM views illustrating 6T SRAM cell and schematic. Mag. 3200x, 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT LINE BIT LINE
metal
POLY 2 WORD LINES
unlayered Figure 24. Topological SEM views illustrating EEPROM array. Mag. 1620x, 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT LINE BIT LINE
metal
POLY 2 WORD LINES
unlayered Figure 25. Perspective SEM views illustrating EEPROM array. Mag. 3240x, 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT LINE
metal POLY 2 WORD LINE
POLY 2 PROGRAM LINE
unlayered Figure 26. Perspective SEM views illustrating EEPROM array. Mag. 8000x, 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
POLY 2 PROGRAM LINE
POLY 1
POLY 2 WORD LINE
Mag. 13,000x
POLY 2
FLOATING GATE (POLY 1)
Mag. 20,000x Figure 27. Perspective SEM views illustrating details of the EEPROM cell. Unlayered, 60°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
BIT
PGM
GND
WORD
BIT
Q2
Q1
PGM
WORD
BIT Q1
Q2
Figure 28. SEM views illustrating EEPROM cell and schematic. Mag. 6500x, 0°.
Atmel AT89C2051
Integrated Circuit Engineering Corporation
PASSIVATION METAL BIT LINE
Mag. 3240x
123 ONE CELL
PASSIVATION 2 PASSIVATION 1 METAL POLY 2 SELECT GATE
Mag. 13,000x POLY 2 POLY 1
N+ S/D
DENSIFIED OXIDE
PRE-METAL DIELECTRIC
POLY 2
Mag. 26,000x POLY 1 N+ S/D
TUNNEL OXIDE
GATE OXIDE
Figure 29. SEM cross section views of EEPROM cell (parallel to bit lines).
Atmel AT89C2051
Integrated Circuit Engineering Corporation
METAL BIT LINES
POLY 2 PROGRAM LINE
POLY 1 FLOATING GATE P SUBSTRATE
Mag. 6500x
PASSIVATION 2
PASSIVATION 1
METAL
POLY 2
POLY 1 LOCAL OXIDE
Mag. 13,000x Figure 30. SEM cross section views of EEPROM cell (perpendicular to bit lines).
Atmel AT89C2051
POLY 2
PRE-METAL DIELECTRIC
METAL
DENSIFIED OXIDE PASSIVATION 2 PASSIVATION 1
LOCAL OXIDE
,,,,,,,,,, ,,,,,,,,,, GATE OXIDE
N+ S/D
P+ S/D
P-WELL
N-WELL
Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate Figure 31. Color cross section drawing illustrating device structure.
Integrated Circuit Engineering Corporation
P SUBSTRATE
Atmel AT89S8252
Integrated Circuit Engineering Corporation
Figure 32. Package photographs of the Atmel AT89S8252. Mag. 1.7x.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
Figure 33. Whole die photograph of the Atmel AT89S8252. Mag. 44x.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
Mag. 400x
Mag. 500x Figure 34. Optical views illustrating markings on the die surface.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
METAL 2
METAL 1 METAL 2
Figure 35. Optical views illustrating metal 2 interconnect. Mag. 825x.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
PASSIVATION 2 PASSIVATION 1 METAL 2 METAL 1 POLY 2
Mag. 10,000x
P SUBSTRATE
METAL 1 POLY 2 GATES
Mag. 13,000x
P SUBSTRATE
PASSIVATION 2
PASSIVATION 1
METAL 2 METAL 1
Mag. 15,000x
LOCAL OXIDE
Figure 36. Glass etch section views illustrating general structure.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
Mag. 1600x POLY 2 PROGRAM LINE POLY 2 WORD LINES
Mag. 6500x Figure 37. Unlayered topological views illustrating EEPROM array on the AT89S8252 device. 0°.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
Mag. 3240x
Mag. 6500x
POLY 2 PROGRAM LINE
POLY 2 WORD LINE
Mag. 13,000x
Figure 38. Perspective SEM views illustrating EEPROM array on the AT89S8252 device. 60°.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
POLY 2
Mag. 13,000x POLY 1
POLY 2 NITRIDE
Mag. 26,000x POLY 1
POLY 2
NITRIDE
Mag. 52,000x
POLY 1 FLOATING GATE
Figure 39. Detailed views of the EEPROM cell.
Atmel AT89S8252
Integrated Circuit Engineering Corporation
METAL 1 BIT LINE
PASSIVATION POLY 2
POLY 1
Mag. 6500x
METAL 1 POLY 2 SELECT GATE
POLY 2
N+ S/D
TUNNEL OXIDE
POLY 1 FLOATING GATE
Mag. 13,000x Figure 40. SEM section views of EEPROM cell on the AT89S8252 device (parallel to bit lines).
Atmel AT89S8252
Integrated Circuit Engineering Corporation
METAL
POLY 2
POLY 1
N+
TUNNEL OXIDE
Mag. 26,000x
DENSIFIED OXIDE INTERPOLY DIELECTRIC POLY 2
POLY 1
TUNNEL OXIDE
GATE OXIDE
Mag. 52,000x Figure 41. Detailed SEM section views of EEPROM cell (parallel to bit lines).
Atmel AT89S8252
Integrated Circuit Engineering Corporation
NITRIDE
POLY 2
POLY 1
GATE OXIDE
POLY 2 NITRIDE
POLY 1
TUNNEL OXIDE
GATE OXIDE
Figure 42. Glass etch section views illustrating the ONO interpoly dielectric. Mag. 52,000x.
