50 MHz–1000 MHz Quadrature Demodulator AD8348 Integrated I/Q demodulator with IF VGA amplifier Operating IF frequency 50 MHz to 1000 MHz (3 dB IF BW of 500 MHz driven from RS = 200 Ω) Demodulation bandwidth 75 MHz Linear-in-dB AGC range 44 dB Third order intercept IIP3 +28 dBm @ min gain (FIF = 380 MHz) IIP3 –8 dBm @ max gain (FIF = 380 MHz) Quadrature demodulation accuracy Phase accuracy 0.5° Amplitude balance 0.25 dB Noise figure 11 dB @ max gain (FIF = 380 MHz) LO input –10 dBm Single supply 2.7 V to 5.5 V Power-down mode Compact 28-lead TSSOP package

APPLICATIONS QAM/QPSK demodulator W-CDMA/CDMA/GSM/NADC Wireless local loop LMDS

PRODUCT OVERVIEW The AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF), variable gain amplifier (VGA), and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseband frequencies. The baseband amplifiers have been designed to directly interface with dualchannel ADCs, such as the AD9201, AD9283, and AD9218, for digitizing and postprocessing. The IF input signal is fed into two Gilbert cell mixers through an X-AMP® VGA. The IF VGA provides 44 dB of gain control. A precision gain control circuit sets a linear-in-dB gain characteristic for the VGA and provides temperature compensation. The LO quadrature phase splitter employs a divide-by-two frequency divider to achieve high quadrature accuracy and amplitude balance over the entire operating frequency range.

FUNCTIONAL BLOCK DIAGRAM

ENBL 15

VREF

IMXO

IOFS

IAIN

IOPP

IOPN

14

8

13

6

4

3

BIAS CELL

VREF 5

VCMO

1

LOIP

28

LOIN

VCMO DIVIDE BY 2

IFIP 11

PHASE SPLITTER

IFIN 10

VGIN 17

GAIN CONTROL VCMO 18

19

24

MXIP MXIN ENVG

21

16

23

QXMO

QOFS

QAIN

25

26

QOPP QOPN

Figure 1.

Optionally, the IF VGA can be disabled and bypassed. In this mode, the IF signal is applied directly to the quadrature mixer inputs via the MXIP and MXIN pins. Separate I and Q channel baseband amplifiers follow the baseband outputs of the mixers. The voltage applied to the VCMO pin sets the dc common-mode voltage level at the baseband outputs. Typically VCMO is connected to the internal VREF voltage, but it can also be connected to an external voltage. This flexibility allows the user to maximize the input dynamic range to the ADC. Connecting a bypass capacitor at each offset compensation input (IOFS and QOFS) nulls dc offsets produced in the mixer. Offset compensation can be overridden by applying an external voltage at the offset compensation inputs. The mixers’ outputs are brought off-chip for optional filtering before final amplification. Inserting a channel selection filter before each baseband amplifier increases the baseband amplifiers’ signal handling range by reducing the amplitude of high level, out-of-channel interferers before the baseband signal is fed into the I/Q baseband amplifiers. The single-ended mixer output is amplified and converted to a differential signal for driving ADCs.

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

03678-0-001

FEATURES

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.

AD8348 TABLE OF CONTENTS AD8348—Specifications.................................................................. 3

Basic Connections...................................................................... 20

Absolute Maximum Ratings............................................................ 6

Power Supply............................................................................... 20

Pin Configurations And Functional Descriptions ....................... 7

Device Enable ............................................................................. 20

Equivalent Circuits ........................................................................... 9

VGA Enable ................................................................................ 20

Typical Performance Characteristics ........................................... 11

Gain Control ............................................................................... 20

VGA and Demodulator ............................................................. 11

LO Input ...................................................................................... 20

Demodulator Using MXIP and MXIN.................................... 14

IF Input ........................................................................................ 20

Final Baseband Amplifiers ........................................................ 15

MX Input ..................................................................................... 20

VGA/Demodulator and Baseband Amplifier......................... 16

Baseband Outputs ...................................................................... 21

Theory of Operation ...................................................................... 18

Output DC Bias Level ................................................................ 21

VGA.............................................................................................. 18

Interfacing to Detector for AGC Operation ........................... 21

Downconversion Mixers ........................................................... 18

Baseband Filters.......................................................................... 22

Phase Splitter............................................................................... 18

LO Generation ............................................................................ 23

I/Q Baseband Amplifiers ........................................................... 18

Evaluation Board ........................................................................ 23

Enable........................................................................................... 18

Outline Dimensions ....................................................................... 28

Baseband Offset Cancellation................................................... 18

ESD Caution................................................................................ 28

Applications..................................................................................... 20

Ordering Guide .......................................................................... 28

REVISION HISTORY Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8348 SPECIFICATIONS Table 1. VS = 5 V, TA = 25oC, FLO = 380 MHz, FIF = 381 MHz, PLO = –10 dBm, RS (LO) = 50 Ω, RS (IFIP and MXIP/MXIN) = 200 Ω, unless otherwise noted. Parameter OPERATING CONDITIONS LO Frequency Range IF Frequency Range Baseband Bandwidth LO Input Level VSUPPLY (VS) Temperature Range IF FRONT END WITH VGA Input Impedance Gain Control Range Maximum Conversion Gain Minimum Conversion Gain 3 dB Bandwidth Gain Control Linearity IF Gain Flatness Input P1dB Second Order Input Intercept (IIP2)

Third Order Input Intercept (IIP3)

LO Leakage Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Noise Figure Mixer Output Impedance Capacitive Load Resistive Load Mixer Peak Output Current

Condition

Min

External Input = 2× LO Frequency

100 50

50 Ω Source

–12 2.7 –40

Typ

75 –10

Max

Unit

2000 1000

MHz MHz MHz dBm V °C

0 5.5 +85

IFIP to IMXO (QMXO) ENVG = 5 V

VGIN = 0.2 V (Maximum Voltage Gain) VGIN = 1.2 V (Minimum Voltage Gain) VGIN = 0.4 V (+21 dB) to 1.1 V (–14 dB) FIF = 380 MHz ±5% (VGIN = 1.2 V) FIF = 900 MHz ±5% (VGIN = 1.2 V) VGIN = 0.2 V (Maximum Gain) VGIN = 1.2 V (Maximum Gain) IF1 = 385 MHz, IF2 = 386 MHz +3 dBm Each Tone from 200 Ω Source VGIN = 1.2 V (Minimum Gain) –42 dBm Each Tone from 200 Ω Source VGIN = 0.2 V (Maximum Gain) IF1 = 381 MHz, IF2 = 381.02 MHz Each Tone 10 dB below P1dB from 200 Ω Source VGIN = 1.2 V (Minumum Gain) Each Tone 10 dB Below P1dB from 200 Ω Source VGIN = 0.2 V (Maximum Gain) Measured at IFIP, IFIN Measured at IMXO/QMXO (LO = 50 MHz) Small Signal 3 dB Bandwidth LO = 380 MHz (LOIP/LOIN 760 MHz)

–2

Maximum Gain, from 200 Ω Source, FIF = 380 MHz

200||1.1 44 25.5 –18.5 500 ±0.5 0.1

Ω||pF dB dB dB MHz dB dB p-p

1.3 –22 +13

dB p-p dBm dBm

65

dBm

18

dBm

28

dBm

–8

dBm

–80 –60 75 ±0.5 0.25 10.75

dBm dBm MHz Degrees dB dB

+2

40 Shunt from IMXO, QMXO to VCMO Shunt from IMXO, QMXO to VCMO

Rev. 0 | Page 3 of 28

0 200

10 1.5 k 2.5

Ω pF Ω mA

AD8348 Parameter IF FRONT END WITHOUT VGA Input Impedance Conversion Gain 3 dB Output Bandwidth IF Gain Flatness Input P1dB Third Order Input Intercept (IIP3)

LO Leakage Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Noise Figure I/Q BASEBAND AMPLIFIER

Gain Bandwidth Output DC Offset (Differential) Output Common-Mode Offset Group Delay Flatness Input Referred Noise Voltage Output Swing Limit (Upper) Output Swing Limit (Lower) Peak Output Current Input Impedance Input Bias Current RESPONSE FROM IF AND MX INPUTS TO BASEBAND AMPLIFIER OUTPUT Gain

CONTROL INPUT/OUTPUTS VCMO Input Range VREF Output Voltage Gain Control Voltage Range Gain Slope Gain Intercept Gain Control Input Bias Current LO Inputs LOIP Input Return Loss

Condition From MXIP, MXIN to IMXO (QMXO) ENVG = 0 V, IMXO/QMXO Load = 1.5 kΩ Measured Differentially Across MXIP/MXIN

Min

FIF = 380 MHZ ±5% FIF = 900 MHZ ±5% IF1 = 381 MHz, IF2 = 381.02 MHz Each Tone 10 dB below P1dB from 200 Ω Source Measured at MXIP/MXIN Measured at IMXO, QMXO Small Signal 3 dB Bandwidth LO = 380 MHz (LOIP/LOIN 760 MHz, Single-Ended)

–2

From 200 Ω Source, FIF = 380 MHz From IAIN to IOPP/IOPN and QAIN to QOPP/QOPN, RLOAD = 2 kΩ Single-Ended to Ground 10 pF Differential Load LO Leakage Offset Corrected Using 500 pF Capacitor on IOFS, QOFS (VIOPP – VIOPN) (VIOPP + VIOPN)/2 – VCMO 0 MHz–50 MHz Frequency = 1MHz

–50 –75

Typ

Max

200||1.5 10.5 75 0.1 0.15 –4 14

Ω||pF dB MHz dB p-p dB p-p dBm dBm

–70 –60 75 ±0.5

dBm dBm MHz Degrees

+2

0.25 21

dB dB

20 125 ±12

dB MHz mV

±35 3 8

+50 +75

1 50||1 2

mV ns p-p nV/√Hz V V mA kΩ||pF µA

30.5 45.5 1.5

dB dB dB

VS –1 0.5

IMXO and QMXO Connected Directly to IAIN and QAIN, Respectively From MXIP/MXIN From IFIP/IFIN, VGIN = 0.2 V From IFIP/IFIN, VGIN = 1.2 V VS = 5 V VS = 2.7 V VGIN Linear Extrapolation Back to Theoretical Gain at VGIN = 0 V

LOIN AC-Coupled to Ground (760 MHz Applied to LOIP)

Rev. 0 | Page 4 of 28

0.5 0.5 0.95 0.2 –55 55

Unit

1 1 1 –50 61

4 1.7 1.05 1.2 –45 67

V V V V dB/V dB

1

µA

–6

dB

AD8348 Parameter POWER-UP CONTROL ENBL Threshold Low ENBL Threshold High Input Bias Current Power-Up Time Power-Down Time POWER SUPPLIES Voltage Current (Enabled) Current (Standby)

Condition

Min

Typ

Max

Unit

Low = Standby High = Enable

0 +VS – 1

VS/2 VS/2 2 45

1 +VS

V V µA µs

Time for Final Baseband Amplifiers to Be within 90% of Final Amplitude Time for Supply Current to be 0.1 µF) or an external voltage source to prevent the feedback loop from oscillating.

VCMO. This forms a high-pass response for the baseband signal path with a lower 3 dB frequency of f PASS =

1 2π × 2650 Ω × COFS

Alternatively, the user can externally adjust the dc offset by driving IOFS (QOFS) with a digital-to-analog converter or other voltage source. In this case, the baseband circuit will operate all the way down to dc (fPASS = 0 Hz). The integrator output current is only 50 µA and can be easily overridden with an external voltage source. The nominal voltage level applied to IOFS (QOFS) to produce a 0 V differential offset at the baseband outputs is 900 mV.

The feedback loop will be broken at dc if an ac-coupled baseband filter is placed between the mixer outputs and the baseband amplifier inputs. If an ac-coupled filter is implemented, the user must handle the offset compensation via some external means.

Rev. 0 | Page 19 of 28

AD8348 APPLICATIONS BASIC CONNECTIONS Figure 49 shows the basic connections schematic for the AD8348. J21 LO

LO

4

5

3

1

4 5

ETC1-1-13

T21 ETC1-1-13 3 1 C21 1000pF

R21 60.4Ω

1000pF

C22 1000pF

1000pF

60.4Ω

C51 100pF

J2I IOPP VREF

3 IOPN

QOPN 26

4 IOPP

QOPP 25

5 VCMO

ENVG 24

6 IAIN

R31 57.6Ω

+VS

R32 174Ω C31 1000pF

C54 0.1µF

LOIN 28

7 COM3

COM3 22

8 IMXO

QMXO 21

10 IFIN

MXIN 19

11 IFIP

MXIP 18

12 VPOS2

C53 100pF

J3Q QOPN

Figure 50. Differential LO Drive with Balun

J2Q QOPP

IF

+VS

SW12

Alternatively, the LO port can be driven single-ended without a balun (Figure 51). The LO signal is ac-coupled directly into the LOIP pin via an ac coupling capacitor and the LOIN pin is accoupled to ground. Driving the LO port single-ended will result in an increase in both quadrature phase error and LO leakage.

MX

QAIN 23

9 COM2 VPOS3 20

C32 1000pF

IFIP

1 LOIP

C55 100pF

C56 0.1µF

+VS R42 C43 1000pF 0Ω T41 ETK4-2T

C41 1µF

VGIN 17

LO

MXIP C42 1000pF

VGIN

1000pF C01 0.1µF C11 4.7µF

13 IOFS 14 VREF

QOFS 16 ENBL 15

C0Q 0.1µF

ENBL

1000pF 60.4Ω

+VS

SW11 DENBL

1 LOIP

LOIN 28

Figure 49. Basic Connections Schematic

POWER SUPPLY

03678-0-051

J3I IOPN

C52 0.1µF

LOIN 28

2 VPOS1 COM1 27

03678-0-064

+VS

03678-0-050

AD8348 1 LOIP

Figure 51. Single-Ended LO Drive.

The voltage supply for the AD8348, between 2.7 V and 5 V, should be provided to the +VPOSx pins and ground should be connected to the COMx pins. Each of the supply pins should be decoupled separately using two capacitors whose recommended values are 100 pF and 0.1 μF (values close to these may also be used).

The recommended LO drive level is between –12 dBm and 0 dBm. The LO frequency at the input to the device should be twice that of the desired LO frequency at the mixer core. The applied LO frequency range is between 100 MHz and 2 GHz.

DEVICE ENABLE

IF INPUT

To enable the device, the ENBL pin should be driven to +VS. Grounding the ENBL pin will disable the device.

The IF inputs have an input impedance of 200 Ω. A broadband 50 Ω match can be achieved via the use of a minimum loss L Pad. Figure 42 shows the S11 of the IF input with and without the L Pad. 1000pF 10 IFIN

Driving the voltage on the ENVG pin to +VS enables the VGA. In this mode, the MX inputs are disabled and the IF inputs are used. Grounding the ENVG pin will disable the VGA and the IF inputs. When the VGA is disabled, the MX inputs should be used.

57.6Ω IFIP

174Ω

11 IFIP 1000pF

03678-0-052

VGA ENABLE

Figure 52. Minimum Loss L Pad for 50 Ω IF Input

GAIN CONTROL When the VGA is enabled, the voltage applied to the VGIN pin sets the gain. The gain control voltage range is between 0.2 V and 1.2 V. This corresponds to a gain range between +25.5 dB and –18.5 dB.

LO INPUT

MX INPUT The mixer inputs MXIP and MXIN have a nominal impedance of 200 Ω and should be driven differentially. When driven from a differential source, the input should be ac-coupled to the source via capacitors, as shown in Figure 53.

For optimum performance, the local oscillator port should be driven differentially through a balun. The recommended balun is M/A-COM ETC1-1-13. The LO inputs to the device should be ac-coupled, unless an ac-coupled transformer is being used. For a broadband match to a 50 Ω source, a 60.4 Ω resistor should be placed between the LOIP and LION pins. Rev. 0 | Page 20 of 28

AD8348 LO

1000pF MXIN 19

4 5

MXIN

1:1 3 1

MXIP 1000pF

1000pF

03678-0-053

MXIP 18

60.4Ω

1000pF

AD8348 1 LOIP

LOIN 28

Figure 53. Differential Drive of MX Inputs +VS

If the MX inputs are to be driven from a single-ended 50 Ω source, a 4:1 balun can be used to transform the 200 Ω impedance of the inputs to 50 Ω while performing the required singleended-to-differential conversion. The recommended transformer is the M/A-COM ETK4-2T.

0.1µF

2 VPOS1 COM1 27

100pF

TO BASEBAND I ADC

VREF

3 IOPN

QOPN 26

4 IOPP

QOPP 25

5 VCMO

ENVG 24

6 IAIN

1.02kΩ

1000pF

TO BASEBAND Q ADC

+VS

QAIN 23

7 COM3

COM3 22

8 IMXO

QMXO 21

1.24kΩ

VCMO

MXIN 19 ETK4-2T MXIP 1000pF

MXIN 19

11 IFIP

MXIP 18

+VS

12 VPOS2

VGIN 17

100pF 100pF

BASEBAND OUTPUTS

VREF

The baseband amplifier outputs IOPP, IOPN, QOPP, and QOPN should be presented with loads of at least 2 kΩ (single-ended to ground). They are not designed to drive 50 Ω loads directly. The typical swing for these outputs is 2 V p-p differential (1 V p-p single-ended), but larger swings are possible as long as care is taken to ensure that the signals remain within the limits of the output swing (VS – 1 V and 0.5 V). To achieve a larger swing, it is necessary to adjust the common-mode bias of the baseband output signals. Increasing the swing can have the benefit of improving the signalto-noise ratio of the baseband amplifier output. When connecting the baseband outputs to other devices, care should be taken to ensure that the outputs are not heavily capacitively loaded (approximately 20 pF and above). Doing so could potentially overload the output or induce oscillations. The effect of capacitive loading on the baseband amplifier outputs can be mitigated by inserting series resistors (approximately 200 Ω).

OUTPUT DC BIAS LEVEL The dc bias of the mixer outputs and the baseband amplifier inputs and outputs is determined by the voltage that is driven onto the VCMO pin. The range of this voltage is typically between 500 mV and 4 V when operating with a 5 V supply. To achieve maximum voltage swing from the baseband amplifiers, VCMO should be driven at 2.25 V; this will allow for a swing of up to 7 V p-p differential (3.5 V p-p single-ended).

INTERFACING TO DETECTOR FOR AGC OPERATION

1000pF

0.1µF

1000pF

1000pF 0.1µF

100pF 1000pF

1000pF IF INPUT Zo = 200Ω

Figure 54. Driving the MX Inputs from a Single-Ended 50 Ω Source

The AD8348 can be interfaced with a detector such as the AD8362 rms-to-dc converter to provide an automatic signal leveling function for the baseband outputs.

10 IFIN

+VS

13 IOFS

QOFS 16

14 VREF

ENBL 15

100pF 100pF

+VS

AD8362 1 COMM ACOM 16 1nF

2 CHPF

VREF 15

3 DECL

VTGT 14

4 INHI

VPOS 13

5 INLO

VOUT 12

6 DECL

VSET 11

1nF 1nF 100pF

0.1µF

+VS

1µF

VSET

7 PWDN ACOM 10 0.1µF 8 COMM

CLPF 9

03678-0-055

MXIP 18

03678-0-066

1µF

9 COM2 VPOS3 20

Figure 55. AD8362 Configuration for AGC Operation

Assuming the I and Q channels have the same rms power, the mixer output (or the output of the baseband filter) of one channel can be used as the input of the AD8362. The AD8362 should be operated in a region where its linearity error is small. Also, a voltage divider should be implemented with an external resistor in series with the 200 Ω input impedance of the AD8362’s input. This will attenuate the AD8348’s mixer output so that the AD8362’s input is not overdriven. The size of the resistor between the mixer output and the AD8362 input should be chosen so that the peak signal level at the input of the AD8362 is about 10 dB down from the top of the AD8362’s dynamic range, which occurs at approximately 10 dBm. The other side of the AD8348’s baseband output should be loaded with a resistance equal to the series resistance of the attenuating resistor in series with the AD8362’s 200 Ω input impedance. This resistor should be tied to the source driving VCMO so that there is no dc current drawn from the mixer output.

Rev. 0 | Page 21 of 28

AD8348

Care should be taken to ensure that blockers (unwanted signals in the band of interest that get demodulated together with the desired signal) do not dominate the rms power of the AD8362’s input. This will cause an undesired reduction in the level of the mixer output. To overcome this, baseband filtering can be implemented to filter out the undesired signals. The signal to the AD8362 should then be taken after the filter. Figure 56 shows the effectiveness of the AGC loop in maintaining a baseband amplifier output amplitude with less than 0.5 dB of amplitude error over an IF input range of 40 dB while demodulating a QPSK modulated signal at 380 MHz. The AD8362 has the benefit of being insensitive to crest factor variations and as such will provide similar performance regardless of the modulation of the incoming signal. 3 QPSK

2

–10 –20

0 ERROR

100

–1

90

–2

80

–3

70 –55

–45

–35 –25 –15 –5 IFIP POWER INPUT (dBm, ZO = 200Ω)

5

–4

40 35

IMXO

C6 82pF

VCMO

TO AD8362 INPUT IF AGC LOOP IS USED

R2 100Ω

IAIN

AD8348

03678-0-056

L2 1.2µH C5 150pF

100

45

30 25 1

2

20 15 10 5 0

1

10 FREQUENCY (MHz)

Figure 59. Baseband Filter Group Delay

R1 60Ω

100

50

Baseband low-pass or band-pass filtering can be conveniently performed between the mixer outputs (IMXO/QMXO) and the input to the baseband amplifiers. Consideration should be given to the output impedance of the mixers (40 Ω).

L1 0.68µH

10 FREQUENCY (MHz)

1

Figure 58. Baseband Filter Response

BASEBAND FILTERS

C2 8.2pF

–50

–80

Figure 56. AD8348 Baseband Amplifier Output vs. IF Input Power with AD8362 AGC Loop

C1 4.7pF

–40

–70

GROUP DELAY (ns)

110

–30

–60

1

ERROR (dB)

120

03678-0-065

I CHANNEL VOLTAGE OUTPUT (IOPP–IOPN) (mV rms)

130

0

03678-0-057

–5.1dBm re 10kΩ

The frequency response and group delay of this filter are shown in Figure 58 and Figure 59.

03678-0-058

140

Figure 57 shows the schematic for a 100 Ω, fourth order elliptic low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source and load impedances of approximately 100 Ω ensure that the filter sees a matched source and load. This also ensures that the mixer output is driving an overall load of 200 Ω. Note that the shunt termination resistor is tied to the source driving VCMO and not to ground. This ensures that the input to the baseband amplifier is biased to the proper reference level. VCMO is not an output pin and must be biased by a low impedance source.

ATTENUATION (dB)

The level of the mixer output (or the output of the baseband filter) can then be set by varying the setpoint voltage fed to Pin 11 (VSET) of the AD8362.

Figure 57. Baseband Filter Schematic

Rev. 0 | Page 22 of 28

AD8348 LO GENERATION Analog Devices has a line of PLLs that can be used for generating the LO signal. Table 4 lists the PLLs together with their maximum frequency and phase noise performance.

The device is enabled by moving Switch SW11 (at the bottom left of the evaluation board) to the ENBL position. The device is disabled by moving SW11 to the DENBL position. If desired, the device can be enabled and disabled from an external source that can be fed into the ENBL SMA connector or the VENB test point, in which case SW11 should be placed in the DENBL position.

Table 4. ADI PLL Selection Table

ADI Model ADF4001BRU ADF4001BCP ADF4110BRU ADF4110BCP ADF4111BRU ADF4111BCP ADF4112BRU ADF4112BCP ADF4116BRU ADF4117BRU ADF4118BRU

Frequency FIN (MHz) 165 165 550 550 1200 1200 3000 3000 550 1200 3000

@ 1 KHz ΦN dBc/Hz, 200 kHz PFD –99 –99 –91 –91 –78 –78 –86 –86 –89 –87 –90

The IF and MX inputs are selected via SW12. The switch should be moved in the direction of the desired input.

ADI also offers the ADF4360 fully integrated synthesizer and VCO on a single chip that offers differential outputs for driving the local oscillator input of the AD8348. This means that the user can eliminate the use of the balun necessary for the singleended-to-differential conversion. The ADF4360 comes as a family of chips with six operating frequency ranges. One can be chosen depending on the local oscillator frequency required. Table 5 below shows the options available. Table 5. ADF4360 Family Operating Frequencies ADI Model ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7

board. A GND test point is conveniently provided next to the +VS test point for the return path.

For convenience, a potentiometer, R15, is provided to allow for changes in gain without the need for an additional dc voltage source. To use the potentiometer, the SW13 switch must be set to the POT position. Alternatively, an external voltage applied to either the test point or SMA connector labeled VGIN can set the gain. SW13 must be set to the EXT position when an external gain control voltage is used. The local oscillator signal should be fed to the SMA connector J21. This port is terminated in 50 Ω. The LO power input range is from –12 dBm to 0 dBm and at a frequency equal to double that of the IF/MX frequency. The IF input should be fed into the SMA connector IFIP. The VGA must be enabled when this port is used (SW12 in the IF position). The evaluation board is by default set for differential MX drive through a balun (T41) from a single-ended source fed into the MXIP SMA connector. To change to a differential driving source, T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in place of T41 to bridge the gap in the input traces. This will present a nominal differential impedance of 200 Ω (100 Ω each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN.

Output Frequency Range (MHz) 2150/2450 1800/2150 1550/1950 1400/1800 1150/1400 1000/1250 Lower frequencies set by external L

EVALUATION BOARD Figure 60 shows the schematic for the AD8348 evaluation board. Note that uninstalled components are indicated with the OPEN designation. The board is powered by a single supply in the range of 2.7 V to 5.5 V. Table 6 details the various configuration options of the evaluation board. Table 7 shows the various jumper configurations for operating the evaluation board with different signal paths.

The baseband outputs are made available at the IOPP, IOPN, QOPP, and QOPN test points and SMA connectors. These outputs are not designed to be connected directly to 50 Ω loads and should be presented with loads of approximately 2 kΩ or greater. The dc bias level of the baseband amplifier outputs are by default tied to VREF through LK11. If desired, the dc bias level can be changed by removing LK11 and driving a dc voltage onto the VCMO test point.

Power to operate the board can be fed to a single +VS test point located near the LO input port at the top of the evaluation

Rev. 0 | Page 23 of 28

AD8348 J21 LO

+VS

C52 0.1µF

4 5

C51 100pF

IOPN

J3I IOPN

GND T21 ETC1-1-13 QOPN

3 1

GND

C9I OPEN

R5I 0Ω

IOPP

C8I OPEN

R4I 0Ω

C21 1000pF

R21 60.4Ω

C22 1000pF

R5Q 0Ω

C9Q OPEN

GND

R4Q 0Ω

C8Q OPEN

QOPP

J3Q QOPN

AD8348

J2I IOPP

1 LOIP

LOIN 28

J2Q QOPP

2 VPOS1 COM1 27 3 IOPN

C10I 0Ω

LK2I

R2I OPEN

C7I OPEN

C13 0.1µF

LK4I

IMXO L3I OPEN

L2I OPEN

L1I OPEN

LK3I

C3I OPEN

C2I OPEN

C1I OPEN

LK1I

C6I OPEN

C5I OPEN

C4I OPEN

4 IOPP

QOPP 25

5 VCMO

ENVG 24

6 IAIN

R1I OPEN

R31 R32 57.6Ω 174Ω C31 1000pF C54 0.1µF

C53 100pF

QAIN 23

7 COM3

COM3 22

8 IMXO

QMXO 21

L1Q OPEN

L2Q OPEN

L3Q OPEN

LK1Q

C1Q OPEN

C2Q OPEN

C3Q OPEN

R1Q OPEN

LK5I

MXIP 18

12 VPOS2

VGIN 17

13 IOFS

QOFS 16

14 VREF

ENBL 15

C4Q OPEN

VREF

ENBL

R11 49.9Ω DENBL

IOFS

LK2Q

C7Q OPEN

R2Q OPEN VCMO

+VS

R44 OPEN

R42 C43 1000pF 0Ω

MXIN

T41 ETK4-2T

R43 OPEN LK5Q

C11 4.7µF

C12 0.1µF

POT

QOFS

C0I 0.1µF

Figure 60. Evaluation Board Schematic

Rev. 0 | Page 24 of 28

C0Q 0.1µF

C42 R41 1000pF OPEN

R14 10kΩ

SW13 SW11

J1Q QMXO

C10Q 0Ω

MXIP

VENB ENBL

C6Q OPEN

C41 1µF

+VS

R12 10kΩ

C5Q OPEN

C55 C55 100pF 0.1µF

MXIN 19

11 IFIP

QMXO

LK3Q

9 COM2 VPOS3 20

C32 1000pF

VCMO

LK4Q

10 IFIN

+VS

R3Q 49.9Ω

LK11

VCMO

IFIP

MX SW12

R3I 49.9Ω

J1I IMXO

IF

EXT R13 OPEN

R15 10kΩ POT VGIN 03678-0-059

VCMO

+VS

QOPN 26

03678-0-060

AD8348

03678-0-061

Figure 61. Evaluation Board Top Layer

Figure 62. Evaluation Board Top Silkscreen

Rev. 0 | Page 25 of 28

03678-0-062

AD8348

03678-0-063

Figure 63. Evaluation Board Bottom Layer

Figure 64. Evaluation Board Bottom Silkscreen

Rev. 0 | Page 26 of 28

AD8348 Table 6. Evaluation Board Configuration Options Component +VS, GND SW11, ENBL

SW13, R15, VGIN

SW12

IFIP, R31, R32 MXIP, MXIN T41, R41, R42, C42, C43

LK11, VCMO

C8, C9, R4, R5 (I and Q) C10 (I and Q)

C1–C7 R1, R2 L1–L3 (I and Q) LK5 (I and Q)

Function Power Supply and Ground Vector Pins. Device Enable: Place SW11 in the ENBL position to connect the ENBL pin to +VS. Place SW11 in the DENBL position to disable the device by grounding the pin ENBL through a 50 Ω pull-down resistor. The device may also be enabled via an external voltage applied to ENBL or VENB. Gain Control Selection: With SW13 in the POT position, the gain of the VGA can be set using the R15 potentiometer. With SW13 in the EXT position, the VGA gain can be set by an external voltage to the SMA connector VGIN. For VGA operation, the VGA must first be enabled by setting SW12 to the IF position. VGA Enable Selection: With SW12 in the IF position, the ENVG pin is connected to +VS and the VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the MX position, the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used when SW12 is in the MX position. IF Input: The single-ended IF signal should be connected to this SMA connector. R31 and R32 form an L Pad that presents a 50 Ω termination to the input. Mixer Inputs: These inputs can be configured for either differential or single-ended operation. The evaluation board is by default set for differential MX drive through a balun (T41) from a single-ended source fed into the MXIP SMA connector. To change to a differential driving source, T41 should be removed along with Resistor R42. The 0 Ω resistors R43 and R44 should be installed in place of T41 to bridge the gap in the input traces. This will present a nominal differential impedance of 200 Ω (100 Ω each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. Baseband Amplifier Output Bias: Installing LK11 connects VREF to VCMO. This sets the bias level on the baseband amplifiers to VREF, which is equal to approximately 1 V. Alternatively, with LK11 removed, the bias level of the baseband amplifiers can be set by applying an external voltage to the VCMO test point. Baseband Amplifier Outputs and Output Filter: Additional low-pass filtering can be provided at the baseband output with these filters. Mixer Output DC Blocking Capacitors: The mixer outputs are biased to VCMO. To prevent damage to test equipment that cannot tolerate dc biases, C10 is provided to block the dc component, thus protecting the test equipment. Baseband Filter: These components are provided for baseband filtering between the mixer outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high and the filter termination impedance is set by R2. See Table 7 for the jumper settings. Offset Compensation Loop Disable: Installing these jumpers will disable the offset compensation loop for the corresponding channel.

Table 7. Filter Jumper Configuration Options Condition xMXO to xAIN Direct xMXO to xAIN via Filter xMXO to J1x Direct, xAIN Unused xMXO to J1x via Filter, xAIN Unused Drive xAIN from J1x

LK1x

LK2x

LK3x

•

• •

• • •

LK4x

• • •

Rev. 0 | Page 27 of 28

Default Condition Not Applicable SW11 = ENBL

SW2 = POT

SW12 = IF

R31 = 57.6 Ω R32 = 174 Ω T41 = M/A-COM ETK4-2T R41, C42, C43 = OPEN R42 = 0 Ω

LK11 Installed

R4, R5 = 0 Ω C10 = 0 Ω

All = OPEN

LK5x = OPEN

AD8348 OUTLINE DIMENSIONS 9.80 9.70 9.60

28

15

4.50 4.40 4.30 1

6.40 BSC

14

PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10

0.30 0.19

1.20 MAX

SEATING PLANE

0.20 0.09

8° 0°

0.75 0.60 0.45

COMPLIANT TO JEDEC STANDARDS MO-153AE

Figure 65. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE AD8348 Products AD8348ARU AD8348ARU-REEL7 AD8348-EVAL

Temperature Range –40°C to +85°C –40°C to +85°C

Package Description Thin Shrink Small Outline Package (28-Lead TSSOP) 7” Tape and Reel Evaluation Board

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03678-0-8/03(0)

Rev. 0 | Page 28 of 28

Package Option RU-28 RU-28