ESSDERC 2016 Joint
Workshop on:
“III-V compound semiconductor technology and devices for advanced nanoelectronics”
300mm high-mobility layer -on insulator substrates (III-V-OI) Julie Widiez, M. Martin, S. Sollier, T. Baron, F. Mazen, S. Favier, A. Salaun, S. Arnaud, S. David, E. Beche, H. Grampeix, C. Veytizou, J.-M. Hartmann, V. Loup, P. Besson, C. Figuet, C. Tempesta, L. Ecarnot, C. Reita
[email protected]
Julie WIDIEZ Lausanne, Sept. 12, 2016
Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Outline INTRODUCTION - FDSOI context - The Smart CutTM technology - Our research fields SPECIFIC STUDIES FOR III-V-OI SUBSTRATE FABRICATION - 300 mm III-V epitaxy developments - Splitting in the InP epitaxial layer - Direct bonding with Al2O3 layer 300 mm III-V-OI SUBSTRATE - Final characterizations - layer transfer on pMOSFETs substrate
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction: the scaling issue Moore’s law: ● For similar chip cost • • •
More functionalities (transistors) Less power per transistor Faster processing
Planar bulk CMOS reaching its limits at 20 nm Can’t go further: 1. Technical challenges: leakage, variability and short channel effects 2. Cost efficiency challenge
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction: the scaling issue
M. Vinet, Leti workshop at IEDM, Washington 2013
-
28/14/10nm nodes : planar FD devices on SOI (FDSOI) AND non planar devices (FinFET) < 10nm nodes : non planar option AND high-mobility material options Our research fields (advanced substrate technologies) : SOI AND high-µ-OI substrates using the Smart CutTM technology
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : the history of Smart CutTM Blistering of materials implanted with « gas» ions has been observed and studied for decades : ●
Potential delamination of nuclear reactors walls (Kaminski et.al, 1971) (1)
●
In silicon, fundamental studies of implantation pioneers (Ligeon et. al , 1976)(2)
Blisters and exfoliated zones at the Si surface after anneal (500°C) or asimplanted (for high fluence condition) E = 10 – 60 keV H+ dose : 5E16 to 1,5E17 at/cm² (1) (2)
Kaminski et.al. IEEE Trans. Nucl. Science (1971). Ligeon et.al. Radiation Effects 27, p 129 (1976).
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : the history of Smart CutTM Blistering of materials implanted with « gas» ions has been observed and studied for decades : ●
Potential delamination of nuclear reactors walls (Kaminski et.al, 1971) (1)
●
In silicon, fundamental studies of implantation pioneers (Ligeon et. al , 1976)(2)
1991 : Smart CutTM invention by M. Bruel in LETI (3)
(3)
●
Bonding of the implanted wafer to a stiffener that prevent blistering
●
fracture propagation at the wafer scale
●
Transfer a thin layer of crystalline material from a donor substrate to another substrate
M.Bruel Electronics letters 31, p1201, 1995.
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : Smart CutTM, a versatile technique A generic way to transfer thin crystalline layers onto a foreign substrate For More Moore applications : top layer/buried oxide/handle substrate can be tuned to optimize performances
SiCOI (2”)(1)
GaAs on Si (2”)(2)
InP on Si (2”)(3)
GaN on sapphire (2”)(4)
and others…… (1) L. Di Cioccio et al., Elect. Lett. 32 p1144 (1996) (2) E. Jalaguier et al., Electron Lett. 34,p408 (1998) (3) E. Jalaguier et al., PDB 4, p 26 (1999). (4) A. Tauzin et al., ECS PV 2005-02, p119 (2005) (5) C. Deguet et al. Electronics Letters 42, p415 (2006) (6) JS Moulet et. al, IEDM 2008, p 679 (2009)
LiNbOI (3”)(6)
GeOI (8”)(5) Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : Smart CutTM, a versatile technique A generic way to transfer thin crystalline layers onto a foreign substrate For More Moore applications : top layer/buried oxide/handle substrate can be tuned to optimize performances
LiNbOI (3”)(6)
GeOI (8”)(5) Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : the context Device dimensions are reaching their limits performances more and more materials driven High-k, metal gate, SiGe channel for pFET already introduced More and more interest in high-mobility materials for the channel
S. Takagi et al., Jpn. J. Appl. Phys. 54, 06FA01 (2015)
Ge and III-V : high permittivity and low band-gap higher sensitivity to SCE Ge : good candidate for high-µ p and n-channel The successful introduction of Ge/III-V materials requires thin films In0.53Ga0.47As (lattice match InP) : good candidate for n-channel High-µ-OI offers electrostatic benefits, large diameter wafer, co-integration with Si Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : III-V, 2 ways of integration III-V-OI approach
M. Yokoyama et al. (S. Takagi), IEEE ELECTRON DEVICE LETTERS VOL. 32, NO. 9, SEPTEMBER 2011
« 3D » approach, FinFET
M. Radosavljevic et al., IEDM10-126 - 129, Intel
Julie WIDIEZ Lausanne, Sept. 12, 2016
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V. Djara et al. (IBM Zurich), IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 2, FEBRUARY 2016
GAA NWFET
N. Waldron et al., IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 11, 2014
Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : InGaAs-OI background
• • •
• • • •
InP substrate III-V /Si wafers bonding InP substrate removing
wafer scalability 8’’ demonstration The university of Tokyo [4] IBM Zürich Research Lab. [5] Expensive process
• • •
The university of Tokyo [1-2] IBM Zürich Research Lab. [3]
4’’ maximum Expensive process [1] Yokoyama et al. VLSI 2009, [2] Kim et al. VLSI 2014, [3] Czornomaz et al. IEDM 2013 [4] Irisawa et al., VLSI 2014, [5] Daix et al., APL 2014.[6] Czornomaz et al. IEDM 2012
• • • •
12’’ Si substrate III-V epitaxy wafers bonding Smart CutTM technology
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Si substrate III-V epitaxy wafers bonding Si+III-V epi donor removing
InP substrate wafers bonding Smart CutTM technology 4’’ maximum Reclaim of the bulk InP
H+ implant
Bulk InP
IBM Zürich Research Lab. [6]
THIS WORK
wafer scalability 12’’ demonstration Reclaim of the Si/III-V donor substrate
Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : Our work 300mm III-V-OI substrate fabrication
Reusable donor
300mm Si wafers
H+ implantation
InP
GaAs Si
III-V (GaAs/InP/InGaAs) epitaxy 20nm Al2O3 deposition (TMA first) 150nm SiO2 deposition / 600°C degassing annealing H+ implantation in InP
Bonding interface
SiO2 Thermal oxidation
300mm Si wafers
CMP and cleaning surface preparation Direct bonding Splitting : 350°C annealing InP wet etching
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Introduction : Our work Transfer of III-V on pFETs substrate 300mm Si wafers III-V layer –OI nFETs
InGaAs
SiGe layer –OI pFETs
Final 3D structure
III-V (GaAs/InP/InGaAs) epitaxy 20nm Al2O3 deposition (TMA first) 150nm SiO2 deposition / 600°C annealing H+ implantation
Oxide deposition SiO2 300 mm processed SiGe-OI pMOSFETs substrate
CMP and cleaning surface preparation SiO2//SiO2 direct |bonding 13 Splitting : 350°C annealing InP wet etching
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Outline INTRODUCTION - FDSOI context - The Smart CutTM technology - Our research fields SPECIFIC STUDIES FOR III-V-OI SUBSTRATE FABRICATION - 300 mm III-V epitaxy developments - Splitting in the InP epitaxial layer - Direct bonding with Al2O3 layer 300 mm III-V-OI SUBSTRATE - Final characterizations - layer transfer on pMOSFETs substrate
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Challenges : How to obtain III-V layer on 300 mm Si substrates ? Lattice mismatch (Si-GaAs 4%, Si-InAs et GaSb >10%) ● Crystalline defects (dislocation, stacking faults…) Polarity ● Antiphase domains Thermal expansion coefficient limits the total thickness before cracks appearing ● Limit the total thickness of III-V layers
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
15
300mm III-V epitaxy III-V direct epitaxy on Si III-V epitaxy with buffer engineering
S. Chen et al., NATURE PHOTONICS, VOL 10, MAY 2016
J.Z. Li et al., APL 91, 021114, 2007
Aspect ratio trapping
J.Z. Li et al., APL 91, 021114, 2007
Using lateral overepitaxy L. Czornomaz et al., 2015 Symposium on VLSI Technology Digest of Technical Papers, T172 Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Results
III-As epitaxy on nominal blanket Si (100) for 300mm InGaAs-OI substrate fabrication ● Roughness is an issue for layer transfer (< 1 nm) ● Thin GaAs buffer optimisation – no APB ● Growth of InGaAs 53% In, thickness = 35 nm
III-V epitaxy scheme ● 300mm Si(100) wafers ● Si native oxide removed using NF3/NH3 remote plasma ● GaAs (400nm) / InP (300nm) buffer layers ● InGaAs layer
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy 300 mm MOCVD III-V Applied Materials cluster tool
SiCoNi™ cleaning module MOCVD Chamber ● TBAs ● TBP ● TMGa ● TMIn ● TMAl
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy GaAs/Si(100) 300 mm µm
AFM
µm
APBs nucleated on the edges of the silicon monoatomic steps RMS roughness is about 2 nm due to APB, Solution : form double steps surfaces Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Si (100) double steps surface
Si(100) with offcut angle >2° leads to double steps formation
Handbook of crystal growth, Thin film and epitaxy, 2nd edition (2015)
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy GaAs/Si(100) 300 mm Standard nominal Si(001) microelectronic wafer (0.1° - 0.5° offcut) Si surface preparation Cleaning + annealing
GaAs/Si(100)
AFM 2x2 µm²
AFM 5x5 µm² Thickness = 140nm
RMS roughness = 0.6nm
Step height=0,28nm Double steps
Nominal Si(001) surface preparation enables double steps formation and prevent APBs nucleation Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
21
300mm III-V epitaxy TEM analysis
Threading dislocation density with t = 600 nm ≈ 109 cm-2 Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Improvement of electrical properties 250nm GaAs:Si(7x1017cm-3) Active layer with APBs
250nm GaAs:Si(7x1017cm-3) Active layer without APBs
400nm GaAs buffer
400nm GaAs buffer Without APBs (from 100nm thick)
With APBs
VS
Si(001)
Si(001)
Hall effect measurements @Room Temperature
R.Alcotte et al. APL Materials 4(4):046101 · April 2016
Electron mobility 10 x higher without APBs Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Improvement of electrical properties 400nm GaAs:Si (7x1017cm-3)
400nm GaAs:Si (7x1017cm-3)
VS
With APBs
Si(001)
Si(001)
µPL @ RT GaAs with APBs APBs-free GaAs
R.Alcotte et al. APL Materials 4(4):046101 · April 2016
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Without APBs
Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
PL intenisty of GaAs without APBs = 3x PL intensity of GaAs with APBs The PL peak without APBs is 40% narrower than with APBs
Directly correlated to the APBs acting as non radiative recombination centers www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy InGaAs/InP buffer GaAs buffer/Si(100) Si(100)/GaAs/InP σ = 1.2 nm PV=9nm
Si(100)/GaAs/InP/In0,53Ga0,47As σ = 2.1 nm PV=17nm 10.00 nm
15.00 nm
5
µm
µm
5
4
3
3
Y[µm]
4
2
2 1
1
0
0 0
1
2
3
4
5
0
0.00 nm
µm
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2
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4
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0.00 nm
µm
Optimization of InGaAs layers
1 µm Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy STEM/TEM characterizations
TEM image
Julie WIDIEZ Lausanne, Sept. 12, 2016
HR-TEM image
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
300mm III-V epitaxy Final results: InGaAs growth on nominal Si(001)
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Outline INTRODUCTION - FDSOI context - The Smart CutTM technology - Our research fields SPECIFIC STUDIES FOR III-V-OI SUBSTRATE FABRICATION - 300 mm III-V epitaxy developments - Splitting in the InP epitaxial layer - Direct bonding with Al2O3 layer 300 mm III-V-OI SUBSTRATE - Final characterizations - layer transfer on pMOSFETs substrate
Julie WIDIEZ Lausanne, Sept. 12, 2016
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Joint SINANO, COMPOSE3 and III-V-MOS Workshop at ESSDERC 2016
www.iii-v-mos-project.eu www.compose3.eu www.sinano.eu
Fracture in the InP epi layer
No previous work of fracture in InP epitaxial layer Publications on fracture in bulk InP fracture dependent on the implantation temperature ● T < 0°C [1] ● 80°C
