Integrated Ferroelectrics

ISSN: 1058-4587 (Print) 1607-8489 (Online) Journal homepage: http://www.tandfonline.com/loi/ginf20

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices Dongseok Kang , Soonhong Ahn , Yonghan Roh , Sungjin Jun , Jaichan Lee & Donggeun Jung To cite this article: Dongseok Kang , Soonhong Ahn , Yonghan Roh , Sungjin Jun , Jaichan Lee & Donggeun Jung (2001) Hysteresis caused by defects in buffer layer of metal-ferroelectricinsulator-semiconductor (MFIS) devices, Integrated Ferroelectrics, 40:1-5, 245-254, DOI: 10.1080/10584580108010848 To link to this article: http://dx.doi.org/10.1080/10584580108010848

Published online: 19 Aug 2006.

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Inregrued Fwiodecmics. 2001. Vol. 40. pp. 245-2SJ Reprints availahlr dircctly from the publisher Photocopyinp prrmillcd by licensc' only

D 2001 Taylor & Francis

Hysteresis Caused by Defects in Buffer Layer of MetalFerroelectric-Insulator-Semiconductor (MFIS) Devices

DONGSEOK KANG~.SOONIJONG AHN~,YONGHAN R O H ~ SUNGJIN JUN~.JAICHAN LEE^, DONGGEUN JUNG~ aSchool of Electrical and Computer Engineering, Sungkyunkwan University.

Suwon, 440-746, Korea, 'Department o f Materials Engineering, C

Sungkyunkwan University. Suwon, 440-746, Korea, Department o f Physics, Brain Korea 21 Physics Research Division. and Institute o f Basic Science, Sungkyunkwan University. Suwon. 440-746, Korea (Received Murch 14, 2001; htfinul,form August 20, 2001)

We have investigated the roles of buffer layer in the PtlSBT-Y20,ip-Si

(MFIS) capacitors. We found that the insertion of Y,O, buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However. negative charges with the effective density of 3.21 x 1 O"/cm' were generated due to the additional process step for Y,O, deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition. we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gatebias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y,O, buffer layer minimize the charge injection. the shift of the hysteresis loops was asymmetrical.

Kejii~or.d..r: nonvolatile memory MFIS: SBT: Y,O;; domain pinning

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INTRODUCTION Metal-ferroelectric-semiconductor field effect transistors (MFSFETs) have been extensively studied due to their attractive properties such as nonvolatile ability and low power consumption. It has been known, however, that the stable ferroelectric-Si interfaces are very difficult to obtain. Consequently, the insertion of buffer layer between the Si substrate and ferroelectric layer (i.e., MFISFETs) has been suggested to improve the interfacial properties, as well as leakage characteristics. Although the roles of buffer layer become more important, the experimental results which may possibly correlate the defects in buffer layer to the reliability of MFIS devices have not bcen fully explored. Recently. several research groups reported the asymmetrical increase of a memory window (AV) as a function of a sweeping gate voltage in MFISFETs [I-51. For example. the capacitance-voltage (C-V) curves of the MFIS capacitors only shift to the negative gate voltage during the forward sweep from inversion to accumulation. This phenomenon raises the question whether observed asymmetrical increase of the memory window is due to the enhanced coercive field. In this work. we investigate the asymmetrical increase of the memory window in view of a domain pinning caused by charged defects in buffer layer.

EXPERIMENTAL Samples were fabricated from 4’, 4 to 6 Sb-cm (100) p-type Si substrates. After cleaning the Si substrate using a standard RCA method. Y,O, buffer layer was deposited by a reactive sputtering method. The thickness of Y,O, used in this work was 150 A: Note that the electrical characteristics did not change due to the thickness of Y,O, LIPto 300 A. A pure yttrium metal target (99.99%) was used for sputtering in O2

ambient. and the flo\\ ratio of Ar to O2 was 4. The SBT films with

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thickness of 3500 A were deposited on YlO; using a metal organic deposition (MOD) method followed by 02 annealing at 800 "C for 1 hr.

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To investigate the roles of buffer layer, the SBT films were also deposited directly on the Si substrate. The shadow mask was used to form the Pt gate by sputtering followed by the formation of substrate ohmic contact. The gate area was 7x10.' cm2. and the schematic of the MF(1)S capacitors used in this work is shown in Fig. 1.

FIGURE 1

Cross-sectional view of the MF(I)S capacitors.

The electrical characteristics of MFIS capacitors were analyzed using the measurement system coiisisted of a Boonton 7200 C-V meter, a HP4140B pA meter, the current and voltage sources. The high frequency (i.e., 1 MHz) C-V technique using the Boonton 7200 was employed to measure the shift of MF(I)S capacitors. A procedure for a low field stress test employed in this work has been described elsewhere 161. Stated briefly. it involves the application of a low electric field to the gate of the MFIS capacitors for a time on the order of minutes during which flatband voltage (V,) is measured periodically. The sign of the electric field is changed periodically, typically several times during an experiment. The Vtb shifts were measured after disconnecting the applied voltage from the samples.

RESULTS AND DISCUSSION The data shown in Fig. ?(a) and (b) represent the hysteresis loops

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obtained from the PtISBTISi and Pt/SBT/Y203/Si capacitors, respectively. The clockwise hysteresis loops were observed, suggesting

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that the ferroelectric polarization controls the Si surface potential. Interestingly, the increase of the memory window depends on the presence of buffer layer (i.e.. YzOi). That is, the insertion of buffer layer results in the asymmetrical shifi of the memory window as the gate voltage increases.

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FIGURE 2

Increase of the memory window as a function of gate

voltage in the Pt/SBT/Si (a) and the Pt/SBT-Y?O;/Si capacitor (b). In Fig. 2(b). the oxide capacitance was reduced due to the

insertion of YIO; buffer layer. I n addition. the hysteresis curves were shifted to the positive gate voltage. suggesting that an additional process

HYSTERESIS CAUSED BY DEFECTS IN MFIS DEVICES

[I64711249

step for depositing buffer layer introduces negative charges. The

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effective density of trapped charges can be calculated by the following eauat ion:

where C,, is the oxide capacitance, AV, is the flatband voltage shift, and A is the gate area. The calculated density was 3.21x101'/cm'. A comparison of the data shown in Fig. 2(a) and (b) therefore suggests that the negative charging caused by insertion of the buffer layer is responsible for the asymmetrical increase of the memory window. Figure 3 illustrates a model for the asymmetrical increase of the memory window. During the forward sweep from inversion to accumulation. the polarization in the SBT film will be aligned toward the ferroelectric/buffer layer interface as shown in Fig. 3(a). In this case, the negatively charged defects in the buffer layer cause a little effect on the domain switching. Therefore the surface potential at the buffer layerSi interface increases if positive gate voltage changes from +2 to +4 V. causing the shift of the hysteresis curves toward the negative gate bias. On the other hand. parts of the domain walls will be pinned due to the negatively charged defects in the buffer layer during the backward sweep from accumulation to inversion. Since only a partial switching is allowed in this case due to the domain pinning, the band bending is less dependent on the applied gate voltage (i.e., charge screen effect). This phenomenon thus induces the preferential domain switching and the asymmetrical increase of the memory window. To clarify the suggested model, the hysteresis curves of the Pt/SBT-Y?O:/Si capacitors were measured at various ramp rates, and the results are presented in Figure 4. As is clearly shown in Fig. 4, the hysteresis curves were shifted toward the negative gate voltage when the ramp rate uas reduced. Recently. Li et al. [7] reported border traps in ferroelectric layer can exchange the electrons b i t h the Si substrate if the ramp rate is sufficiently slom ( 1 8 0 mV/s). The charge injection then

2W/( 16481

DONGSEOK KANG er (11

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causcs thc counterclockwise hysteresis loops in the p-Si subsirate, resulting in the reduced memory window caused by the ferroelectric polarization. The data shown in Fig. 4. however, show the hystcresis loops caused by the ferroelectric polarization only (i.e., clockwise hysteresis loops). Further, the width of memory window is same. within experimental error, even at thc ramp rate of 50 mV/s. Therefore. the effect of charge injection from the Si substrate must be excludcd. This is duc to the fact that charge injection was effectively prohibited due to the presence of 15-30 nm Y?O1buffer. Since the charge hjection was cxcluded for a possible cause of the hysteresis shift, we suggest that the data sh0w.n in Fig. 1 may be caused by the transport of the mobile positivc charge (e.g.. defect containing oxygen vacancies (81) according to the applied gate bias. For example. the mobile positive charges shift toward the fi.rroelectriclbuffer layer interface if the ramp rate is lowered, causing the negative shift of the hysteresis loops.

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FIGURE 3 The model for the asymnietrical increase of the nicmor!’ window i n thc I’t/SBT-Y4~JSicapacitor.

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HYSTERESIS CAUSED BY DEFECTS IN MFIS DEVICES

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FIGURE 4 The hysteresis loops measured at the different ramp rate in the Pt/SBT-Y103/Sicapacitor. Figure 5 shows the typical characteristics of the flatband voltage shifts as a function of a stressing time. The data shown in Fig. 5(a) and (b) were obtained from the samples without and with YzO;. respectively. The insets show the corresponding hysteresis curves measured before and after +3V bias stress for 30 minutes. The data shown in Fig. 5 represent two important facts. First, the memory window caused by the ferroelectric polarization (shown as clockwise hysteresis loop) did not change, consistent with the results of Fig. 4. Again, this observation supports the idea that the charge injection is minimal in our current sample. Second. the shift of the hysteresis loops in the PtISBTISi capacitors is symmetrical. On the other hand, the asymmetrical shift of flatband voltage was observed from the Pt/SBT-Y,OJSi capacitor. In Fig. j(b), mobile positive charges move to the SBT-YrO3 interface during the positive bias stress. This phenomenon can cause the negative C-V shift without reducing the width of memory window since the effect ofcharge injection can be ignored in the Pt/SBT-Y:O:/Si capacitors. During the negative bias stress (i.e.. -3V for 30 min.). however. the shift of mobile positive charges to the Pt-SBT interface was less effective due to the

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DONGSEOK KANG et a1

charge screen effect caused by the trapped negative charges. Therefore, the degree of C-V shift to the positive gate bias is less, consistent with

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the results discussed in Fig. 2.

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FIGURE 5 Flatband voltage versus time curve for an applied gate bias of ;t3 V on (a) PtISBTISi and (b) Pt/SBT-Y?O1/Sicapacitor. Figure 6 shows the relaxation phenomenon of the 5 3 V stressed PtlSBT-Y,O;/Si capacitors. The hysteresis curves measured two da) s

HYSTERESIS CAUSED BY DEFECTS IN MFIS DEVICES

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after the 1-3 V stress moves back toward the positive gate voltage, suggesting the data shown in Fig. 5 indeed were caused by the mobile positive charges. In addition, the shift of hysteresis curve stressed at -3 V for 30 minutes was negligible up to the time scale employed in this

work. Currently, we are investigating this phenomenon in more detail.

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CONCLUSIONS We have characterized the Pt/SBT-Y,O,/p-Si (MFIS) capacitors. We found that the insertion of Y 2 0 3buffer layer improves the interfacial properties. For example, charge injection from the Si substrate to ferroelectric layer was effectively prohibited. However. a significant amount of negative charges was also introduced due to the presence of Y,O, buffer layer. Based on the shift of hysteresis curves, we calculated the effective density of 3.2 1 x 1O"Icm'. We suggested that negative charges in Y,O, buffer layer induce the domain pinning. causing the preferential switching. The later produces the asymmetrical increase of

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the memory window via the flatband voltage shift toward the negative gate voltage during the forward sweep. In addition, we found that mobile positive charge (e.g., oxygen vacancies) causes the shift of hysteresis curves depending on the bias polarity, as well as the ramp rate during the C-V measurement. Negative charges in Y,O, buffer layer compensate the effect of positive-charge shift when the negative gate bias was applied, causing the asymmetrical shift of the hysteresis curves. Detailed analysis of our data led us to conclude that a careful preparation for buffer layer is required to prevent the phenomena observed in this work. Acknowledgements This work is supported by the collaborative project of System IC 2010. The authors (D. Kang and S. A h ) are also supported by the BK21 project. The authors would like to thank Dr. Y. T. Kim from the KIST for providing the samples used in the present experiments References [ l ] Y. T. Kim. and D. S. Shin, Appl. Phys. Lett.. 71. 35074 (1997). [2] H. N. Lee, Y. T. Kim and S. H. Choh, Appl. Phys. Lett.. 76. 1066

(2000). [3] Woo-Chul Yi, Chang-Su Seo, Sook-11 Kwun and Jong-Gul Yoon, Appl. Phys. Lett.. 77. 1044 (2000). [4] Y. Lin. B. R. Zhao, H. B. Peng, Z. Hao, B. Xu. Z. X. Zhao and J. S. Chen. J. Appl. Phys.. 86,4467 (1999). [5] Woo-Chul Yi. Joon-Seon Choe. Chang-Rok Moon, Sook-I1 Kwun and Jong-Gul Yoon, Appl. Phys. Lett.. 73, 903 ( 1 998). [6] Y. Roh, K. Kim and D. Jung, Jpn. J. Appl. Phys., 36. 1681 (1997). [7] W. P. Li, R. Zhang, J. Shen. Y. M. Liu. B. Shen, P. Chen. Y. G. Zhou. J. Li. X. L. Yuan. Z. Z. Chen, Y. Shi, Z. G. Liu and Y. D. Zeng, Appl. Phys. Lett.. 77. 564 (2000). [8] W. L. Warren. D. Dimos. G. E. Pike. B. A. Tuttle. M. V. Raymond. R. Ramesh and J. T. Evans, Tr.. Appl. Phys. Lett.. 67. 866 (19953.