12-1 Clock 3 ns Clock
WB OF
Register file
3 ns
3
Register file
3 ns
3 ns 1
MUX B
MUX B
1 ns
1 ns
OF EX
Function unit
MUX D
4 ns
1 ns
2
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
Function unit
4 ns
EX WB 3
(a) Conventional
1 ns
1 ns MUX D
(b) Pipelined
1 ns
12-2 1 OF Operand Fetch (OF)
AA
Register file A data B data
BA
Constant in MUX B
MB
OF EX
Address out Data out
2 Execute (EX)
A
B
FS V
Function unit
C N
F
Z
Data in
EX WB
MD 3 Write-back (WB) WB
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
RW DA
0 1 MUX D
D data Register file (same as above)
12-3
Clock cycle R1
R2 2 R3 R4
1
sl R6
2
R7
R7 1 1
3
R1
R0 1 2
4
Data out R4
R3
5
Data in
6
R5
7
0
1
2
3
OF
EX
WB
OF
EX
WB
OF
EX
WB
OF
EX
WB
OF
EX
WB
OF
EX
WB
OF
EX
Microoperation
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
4
5
6
7
8
9
WB
12-4 PC
IF
Address Stage 1
Instruction memory Instruction
IF
IR
DOF
Register file A data B data
AA
Stage 2
Zero fill Instruction decoder
DOF
MUX B
AABAMB
Data A
Address out FS
MW 4
FS C V N Z
Stage 3
EX
A
B
F
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
MD RW MD RW DA CONTROL DATAPATH
Data memory Data out Data in Data out MW Data I Data in Address
Data F DA
Address
Function unit
WB
WB
MB Data B
EX
Stage 4
BA
MUX D D data register file (same as above)
Data memory (same as above)
12-5
Clock cycle 1 2 3
1
2
3
4
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
DOF
EX
4 5 6 7 Instruction
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
5
6
7
IF
8
9
10
WB
12-6
R0 5 0 R1 PC Program counter
R31 Register file © 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-7
31 Three-register type
Two-register type
Branch
25 24
OPCODE
OPCODE
OPCODE
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
20 19
15 14
10 9
DR
SA
DR
SA
Immediate
DR
SA
Target offset
SB
0
T 12-1
TABLE 12-1 RISC Instruction Operations Operation
Symbolic Notation Opcode
No Operation Move A Add
NOP MOVA ADD
0000000 1000000 0000010
SUB AND OR XOR NOT ADI SBI ANI ORI
0000101 0001000 0001001 0001010 0001011 0100010 0100101 0101000 0101001
None R[DR] ← R[SA] R[DR] ← R[SA] + R[SB] R[DR] ← R[SA] + R [SB ] + 1 R[DR] ← R[SA] ∧ R [SB] R[DR] ← R[SA] ∨ R[SB] R[DR] ← R[SA] ⊕ R[SB] R[DR] ← R[ SA] R[DR] ← R[SA] + se IM R[DR] ← R[SA] + se IM + 1 R[DR] ← R[SA] ∧ (0 || IM) R[DR] ← R[SA] ∨ (0 || IM)
XRI
0101010
R[DR] ← R[SA] ⊕ (0 || IM)
AIU
1000010
R[DR] ← R[SA] + (0 || IM)
SIU
1000101
R[DR] ← R[SA] + ( 0 || IM ) + 1
MOVB
0001100
R[DR] ← R[SB]
LSR
0001101
R[DR] ← lsr R[SA] by SH
LSL
0001110
R[DR] ← lsl R[SA] by SH
LD ST JMR SLT BZ BNZ JMP JML
0010000 0100000 1110000 1100101 1100000 1010000 1101000 0110000
R[DR] ← M[R[SA]] M[R[SA]] ← R[SB] PC ← R[SA] If R[SA] < R[SB], thenR[DR] + 1 If R[SA] = 0, then PC ← PC + 1 + se IM If R[SA] ≠ 0, then PC ← PC + 1 + se IM PC ← PC + 1 + se IM PC ← PC + 1 + se IM, R[DR] ← PC + 1
Subtract AND OR Exclusive-OR Complement Add Immediate Subtract Immediate AND Immediate OR Immediate Exclusive-OR Immediate Add Immediate Unsigned Subtract Immediate Unsigned Move B Logical Right Shift by SH Bits Logical Left Shift by SH Bits Load Store Jump Register Set if Less Than Branch on Zero Branch on Nonzero Jump © 2004 Pearson Education, Inc. Jump and Link M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
Action
12-8
MUX C 0 1 3 2
PC
+1
PC21
2
BS1
BS0
PS Z
BrARAA
IF
Address Instruction memory Instruction IF DOF
IR IM 5 IR14:0
32 3 32 Register file with R0 5 0 A data B data
Constant unit
SH 5 IR4:0
CS AA
Instruction decoder MA MB AA
PC21
BA CS
1 0
MA
SH
1 0
MB MUX A MUX B Bus A Bus B
PC22 BS PS MWFS
DOF EX
RAA
SH
Address 5 SH 5 FS Z N C
Adder V
A
B
Modified function unit
0
Data out MW Data in Write
EX WB
31 MD
Data memory
Address Data memory
F
BrA
RW DA MD
BA
0
1 2
MUX D
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
RW DA
Bus D D Data 32 3 32 Register file with R0 5 0
WB
12-9
Left/right 0
SH 5 0 || A
Selective S 2’s complement 2
2
64
2 47 4-to-1 multiplexers (rotate right 0, 16, 32, or 48 bit positions) 47 35 4-to-1 multiplexers (rotate right 0, 4, 8, or 12 bit positions) 35 32 4-to-1 multiplexers (rotate right 0, 1, 2, or 3 bit positions) 32 G
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-2
TABLE 12-2 Definition of Control Fields BS and PS BS Code
PS Code
PC ← PC + 1
00
X
Increment PC
Z: PC ← BrA, Z: PC ← PC + 1
01
0
Branch on Zero
Z: PC ← BrA, Z: PC ← PC + 1
01
1
Branch on Nonzero
PC ← R[ AA ]
10
X
Jump to Contents of R[AA]
PC ← BrA
11
X
Unconditional Branch
Register Transfer
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
Comments
T 12-3
TABLE 12-3 Control Words for Instructions Symbolic Notation Action
NOP MOVA ADD SUB AND OR XOR NOT ADI SBI ANI ORI XRI AIU SIU MOVB LSR LSL LD ST JMR SLT BZ BNZ JMP JML
Op Code
None 0000000 R[DR] ← R[SA] 1000000 R[DR] ← R[SA] + R[SB] 0000010 R[DR] ← R[SA] + R[ SB] + 1 0000101 R[DR] ← R[SA] ∧ R[SB] 0001000 R[DR] ← R[SA] ∨ R[SB] 0001001 R[DR] ← R[SA] ⊕ R[SB] 0001010 R[DR] ← R [ SA ] 0001011 R[DR] ← R[SA] + se IM 0100010 R[DR] ← R[SA] + ( se IM ) + 1 0100101 R[DR] ← R[SA] ∧ zf IM 0101000 R[DR] ← R[SA] ∨ zf IM 0101001 R[DR] ← R[SA] ⊕ zf IM 0101010 R[DR] ← R[SA] + zf IM 1000010 R[DR] ← R[SA] + ( zf IM ) + 1 1000101 R[DR] ← R[SB] 0001100 R[DR] ← lsr R[SA] by SH 0001101 R[DR] ← lsl R[SA] by SH 0001110 R[DR] ← M[R[SA]] 0010000 M[R[SA]] ← R[SB] 0100000 PC ← R[SA] 1110000 If R[SA] < R[SB] then R[DR] ← 1 1100101 If R[SA] = 0, then PC ← PC + 1 + se IM 1100000 If R[SA] ≠ 0, then PC ← PC + 1 + se IM 1010000 PC ← PC + 1 + se IM 1101000 PC ← PC + 1 + se IM, R[DR] ← PC + 1 0110000
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
Control Word Values RW MD BS PS MW
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1
XX 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 00 00 X 01 00 X XX 00 X XX 10 X 10 00 X XX 01 0 XX 01 1 XX 11 X 00 11 X
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
FS MB MA CS XXXX
X
X
0000 0010 0101 1000 1001 1010 1011 0010 0101 1000 1001 1010 0010 0101 1100 1101 1110
X
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0
X
X
0 0 0 0 0 0 0 0
X X X X X X
XXXX XXXX XXXX
0101 0000 0000
0 0 0 0 0 X
1 1 1 1 1 1 1 0 X X X
0 X
0 1 1 XXXX 1 0000 1
X
1
X X X X X X X X
1 1 1 1
12-10 MOVA R1, R5
R1
ADD R2, R1, R6
R2
R5
1
2
3
4
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
R1 1 R6 R3
ADD R3, R1, R2
Write R1 5 6 Write R2
R1 1 R2
WB
First read R1 Second read R1 Read R2 (a) The data hazard problem
Write R1 MOVA R1, R5
R1
R5
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
NOP ADD R2, R1, R6
R2
R1 1 R6
NOP ADD R3, R1, R2
R3
R1 1 R2
First read R1 Second read R1 © 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime (b) A LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
Read R2 program-based solution
Write R2
WB
12-11
R1 data hazard detected pipeline stalled, and bubble launched R1 write and reads MOVA R1, R5 (ADD R2, R1, R6) ADD R2, R1, R6
R1 R2
R5
1
2
3
4
IF
DOF
EX
WB
IF
DOF
R1 1 R6 R2
R1 1 R6 R3
(ADD R3, R1, R2)
IF
R1 1 R2 R3
ADD R3, R1, R2
EX
IF
DOF
R1 1 R2
6
7
8
R2 Write and read
DOF
R2 data hazard detected, pipeline stalled, and bubble launched.
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
5
IF
WB DOF
EX
WB
12-12
MUX C 0 1 3 2
2
BS1
BS0
PS Z
BrA RAA
PC
IF Address Instruction memory Instruction
11
PC21
IR
IF IM 5 IR14:0
DOF
Constant unit
SH 5 IR4:0
CS
Instruction decoder
AA
MA MB AA BA
32 3 32 Register file with R0 5 0 A data B data
BA
PC21
CS SH
Comp
1 0 1 0 MB MUX A MUX B Bus A Bus B
MA Comp
PC22
DOF
HB BS PS MW FS
HA
SH
EX
DHS RAA
DHS
SH FS
5 5 Z
N
A
B
Modified function unit
C
Adder
V
F
BrA
Address Data memory Data out MW Data inWrite Address Data memory EX WB
0 31 RW DA MD
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
MD RW DA
0 1 2 MUX D Bus D D Data 32 3 32 Register file with R0 = 0
WB
12-13
MUX C 0 1 3 2
PC
11
PC21
2
BS1
BS0
PS Z
BrA RAA IF Address Instruction memory Instruction IR
IF IM 5 IR14:0
DOF
Constant unit
SH 5 IR4:0
32 3 32 Register file with R0 5 0 A data B data
CS
Instruction decoder MA MB AA Comp
SH
AA
BA
Comp
PC22
BA
PC21
CS HA MA
HB 2 1 0 2 1 0 MUX A MUX B MB Bus A Bus B
DOF EX
HB BS PS MW FS
SH
HA RAA
Bus D' MUX D' 0 1 2 0 N
31
SH FS
5 5
A
B
Modified function unit
Z C
Adder
V
F
BrA
Address Data memory Data out MW Data inWrite Address Data memory EX
0 RW DA MD
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
WB
31 MD
RW DA
0 1 2 MUX D Bus D D Data 32 3 32 Register file with R0 = 0
WB
12-14
MOVA R1, R5 ADD R2, R1, R6 ADD R3, R1, R2
R1 R2
R5
1
2
3
IF
DOF
EX
IF
DOF
EX
WB
IF
DOF
EX
R1 1 R6 R3
R1 data hazard detected and R1 value forwarded R1 write and read 4 5 6 Write R2 WB
R1 1 R2
R2 data hazard detected and R2 value forwarded
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
WB
12-15 R1 = 0 evaluated
1 BZ R1, 18
1
2
3
IF
DOF
EX
IF
DOF
2 MOV R2, R3
IF
3 MOV R1, R2 20 MOV R5, R6
PC set to 20 4 5 6 7 Change in R2 WB Change in R1 EX WB DOF
EX
WB
IF
DOF
EX
WB
Instruction MOV R5, R6 fetched from target address (a) Branch Hazard Problem R1 = 0 evaluated
1 BZ R1, 18
1
2
3
IF
DOF
EX
IF
DOF
2 NOP
IF
3 NOP 20 MOV R5, R6
PC set to 20 4 5 6 7 No change WB No change EX WB DOF
EX
WB
IF
DOF
EX
Instruction MOV R5, R6 fetched from target address (b) Program-based Solution
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
WB
12-16
R1 = 0 evaluated
1 BZ R1, 18 2 MOVA R2 R3
1
2
3
IF
DOF
EX
IF
DOF
3 MOVA R1 R2 20 MOVA R5 R6
IF
PC set to 20 4 5 6 7 No change WB No change EX WB DOF IF
Branch detected and bubbles launched Instruction MOV R5, R6 fetched from target address © 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
WB DOF
EX
WB
12-17 MUX C 0 1 3 2
PC
11
PC21
BS1
BS0
2
PS Z
BrA RAA IF Address Instruction memory Instruction
IR
IM 5 IR14:0 SH 5 IR4:0
32 3 32 Register file with R0 = 0 A data B data
Constant unit CS AA
Instruction decoder
IF DOF BA
MA MB AA BA CS PC21 SH
1 0 1 0 MB MUX A MUX B Bus A Bus B
MA
PC22 RAA
BS PS MW FS SH
SH FS
5
5
A
B
Modified function unit
Z N ADDER
C V
F
BrA
RW DA MD
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
DOF EX
0
RW DA
Address Data memory Data out MW Data inWrite Address Data memory EX WB
31 0 1 2 MUX D Bus D D Data 32 3 32 Register file with R0 = 0
WB
12-18
Microprogram Counter
Instruction fetch Decode & Operand Fetch
Control ROM
Execute Write-back
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-19
31
25 24
20 19
10 9
15 14
Three-register type
OPCODE
DR
SA
Two-register type
OPCODE
DR
SA
Immediate
Branch 1
OPCODE
DR
SA
Long target offset
Branch 2
OPCODE
DR
SA
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
SB
SB
Short target offset
0
12-20
2
MUX C 0 1 3 2
PC
MS
BS1
BS0
PS Z
BrA RAA IF
11
Address Instruction memory Instruction
PC21
IR
IF
IM = IR14:0 IR4:0
CA
Constant unit
MIR30:0
DA AA BA
From CC
1
MI
DFDA
MUX I 0 CS AX BX DX
PC22
Register 5 address 5 logic 5
4 BA 4 DA 4
CS
Instruction decoder SA
AA
PC21
DOF
32 x 32 Register file with R0 = 0 A data B data
AX 2 1 0 1 0 BX DX DFDA MUX AMUX B Bus A Bus B
DOF EX
BS PS MW FS
RAA
LC SH
SH FS Z
5
A 5
Adder L ZN C V
BrA
LC
RW FDA MD
0
27
Modified function unit F
Data in Write Address Data memory EX
CC 5
WB
To Mux A MD
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
B
Address Data memory Data out MW
RW FDA
0 1 MUX D Bus D D Data 32 3 32 Register file with R0 5 0
WB
T 12-4
TABLE 12-4 Added or Modified Control Word (Microinstruction) Fields for CISC Control Fields MZ 2b
CA 8h
BS P 2b S
See See Next Table Address Table 12-3 or Con- 12-2 stant
Register Fields Action
0X 10 ... 1F
DX Source R[DR] 00 and Dest. R[SB] Dest R[DR] 0X with X ≠ 0 R16 10 ... ... 1F R31 © 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
MA
LC
Code Code Code Action Action Action Code 5h 2b 2b
AX, BX
R[SA], R[SB] R16 ... R31
CS
zf IM se IM se IMS zf CA
00 01 10 11
A Data PC −1 0 || CC
00 01 10
Hold CC Load CC
0 1
12-21 SA CACA21 11
8 0
MC
8
MS MI MZ MZ21 PS Z
8
1 2 Mux E
Microaddress control
ME
3
8
Address Microcode ROM Data 41 MIR 2 MZ
8 CA
MIR30:0
31
DOF 2 MZ21
EX
8 CA21 (a)
40 39 38 M Z
CA
31 30 29
25 24 23 22 21 20 19
R W
M P M BS D S W
DX
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
(b)
16 15 14 13 12 11 FS
L C
M M A B
7 6 AX
21 0 BX
C S
T 12-5
TABLE 12-5 Address Control Inputs
MZ
Outputs
MZ
MI
PS
Z
ME1
ME0
11
01
X
0
0
0
0
1
PS Z: MC ← MC + 1
11
01
X
0
1
0
1
1
PS Z: MC ← CA −1
11
01
X
1
0
0
1
1
PS Z: MC ← CA −1
11
01
X
1
1
0
0
0
PS Z: MC ← MC + 1
0X
01
X
X
X
0
0
1
MC ← MC + 1
X0
01
X
X
X
0
0
1
MC ← MC + 1
XX
00
0
X
X
1
0
0
MC ← CA
XX
00
1
X
X
0
1
1
MC ← SA
XX
10
X
0
X
1
0
0
PS: MC ← CA
XX
10
X
1
X
1
0
1
PS: MC ← CA
XX
11
X
X
X
0
0
1
MC ← MC + 1
1
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
MS Register Transfer Due to ME
T 12-6A
TABLE 12-6 Example Microprograms for CISC Architecture Microinstructions Action
Address MZ
CA
R M P M L M W DX D BS S W FS C MA B AX BX CS
Shared Microinstructions MI: MC ←SA, MI:MC ←00 IDLE 00 MC ←MC + 1 (NOP) Arbitrary 01 R16 ←R[ SA] + zf IML MC ←MC + 1 (NOP) R17 ←M[ R16 ] MC ←MC + 1 (NOP) R[ DR] ←M[ R17 ]
00 XX
0 00 0 00 0 0 00 0 00 0
Load Indir ect Indexed (LII) LII0 01 00 1 10 0 00 LII1 01 00 0 00 0 00 LII2 01 00 1 11 1 00 LII3 01 00 0 00 0 00 LII4 10 IDLE 1 01 1 00
0 0 0 0 0
0 0
0 0 00 0 00 00 00 0 0 00 0 00 00 00
0 0 0 0 0
2 0 0 0 0
0 0 0 0 0
00 00 00 00 00
1 0 0 0 0
00 00 10 00 11
00 00 00 00 00
00 00 00 00 00
Compare Less Than or Equal To (BLE) R[ SA] − R[ SB] CC ←L|| Z ||N ||C || V MC ←MC + 1 (NOP) R31← CC ∧ 11000 MC ←MC + 1 (NOP) if ( R31 ≠ 0) MC ←BLE7 else MC ← MC + 1 MC ←MC + 1 (NOP) MC ←IDLE PC ← PC − 1 + se IML, MC ←IDLE
BLE0
01
00
0 01 0 00 0
0
5 1 00 0 00 00 00
BLE1 BLE2 BLE3
01 01 01
00 18 00
0 00 0 00 0 1 1F 0 00 0 0 00 0 00 0
0 0 0
0 0 00 0 00 00 00 8 0 10 1 00 00 11 0 0 00 0 00 00 00
BLE4
11 BLE7
0 00 0 00 1
0
0 0 00 0 1F 00 00
BLE5 BLE6
01 00 00 IDLE
0 00 0 00 0 0 00 0 00 0
0 0
0 0 00 0 00 00 00 0 0 00 0 00 00 00
BLE7
10 IDLE
0 00 0 11 0
0
0 0 01 1 00 00 10
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-6B
TABLE 12-6 Example Microprograms for CISC Architecture Microinstructions Action
Address MZ
CA
R M P M L M W DX D BS S W FS C MA B AX BX CS
Shared Microinstructions MI: MC ←SA, MI:MC ← 00 IDLE 00 MC ← MC + 1 (NOP) Arbitrary 01 R16 ← R[SB] MC ← MC + 1 (NOP) R16 ← R16 − 1 R17 ← R[ DR] R18 ← R[SA] + R16 R19 ← R17 + R16 R20 ← M[ R18 ] MC ← MC + 1 (NOP) M[ R19 ] ← R20 if (R16 ≠ 0 )MC ← MMB2 MC ← MC + 1 (NOP) MC ← IDLE
00 XX
0 00 0 00 0 0 00 0 00 0
Move Memory Block (MMB) MMB0 01 00 1 10 0 00 MMB1 01 00 0 00 0 00 MMB2 01 01 1 10 0 00 MMB3 01 00 1 00 0 00 MMB4 01 00 1 12 0 00 MMB5 01 00 1 13 0 00 MMB6 01 00 1 14 1 00 MMB7 01 00 0 00 0 00 MMB8 01 00 0 00 0 00 MMB9 11 MMB2 0 00 0 00 MMB10 01 00 0 00 0 00 MMB11 10 IDLE 0 00 0 00
© 2004 Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
0 0 0 0 0 0 0 0 0 1 0 0
0 0
0 0 00 0 00 00 00 0 0 00 0 00 00 00
0 C 0 00 0 00 00 00 0 0 0 00 0 00 00 00 0 5 0 00 1 00 00 11 0 C 0 00 0 00 11 00 0 2 0 00 0 00 10 00 0 2 0 00 0 11 10 00 0 0 0 00 0 12 00 00 0 0 0 00 0 00 00 00 1 0 0 00 0 13 14 00 0 0 1 00 0 10 00 00 0 0 0 00 0 00 00 00 0 0 0 00 0 00 00 00
