XR-2206 ...the analog plus

PerpustakaanMonolithic Unika Function Generator

company TM

June 1997-3

FEATURES

APPLICATIONS
Waveform Generation


Low-Sine Wave Distortion, 0.5%, Typical
Excellent Temperature Stability, 20ppm/°C, Typ.


Sweep Generation


Wide Sweep Range, 2000:1, Typical


AM/FM Generation


Low-Supply Sensitivity, 0.01%V, Typ.


V/F Conversion


Linear Amplitude Modulation


FSK Generation


TTL Compatible FSK Controls


Phase-Locked Loops (VCO)


Wide Supply Range, 10V to 26V
Adjustable Duty Cycle, 1% TO 99%

GENERAL DESCRIPTION The XR-2206 is a monolithic function generator integrated circuit capable of producing high quality sine, square, triangle, ramp, and pulse waveforms of high-stability and accuracy. The output waveforms can be both amplitude and frequency modulated by an external voltage. Frequency of operation can be selected externally over a range of 0.01Hz to more than 1MHz.

The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical drift specification of 20ppm/°C. The oscillator frequency can be linearly swept over a 2000:1 frequency range with an external control voltage, while maintaining low distortion.

ORDERING INFORMATION

Part No.

Package

Operating Temperature Range

XR-2206M

16 Lead 300 Mil CDIP

-55°C to +125°C

XR-2206P

16 Lead 300 Mil PDIP

–40°C to +85°C

XR-2206CP

16 Lead 300 Mil PDIP

0°C to +70°C

XR-2206D

16 Lead 300 Mil JEDEC SOIC

0°C to +70°C

Rev. 1.03 1972

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  (510) 668-7017 1

XR-2206 Perpustakaan Unika

TC1

5

TC2

6

TR1

7

TR2

8

FSKI

9

AMSI

1

Timing Capacitor

Timing Resistors

VCC

GND

BIAS

4

12

10 11 SYNCO

VCO

Current Switches

Multiplier And Sine Shaper

WAVEA1 13 WAVEA2 14 SYMA1 15 SYMA2 16

Figure 1. XR-2206 Block Diagram

Rev. 1.03 2

+1

2

STO

3

MO

XR-2206 Perpustakaan Unika

AMSI STO MO VCC TC1 TC2 TR1 TR2

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

SYMA2 SYMA1 WAVEA2 WAVEA1 GND SYNCO BIAS FSKI

AMSI STO MO VCC TC1 TC2 TR1 TR2

16 Lead PDIP, CDIP (0.300”)

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

SYMA2 SYMA1 WAVEA2 WAVEA1 GND SYNCO BIAS FSKI

16 Lead SOIC (Jedec, 0.300”)

PIN DESCRIPTION Pin #

Symbol

Type

Description

1

AMSI

I

Amplitude Modulating Signal Input.

2

STO

O

Sine or Triangle Wave Output.

3

MO

O

Multiplier Output.

4

VCC

5

TC1

I

Timing Capacitor Input.

6

TC2

I

Timing Capacitor Input.

7

TR1

O

Timing Resistor 1 Output.

8

TR2

O

Timing Resistor 2 Output.

9

FSKI

I

Frequency Shift Keying Input.

10

BIAS

O

Internal Voltage Reference.

O

Sync Output. This output is a open collector and needs a pull up resistor to VCC.

Positive Power Supply.

11

SYNCO

12

GND

13

WAVEA1

I

Wave Form Adjust Input 1.

14

WAVEA2

I

Wave Form Adjust Input 2.

15

SYMA1

I

Wave Symetry Adjust 1.

16

SYMA2

I

Wave Symetry Adjust 2.

Ground pin.

Rev. 1.03 3

XR-2206 Perpustakaan Unika

DC ELECTRICAL CHARACTERISTICS Test Conditions: Test Circuit of Figure 2 Vcc = 12V, TA = 25°C, C = 0.01F, R1 = 100k
, R2 = 10k
, R3 = 25k
Unless Otherwise Specified. S1 open for triangle, closed for sine wave. XR-2206M/P Parameters

Min.

Typ.

XR-2206CP/D Max.

Min.

Typ.

Max.

Units

Conditions

General Characteristics Single Supply Voltage

10

26

10

26

V

Split-Supply Voltage

+5

+13

+5

+13

V

20

mA

Supply Current

12

17

14

R1  10k


Oscillator Section Max. Operating Frequency

0.5

Lowest Practical Frequency

1

0.5

0.01

1

MHz

0.01

Hz

C = 1000pF, R1 = 1k
C = 50F, R1 = 2M


Frequency Accuracy

+1

+4

+2

% of fo

Temperature Stability Frequency

+10

+50

+20

ppm/°C 0°C
TA
70°C R1 = R2 = 20k


Sine Wave Amplitude Stability2

4800

4800

ppm/°C

Supply Sensitivity

0.01

0.01

%/V

2000:1

fH = fL

2

%

fL = 1kHz, fH = 10kHz

Sweep Range

0.1

1000:1 2000:1

fo = 1/R1C

VLOW = 10V, VHIGH = 20V, R1 = R2 = 20k
fH @ R1 = 1k
fL @ R1 = 2M


Sweep Linearity 10:1 Sweep

2

1000:1 Sweep

8

8

%

fL = 100Hz, fH = 100kHz

FM Distortion

0.1

0.1

%

+10% Deviation

Figure 5

Recommended Timing Components Timing Capacitor: C Timing Resistors: R1 & R2 Triangle Sine Wave

0.001

100

0.001

100

F

1

2000

1

2000

k


Output1

Figure 3

Triangle Amplitude Sine Wave Amplitude

160 40

60

80

160

mV/k


Figure 2, S1 Open

60

mV/k


Figure 2, S1 Closed

Max. Output Swing

6

6

Vp-p

Output Impedance

600

600




Triangle Linearity

1

1

%

Amplitude Stability

0.5

0.5

dB

For 1000:1 Sweep

%

R1 = 30k


%

See Figure 7 and Figure 8

Sine Wave Distortion Without Adjustment

2.5

With Adjustment

0.4

2.5 1.0

0.5

1.5

Notes 1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3. 3 2 For maximum amplitude stability, R should be a positive temperature coefficient resistor. 3 Bold face parameters are covered by production test and guaranteed over operating temperature range. Rev. 1.03 4

XR-2206 Perpustakaan Unika

DC ELECTRICAL CHARACTERISTICS (CONT’D) XR-2206M/P Parameters

Min.

Typ.

50

100

XR-2206CP/D Max.

Min.

Typ.

Max.

Units

50

100

k


Conditions

Amplitude Modulation Input Impedance Modulation Range

100

100

%

Carrier Suppression

55

55

dB

Linearity

2

2

%

For 95% modulation

Amplitude

12

12

Vp-p

Measured at Pin 11.

Rise Time

250

250

ns

CL = 10pF

Fall Time

50

50

ns

CL = 10pF

Saturation Voltage

0.2

0.4

0.2

0.6

V

IL = 2mA

Leakage Current

0.1

20

0.1

100

A

VCC = 26V

Square-Wave Output

FSK Keying Level (Pin 9)

0.8

1.4

2.4

0.8

1.4

2.4

V

See section on circuit controls

Reference Bypass Voltage

2.9

3.1

3.3

2.5

3

3.5

V

Measured at Pin 10.

Notes 1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3. 3 2 For maximum amplitude stability, R should be a positive temperature coefficient resistor. 3 Bold face parameters are covered by production test and guaranteed over operating temperature range.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 750mW Derate Above 25°C . . . . . . . . . . . . . . . . . . . . . . 5mW/°C

Total Timing Current . . . . . . . . . . . . . . . . . . . . . . . . 6mA Storage Temperature . . . . . . . . . . . . -65°C to +150°C

SYSTEM DESCRIPTION The XR-2206 is comprised of four functional blocks; a voltage-controlled oscillator (VCO), an analog multiplier and sine-shaper; a unity gain buffer amplifier; and a set of current switches.

terminals to ground. With two timing pins, two discrete output frequencies can be independently produced for FSK generation applications by using the FSK input control pin. This input controls the current switches which select one of the timing resistor currents, and routes it to the VCO.

The VCO produces an output frequency proportional to an input current, which is set by a resistor from the timing Rev. 1.03 5

XR-2206 Perpustakaan Unika

VCC

1mF 4 1 5

16

C 6 FSK Input

S1 = Open For Triangle = Closed For Sinewave

15 14 13

9 7 8

R1 R2

25K

Mult. And Sine Shaper

VCO

Symmetry Adjust

S1

THD Adjust 500

Current Switches

Triangle Or Sine Wave Output Square Wave Output

2

+1

11 10 12 1mF

XR-2206

3

10K

R3 25K +

VCC 1mF

VCC 5.1K

5.1K

Figure 2. Basic Test Circuit

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ

26

70°C Max. Package Dissipation

Triangle

5 4

22 1KW

Sinewave

3 2 1

0

20

40

60

80

ICC (mA)

Peak Output Voltage (Volts)

6

2KW

18 10KW 14 30KW 10 8

100

12

16

20

24

28

VCC (V)

R3 in (KW)

Figure 3. Output Amplitude as a Function of the Resistor, R3, at Pin 3

Figure 4. Supply Current vs Supply Voltage, Timing, R

Rev. 1.03 6

XR-2206 Perpustakaan Unika

10M

ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ

1M

Normal Output Amplitude

Timing Resistor ( W )

MAXIMUM TIMING R

NORMAL RANGE

100K

TYPICAL VALUE

10K

1K

4V

1.0

0.5

MINIMUM TIMING R

10-2

102

10

104

0

VCC / 2

106

Frequency (Hz)

DC Voltage At Pin 1

Figure 5. R versus Oscillation Frequency.

Figure 6. Normalized Output Amplitude versus DC Bias at AM Input (Pin 1)

ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 5

5

3

2

1

10

100

R=3KW VOUT =0.5VRMS Pin 2 RL=10KW

3

2

1

0

1.0

ÁÁÁ ÁÁÁÁ ÁÁÁÁ

4

C = 0.01mF Trimmed For Minimum Distortion At 30 KW

Distortion (%)

Distortion (%)

4

4V

0

103

10

100

1K

10K

100K

1M

Frequency (Hz)

Timing R K(W)

Figure 7. Trimmed Distortion versus Timing Resistor.

Figure 8. Sine Wave Distortion versus Operating Frequency with Timing Capacitors Varied.

Rev. 1.03 7

XR-2206 Perpustakaan Unika

3 C=0.01F

Frequency Drift (%)

2

R=1M
R=2K


1

R=10K
R=200K


R=200K
0

-1

R=1M


Sweep Input

R=1K


Rc + -

IB

VC

-2 R=1K
-3 -50

-25

0

25

IT

IC

R=10K
R=2K


50

75

R

ÁÁ

Pin 7 or 8

+ 3V -

12

125

100

Ambient Temperature (C°)

Figure 9. Frequency Drift versus Temperature.

Figure 10. Circuit Connection for Frequency Sweep. VCC

1F 4 1 5 C

16 Mult. And Sine Shaper

VCO

6

14 13

9

2M

R1

1K

7 8

Current Switches

+1

10

R

12

S1 Closed For Sinewave

15 S1

200

2

Triangle Or Sine Wave Output

11

Square Wave Output

XR-2206

3 R3 50K

+

10K

1F +

VCC 10F

VCC 5.1K

5.1K

Figure 11. Circuit tor Sine Wave Generation without External Adjustment. (See Figure 3 for Choice of R3) Rev. 1.03 8

XR-2206 Perpustakaan Unika

VCC

1
F 4 1 5 C

1 F= RC

25K

Mult. And Sine Shaper

VCO

6

R1

1K

7 8

RB

15 14

S1 Closed For Sinewave S1

13

9

2M

Symmetry Adjust

16

RA 500

Current Switches

2

+1

Triangle Or Sine Wave Output Square Wave Output

11 10

R

12

3

XR-2206

R3 50K

+ 1
F

10K

+

VCC

10
F VCC 5.1K

5.1K

Figure 12. Circuit for Sine Wave Generation with Minimum Harmonic Distortion. (R3 Determines Output Swing - See Figure 3)

VCC

1
F 4

1 5 >2V

F1

600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)

MC14051B MC14052B MC14053B 2

MOTOROLA CMOS LOGIC DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ v ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE Characteristic

Propagation Delay Times (Figure 6) Switch Input to Switch Output (RL = 10 kΩ) MC14051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns MC14052 tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns

VSS unless otherwise indicated) VDD – VEE Typ # Unika Vdc All TypesPerpustakaan Symbol Max

ns

5.0 10 15

35 15 12

90 40 30

5.0 10 15

30 12 10

75 30 25

5.0 10 15

25 8.0 6.0

65 20 15

ns

MC14053 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns

Inhibit to Output (RL = 10 kΩ, VEE = VSS) Output “1” or “0” to High Impedance, or High Impedance to “1” or “0” Level MC14051B

Unit

tPLH, tPHL

ns

tPHZ, tPLZ, tPZH, tPZL

ns

5.0 10 15

350 170 140

700 340 280

MC14052B

5.0 10 15

300 155 125

600 310 250

ns

MC14053B

5.0 10 15

275 140 110

550 280 220

ns

5.0 10 15

360 160 120

720 320 240

MC14052B

5.0 10 15

325 130 90

650 260 180

ns

MC14053B

5.0 10 15

300 120 80

600 240 160

ns

—

10

0.07

—

%

BW

10

17

—

MHz

—

10

– 50

—

dB

Channel Separation (Figure 8) (RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, fin = 3.0 MHz

—

10

– 50

—

dB

Crosstalk, Control Input to Common O/I (Figure 9) (R1 = 1 kΩ, RL = 10 kΩ Control tTLH = tTHL = 20 ns, Inhibit = VSS)

—

10

75

—

mV

Control Input to Output (RL = 10 kΩ, VEE = VSS) MC14051B

Second Harmonic Distortion (RL = 10KΩ, f = 1 kHz) Vin = 5 VPP Bandwidth (Figure 7) (RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF 20 Log (Vout/Vin) = – 3 dB) Off Channel Feedthrough Attenuation (Figure 7) RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p fin = 4.5 MHz — MC14051B fin = 30 MHz — MC14052B fin = 55 MHz — MC14053B

tPLH, tPHL

ns

* The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA

MC14051B MC14052B MC14053B 3

Perpustakaan Unika

VDD

VDD V DD

IN/OUT

OUT/IN

VEE

VDD LEVEL CONVERTED CONTROL

IN/OUT

OUT/IN

CONTROL

VEE

Figure 1. Switch Circuit Schematic

TRUTH TABLE

16

Control Inputs ON Switches

Select Inhibit

C*

B

A

MC14051B

0 0 0 0

0 0 0 0

0 0 1 1

0 1 0 1

X0 X1 X2 X3

0 0 0 0

1 1 1 1

0 0 1 1

0 1 0 1

X4 X5 X6 X7

1

x

x

x

None

MC14052B Y0 Y1 Y2 Y3

X0 X1 X2 X3

MC14053B Z0 Z0 Z0 Z0

Y0 Y0 Y1 Y1

X0 X1 X0 X1

Z1 Z1 Z1 Z1

Y0 Y0 Y1 Y1

X0 X1 X0 X1

None

None

* Not applicable for MC14052 x = Don’t Care

16

INH A B C

6 11 10 9

VDD

8 X0 13 X1 14

VSS

7

VEE

X2 15 X3 12

3 X

X4 1 X5 5 X6 2 X7 4

Figure 2. MC14051B Functional Diagram

VDD 16

INH 6

BINARY TO 1–OF–4 DECODER WITH INHIBIT

LEVEL CONVERTER

A 10 B 9 8 X0 12 X1 14

VSS

7

BINARY TO 1–OF–8 DECODER WITH INHIBIT

LEVEL CONVERTER

INH A B C

VEE

X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4

Figure 3. MC14052B Functional Diagram

MC14051B MC14052B MC14053B 4

6 11 10 9

BINARY TO 1–OF–2 DECODER WITH INHIBIT

LEVEL CONVERTER 8

13 X

VDD

VSS

7

VEE

X0 12

14 X

X1 13 Y0 2 3 Y

15 Y

Y1 1 Z0 5

4 Z

Z1 3

Figure 4. MC14053B Functional Diagram

MOTOROLA CMOS LOGIC DATA

TEST CIRCUITS Perpustakaan Unika

ON SWITCH CONTROL SECTION OF IC

A B C

PULSE GENERATOR

Vout

LOAD V

CL

RL

INH

SOURCE VDD VEE

Figure 5. ∆V Across Switch

VEE VDD

Figure 6. Propagation Delay Times, Control and Inhibit to Output

A, B, and C inputs used to turn ON or OFF the switch under test. RL

A B C VSS

Vout

INH

RL

A B C

ON

INH

OFF

CL = 50 pF

Vout

Vin

RL

VDD – VEE 2

VDD – VEE 2

Figure 7. Bandwidth and Off–Channel Feedthrough Attenuation

CL = 50 pF

Vin

Figure 8. Channel Separation (Adjacent Channels Used For Setup)

OFF CHANNEL UNDER TEST

A B C

Vout RL

INH

CONTROL SECTION OF IC

VDD VEE OTHER CHANNEL(S)

VEE VDD

CL = 50 pF

R1 COMMON

VEE VDD

Figure 9. Crosstalk, Control Input to Common O/I

Figure 10. Off Channel Leakage

NOTE: See also Figures 7 and 8 on Page 6–51.

MOTOROLA CMOS LOGIC DATA

MC14051B MC14052B MC14053B 5

VDD

KEITHLEY 160 DIGITAL MULTIMETER

Perpustakaan Unika

10 k 1 kΩ RANGE

VDD

X–Y PLOTTER

VEE = VSS

Figure 11. Channel Resistance (RON) Test Circuit

300

300

250 200 150

TA = 125°C

100

25°C – 55°C

50 0 – 10

RON , “ON” RESISTANCE (OHMS)

R ON , “ON” RESISTANCE (OHMS)

350

– 8.0 – 6.0 – 4.0 – 2.0

0

0.2

4.0

6.0

8.0

250 200 150

25°C – 55°C

50 0 – 10

– 8.0 – 6.0 – 4.0 – 2.0

0

0.2

4.0

6.0

8.0

Vin, INPUT VOLTAGE (VOLTS)

Vin, INPUT VOLTAGE (VOLTS)

Figure 12. VDD = 7.5 V, VEE = – 7.5 V

Figure 13. VDD = 5.0 V, VEE = – 5.0 V

700

350

600

300

500 400 300 TA = 125°C 200 25°C 100 0 – 10

TA = 125°C

100

10

R ON , “ON” RESISTANCE (OHMS)

R ON , “ON” RESISTANCE (OHMS)

TYPICAL RESISTANCE CHARACTERISTICS 350

– 55°C – 8.0 – 6.0 – 4.0 – 2.0

0

0.2

4.0

6.0

8.0

10

TA = 25°C

250

VDD = 2.5 V

200 150 5.0 V 100

7.5 V

50 0 – 10

10

– 8.0 – 6.0 – 4.0 – 2.0

0

0.2

4.0

6.0

8.0

Vin, INPUT VOLTAGE (VOLTS)

Vin, INPUT VOLTAGE (VOLTS)

Figure 14. VDD = 2.5 V, VEE = – 2.5 V

Figure 15. Comparison at 25°C, VDD = – VEE

10

PIN ASSIGMENT MC14051B

MC14052B

MC14053B

X4

1

16

VDD

Y0

1

16

VDD

Y1

1

16

VDD

X6

2

15

X2

Y2

2

15

X2

Y0

2

15

Y

X

3

14

X1

Y

3

14

X1

Z1

3

14

X

X7

4

13

X0

Y3

4

13

X

Z

4

13

X1

X5

5

12

X3

Y1

5

12

X0

Z0

5

12

X0

INH

6

11

A

INH

6

11

X3

INH

6

11

A

VEE

7

10

B

VEE

7

10

A

VEE

7

10

B

VSS

8

9

C

VSS

8

9

B

VSS

8

9

C

MC14051B MC14052B MC14053B 6

MOTOROLA CMOS LOGIC DATA

APPLICATIONS INFORMATION Figure A illustrates use of the on–chip level converter detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control signal is used to directly control a 9 Vp–p analog signal. The digital control logic levels are determined by VDD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD – VSS = 5 V maximum swing above V SS ; V SS – V EE = 5 V maximum swing below VSS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients

above VDD and/or below VEE are anticipated on the analog Perpustakaan Unika channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE. For example, V DD = + 10 V, V SS = + 5 V, and V EE – 3 V is acceptable. See the Table below.

+5 V

–5 V VDD

VSS

VEE + 4.5 V

9 Vp–p ANALOG SIGNAL

SWITCH I/O MC14051B MC14052B MC14053B

+5 V

EXTERNAL CMOS DIGITAL CIRCUITRY

0–TO–5 V DIGITAL

COMMON O/I

9 Vp–p ANALOG SIGNAL

GND

– 4.5 V

INHIBIT, A, B, C

CONTROL SIGNALS

Figure A. Application Example VDD

VDD

DX

DX ANALOG I/O

COMMON O/I

DX

DX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VEE

VEE

Figure B. External Germanium or Schottky Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS VDD In Volts

VSS In Volts

VEE In Volts

Control Inputs Logic High/Logic Low In Volts

+8

0

–8

+ 8/0

+ 8 to – 8 = 16 Vp–p

+5

0

– 12

+ 5/0

+ 5 to – 12 = 17 Vp–p

+5

0

0

+ 5/0

+ 5 to 0 = 5 Vp–p

+5

0

–5

+ 5/0

+ 5 to – 5 = 10 Vp–p

+ 10

+5

–5

+ 10/ + 5

+ 10 to – 5 = 15 Vp–p

MOTOROLA CMOS LOGIC DATA

Maximum Analog Signal Range In Volts

MC14051B MC14052B MC14053B 7

OUTLINE DIMENSIONS Perpustakaan Unika

L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16

9

1

8

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–B– C

L

DIM A B C D E F G H K L M N

–T– K

N

SEATING PLANE

M

E F

J

G D

16 PL

0.25 (0.010)

16 PL

0.25 (0.010)

M

T A

T B

M

S

INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040

MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01

S

P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.

–A– 16

9

1

8

B

F

C

L

S –T–

SEATING PLANE

K

H G

D

J

16 PL

0.25 (0.010)

MC14051B MC14052B MC14053B 8

M

T A

M

M

DIM A B C D F G H J K L M S

INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040

MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS Perpustakaan Unika

D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A–

16

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

9

–B– 1

P

8 PL

0.25 (0.010)

8

M

B

S

G

R

K

F

X 45 _

C –T–

SEATING PLANE

M D

16 PL

0.25 (0.010)

M

T B

S

A

S

J

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MOTOROLA CMOS LOGIC DATA ◊

*MC14051B/D*

MC14051B MC14052B MC14053B MC14051B/D 9