IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 27, NO. 8, OCTOBER 2009

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On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems Felix Gutierrez, Jr. Student Member, IEEE, Shatam Agarwal, Student Member, IEEE, Kristen Parrish, Student Member, IEEE, and Theodore S. Rappaport, Fellow, IEEE

Abstract—This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for wireless personal area networks (WPANs) promise to reduce interconnection losses and greatly reduce wireless transceiver costs, while providing unprecedented flexibility for device manufacturers. This paper presents the current state of research in on-chip integrated antennas, highlights several pitfalls and challenges for on-chip design, modeling, and measurement, and proposes several antenna structures that derive from the microwave microstrip and amateur radio art. This paper also describes an experimental test apparatus for performing measurements on RFIC systems with on-chip antennas developed at The University of Texas at Austin. Index Terms—WPAN, 60 GHz, RFIC, CMOS, on-chip antenna, millimeter wave, mmWave communications, passive radiating elements.

I. I NTRODUCTION

W

ITHIN the past decade, the wireless communications community has become increasingly interested in the worldwide 60 gigahertz (GHz) radio frequency (RF) band [1], [2], [3], [4], [5], [6], [7], [8]. In 2001, the United States Federal Communications Commission (FCC) released 7 GHz of bandwidth (57-64 GHz) for unlicensed use, while other governments have similarly allowed portions of the 60 GHz band to be used without a license. While the precise frequency allocation is different in each country, all bands share a common 5 GHz of continuous bandwidth centered at 60 GHz (see Figure 1). The IEEE 802.15.3c WPAN committee has been advancing technologies in this frequency band since 2003. With such a large RF bandwidth available at 60 GHz, data rates of several gigabits per second (Gbps) are attainable within local areas, greatly surpassing possible wireless transmission capability. Wireless personal area networks (WPANs) at 60 GHz will revolutionize the home, workplace, and classroom, and will enable a vast array of applications, such as uncompressed high definition media transfer. Libraries of books, high definition movies, and data files will be transferred in seconds.

Manuscript received 1 April 2009; revised 31 March 2009. All authors are with the Wireless Networking and Communications Group (WNCG), in the Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, 78712. Portions of this work have been submitted for presentation in IEEE Globecom 2009. This project is funded by the US Army Research Laboratory under contract number W011F-08-1-0438, and the WNCG Industrial Affiliates program (e-mail: [email protected], [email protected], [email protected], [email protected]). Digital Object Identifier 10.1109/JSAC.2009.091007.

Fig. 1.

60 GHz frequency bands in various countries, from [5], [6].

In order for 60 GHz technology to be adopted rapidly, device and system costs must be kept as low as possible. Integrated circuit (IC) fabrication processes such as SiGe and GaAs are suitable for analog circuits operating at 60 GHz, but are relatively expensive. Fully integrated CMOS offers the greatest cost savings and highest yield, especially when considering packaging, integration, and interconnect issues. CMOS IC technology, which has been optimized for digital circuitry and is used extensively by most fabless semiconductor manufacturers throughout the world, is a cost effective solution for millimeter wave RF devices. As described in the literature [9], [10], [11], [12], [13], [14], [15], [16], RF circuits and systems operating at 60 GHz using CMOS technology are now viable and can be produced using standard fabless techniques at foundries such as TSMC and UMC. However, integration of the antenna with the RF electronics on one chip in a single, standard fabrication cycle, is a novel approach that has only recently received attention. Implementing an antenna in the same semiconductor process as integrated circuits is called an integrated antenna, and has been pioneered in [17], [18], [19], but the utility and value of this approach in a single fabrication process is most apparent for millimeter wave systems [10], [11], [20], [16]. While other authors have made use of techniques such as the dielectric lens, these techniques require extensive deviation from the standard CMOS process [21], [22], [23]. If the radiating elements of a 60 GHz transceiver could be integrated with the other electronics on a single chip in a standard CMOS process, a great deal of cost savings would be realized, both at the chip level, as well as for the manufac-

c 2009 IEEE 0733-8716/09/$25.00 

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turer of the wireless product. Today, wireless communication devices such as personal computers and cell phones typically contain six or more separate radio transceivers. For example, standard laptops already have transceivers for Bluetooth, WiFi, Cellular (Wide Area Network), dual band PCS, and UWB radios contained in a single consumer product. The number of radios in a laptop computer or high-end cell phone will only increase over time, and it is clear that more standards and technologies will dictate the need for as many as 12 to 14 radios in high end personal communicators by the year 2012. By producing on-chip antennas in a standard CMOS circuit fabrication cycle, multiple manufacturing issues are eliminated or lessened. Unshielded “windows” in the device casing could allow RF waves to propagate to and from the on-chip antenna, enabling manufacturers to eliminate complex embedded antenna and expensive feedlines and cabling that are used today. At 60 GHz, the physical dimensions of antennas are such that they can fit on a small (e.g. 5mm X 5mm) die, suggesting that an entire system on a chip can be manufactured inexpensively in one step without any special packaging or difficult assembly or wiring. Even if on-chip antennas are fabricated as stand alone chips, separate from the bulk of RFIC electronics, the savings and design flexibility realized by original equipment manufacturers (OEMs) of consumer electronic (CE) devices (e.g. laptops, set top boxes, cell phones, etc.) would be substantial. If antennas became simple socket solutions, OEMs could simply place many low cost antenna chips throughout the printed circuit board (PCB) while using simple PCB transmission lines and switching/phasing to provide arbitrarily high-gain radiation patterns that work in concert with the particular mechanical and physical layout and shielding of a CE device. Essentially, on chip antennas, whether passive or active (with basic RF amplification stages), would provide many degrees of freedom for the design and implementation of CE devices, while eliminating or greatly reducing the Bill of Material Costs for RF antennas. The large antenna gains and pattern flexibility at 60 GHz will support reliable low power, high bandwidth communications over short distances with minimal power drain, as the antenna gains are traded for transmitted power consumption to overcome RF propagation losses and obstructions in the channel [7], [8]. Unfortunately, combining RFIC electronics with integrated antennas at 60 GHz poses several major challenges. One major issue is the materials used in standard CMOS technology are not optimized for millimeter wave structures, thus as the operating frequency approaches the millimeter wave regime, device performance deteriorates due to losses in the metallization layers as well as losses in the doped bulk silicon substrate. Additionally, models for passive and active devices at 60 GHz are not yet thoroughly proven and are continuing to evolve. The discrepancy between simulation and actual performance of 60 GHz radiating devices introduces the need for extensive iterations to improve today’s simulation tools. Determining radiating fields from the CMOS substrate requires robust and accurate field solvers, and many of the commercial field solvers have not been rigorously tested or verified by measurement at 60 GHz and above. Furthermore, specialized measurement systems are needed to experimentally determine radiation efficiencies, gains, and impedances of on-chip anten-

nas. Researchers must develop a strong feedback loop between proven millimeter wave simulation capabilities, fabrication techniques, and measurement capabilities of devices in order to develop design guidelines for on-chip antennas at 60 GHz. Finally, after the challenges of fabricating an antenna onto a substrate are met, the integration of this antenna with active circuitry introduces more challenges. On-chip antennas operate best when mounted on thick, low dielectric substrates. However, active components perform better on thin, high dielectric substrates [24]. Therefore, in theory, one cannot implement maximally performing circuitry on the same chip as an optimal antenna. Also, an on-chip antenna could radiate onto RF circuitry contained in the same chip, which could cause deleterious electromagnetic interference (EMI). This paper summarizes the emerging field of integrated antennas. Section II describes recently reported results in the field of 60 GHz integrated antennas. Section III presents several novel antenna concepts, with extensive simulation results. These antenna concepts indicate promising approaches, as well as challenges that must be overcome. Section IV describes an experimental measurement system developed at The University of Texas at Austin for the test and measurement of on-chip antennas and RFICs up to 67 GHz. The paper concludes with a synopsis of results from this work. II. PAST W ORK IN 60 GH Z O N - CHIP A NTENNAS Previous researchers have reported on-chip antennas using CMOS processes for use in the 60 GHz band. Several different antenna configurations have been simulated, fabricated, and to a much lesser extent, verified by measurement. Y. P. Zhang, et al., have implemented both inverted-F and quasi-Yagi antennas on a standard low resistivity substrate (10 Ωcm) [25]. These antennas were implemented with a specialized BEOL technology to overcome the challenges caused by the substrate. In this fabrication, proton implantation in the substrate is used to increase the resistivity, reduce substrate losses, and improve performance. The maximum radiation for the inverted-F antenna occurred above the antenna, and radiation along the horizon (off the edge of the chip) was 32 dB weaker than at the zenith (directly above the chip). Using the Zeland IE3D simulation tool, the authors found a radiation efficiency of 3.5%, which is unfortunately typical in much of the literature to date. By comparison, typical radiation efficiencies for antennas in free space are much higher, on the order of 70% or more. The quasi-Yagi in [25] was found to exhibit maximum gain in a direction directly above the substrate of the chip (at zenith), and not off the end of the chip (on the horizon) as would be expected for a Yagi antenna in free space. The maximum gain was measured as -12.5 dBi at 65 GHz. Simulated radiation efficiency was 5.6%. The crosspolarization radiation for this antenna (shown in Figure 6 of [25]) is significantly weaker than the copolarization radiation. While return loss and maximum gain were measured with a probe station and network analyzer using a method described in [25], the authors did not measure radiation patterns. Also, the authors defined their simulation substrates as an infinite perfectly conductive ground plane. This simple yet unrealistic assumption can greatly alter simulation results.

GUTIERREZ et al.: ON-CHIP INTEGRATED ANTENNA STRUCTURES IN CMOS FOR 60 GHZ WPAN SYSTEMS

In 2008, researchers from National Cheng Kung University created a coplanar waveguide (CPW) feedline and an onchip 3-element Yagi antenna in standard 0.18 μm CMOS technology [26]. The authors used Ansoft HFSS to simulate the antenna structure and obtain a radiation efficiency of approximately 10%. As in [25], no radiation measurements were made for the on-chip antenna. Antenna gain was reported as -10.6 dBi at 60 GHz. These same authors also implemented a triangular monopole antenna in the same 0.18 μm CMOS technology [27]. The simulated radiation efficiency of this antenna was approximately 12%. The maximum value of the gain was calculated from S-parameters to be -9.4 dBi at 60 GHz. It is clear from past works that the design and implementation of on-chip antennas is difficult and very inefficient. Most of the structures presented in literature radiate with maximum gain directly above the chip (0 ◦ from zenith), and not off the end (approaching the horizon) as a typical Yagi or horizontally oriented antenna would behave in free space. Gain and radiation efficiencies are very poor, typically yielding gains of -12 dBi to -16 dBi. Additionally, antenna radiation patterns have not been measured for any of the antennas in [27], [26], [25]. III. N EW C ONCEPTS FOR 60 GH Z I NTEGRATED A NTENNAS One challenge with designing antennas to be fabricated onchip is the small distance (typically several microns) between radiating elements, the surrounding metal layers, and the bulk silicon of the IC. Interactions with the ground plane and the lossy silicon substrate causes near field energy to dissipate rapidly around the antenna, which greatly reduces radiation efficiency and gain. Researchers and amateur (ham) radio operators have long known of the issues of transmitting over ground planes. Hams have designed passive high-gain antennas to communicate over great distances throughout the world. Stacking and phasing these directional antennas in an array boosts gains even further at HF frequencies. By adapting passive directional antennas in the amateur radio art at frequencies between 1 and 30 MHz, it is conceivable to create high gain antennas at millimeter-wave frequencies on ICs by properly scaling antenna dimensions. Antennas such as the rhombic [28], the Yagi, the long wire [29], and even low-profile [30] and loop antennas [31] have been commonly used in amateur radio, but are now considered for the novel application of passive integrated millimeter wave antennas. This section considers the design of popular HF antennas (the dipole, Yagi, rhombic and loop) for use at millimeter wave frequencies on a CMOS substrate. A. Overview of simulation methods We considered a substrate model for standard CMOS 0.18μm IC technology as shown in Figure 2. We model a chip with common dimensions of 5 mm x 5 mm with 6 metal layers above bulk silicon. Since the modeled ground plane is confined to the dimensions of the chip, diffraction may introduce radiation on the lower hemisphere (below the

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Fig. 2. Illustration of IC model including silicon dioxide layers for a typical CMOS integrated circuit. Not to scale.

die). The dielectric between metal layers (silicon dioxide) is modeled as lossless, while the losses in silicon bulk substrate are modeled with conductivity (σ) of 10 S/m, as in [25] and in [32]. Realistic millimeter wave antennas were modeled with Ansoft HFSS (High Frequency Structural Simulator), a leading commercial finite element method field solver which simulates three-dimensional structures and produces S-parameters and radiation patterns. HFSS is used in both [26] and [27] , as well as numerous other works. The effective wavelength at 60 GHz for an IC substrate is estimated by using the frequency and material properties of the top IC layer (silicon dioxide, r = 3.9), where

λef f = √

1 λf reespace = √ 0 μ0 f

(1)

1 λf reespace 1 = √ = . √ μf 0 r μ0 f r

(2)

where λfreespace is 5 mm for 60 GHz, and λeffective is calculated by including the effect of the dielectric constant. Here, λeffective = 2.53 mm. We explored on-chip antennas based on the basic half-wave dipole, the multi-element Yagi, the rhombic antenna, and the loop antenna. These simple antennas have historically been very reliable and provide reasonable gain, high front-to-back and front-to-side ratios, and radiation near the horizon. We identified the following key issues: a) how performance is a function of on-chip placement of radiating elements; b) how design guidelines should be applied to on-chip antenna design, and how these guidelines differ from standard antenna design in free space above ground; c) the tolerances that exist between the widths, lengths, and spacings for various radiating and parasitic on-chip elements; and d) the maximum achievable gain, and the direction of this maximum gain, for a wide range of new integrated passive on-chip antennas. B. Feed systems In order to accurately simulate antennas, the feed systems that carry the signal from the on-chip circuit output to the antenna inputs must also be simulated with a 50 Ω source. Simulations of antennas without feed systems were slightly different from those of the antennas fed by simple feed structures. Two feed systems were examined in simulation. The concept of stacked vias was used to form these feed lines. For the dipole antenna, a via is extended from Metal 6

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Fig. 3.

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 27, NO. 8, OCTOBER 2009

Feed system for the dipole antenna.

Feed system for the Yagi antenna.

down to Metal 1, to transfer the signal from an inner layer to the top layer. For initial calculations, we approximated the two parallel vias as a parallel plate waveguide, in order to derive dimensions that would approach a 50 Ω impedance. From [33], the parallel plate feedline has an impedance of Zo = η wb , where w is the width of the transmission line plates, b is the spacing between plates, and η is the intrinsic impedance in the material. By noting that η in silicon dioxide is approximately half of η in free space, we deduced the proper spacing between the two feed plates should be approximately 1 4 the width of the dipole elements to maintain a 50 Ω impedance. This feed system is shown in Figure 3. Metal 1 is the lowest metal layer, where RF electronics interconnect, and Metal 6 is the top layer, where antenna elements would most likely be fabricated. The signal is fed from the on-chip output to the Metal 1 layer and connected to the antenna on Metal 6 by a stack of vias on each side. For the Yagi antenna, a slightly different via feed system was used, shown in Figure 4. The Yagi feed had wider vias compared to the parallel plate transmission line used in the dipole model (discussed below), in order to demonstrate the sensitivity of feed line performance to manufacturing variability. Our simulations showed negligible differences between the two feed systems. The rhombic and loop antennas were fed directly with a 60 GHz source and a 50 Ω source impedance. Due to the

Fig. 5. Top view of on-chip integrated dipole antenna (not to scale) and radiation pattern for this antenna. Maximum gain is -7.3 dBi (radial power units are in dBi). As indicated, φ is the azimuthal angle in the XY plane, where the X axis is 0 ◦ and the Y axis is 90 ◦ . θ is the elevation angle where the Z-axis is 0 ◦ , and the XY plane is 90 ◦ .

Fig. 6. widths.

S11 characteristics of two dipole antennas with different element

wideband nature of the rhombic antenna, additional matching networks were not necessary to achieve a sufficient impedance match. Unless otherwise stated, all simulations used a source with a standard 50 Ω impedance to excite the antennas. C. On-chip dipole antenna at 60 GHz To understand on-chip antenna properties, we first considered half-wavelength dipoles using a wide range of line widths and orientations. The best performance with respect to gain was obtained by placing a center fed dipole on the edge of the chip (See Figure 5). Using equation (2), an on-chip dipole with leg length λ/4 = 632.5 μm was simulated using a 30 μm antenna width. Each dipole λ/4 element was shortened to 570 μm to shift minimum S11 up to 60 GHz as seen in Figure 6. Minimum S11 shows an optimal impedance, to improve power transfer and efficiency. When the width of the dipole elements is doubled to 60 microns while keeping the lengths the same, we observed that S11 is minimized at 56.5 GHz (as opposed to 59.5 GHz). If the dipole is mounted on the center of the chip, as opposed to the edge, then the gain is a very poor 13.6 dBi, due to the lossy substrate and the close proximity of the radiation angle to the horizon. As shown in Figure 5, the edge mounted antenna (width of 30 μm) exhibits maximum gain of -7.3 dBi at an elevation angle of 0 ◦ above the substrate horizon (θ = 90 ◦ ), and has a typical broadside pattern. This

GUTIERREZ et al.: ON-CHIP INTEGRATED ANTENNA STRUCTURES IN CMOS FOR 60 GHZ WPAN SYSTEMS

Fig. 7. Top view of three individually simulated two-element on-chip Yagi antennas (not to scale). The Yagi antenna was simulated at the center, lower right corner, and right edge of the 5mm x 5mm chip.

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Fig. 8. S11 (dB) as the reflector is moved away from the driven element. Spacing is measured from the edge of the driven element to the edge of the reflector. Also shown is the centered 597 μm dipole quarter-wave element without any reflector and the scaled 574 μm quarter-wave element dipole with the 0.11λ-spaced reflector.

directionality provides the on-chip circuitry some radiation protection. Radiation efficiency is still poor, at approximately 9%. With element widths of 60 μm, the maximum gain increases to -6.7 dBi, approximately 9 dB less than that of a free space dipole antenna. These significant changes highlight the importance of understanding antenna performance on-chip as it is relatively unknown today. D. On-chip Yagi antenna at 60 GHz The Yagi antenna uses parasitic metals around the dipole to reflect and direct energy to achieve increased gain. There are several degrees of freedom when designing a Yagi antenna, such as the spacing, lengths, and widths of each parasitic element. We examined how spacing and widths affect Yagi performance on silicon, as well as the optimal antenna orientation to achieve maximum gain. Simulations of a 2-element Yagi, consisting of a driven element and a parasitic reflector, showed highest gain when a Yagi antenna was centered along the chip edge as shown in Figure 7. Using a thinner dipole width w = 15 μm, the Yagi dipole (driven element) length was adjusted to maintain a minimum S11 at approximately 60 GHz. Optimal performance was found when each leg of the driven element was increased to  = 597 μm (approximately 5% longer than the single dipole). The center feed spacing between each λ/4 element was 7 μm. We first investigated performance as a function of the distance between the reflector and the driven element of a Yagi antenna. The Yagi dipole was placed at the center of the 5mm x 5mm chip. According to [31], Yagi reflectors in free space should be spaced between 0.15λ and 0.20λ. Given that the Yagi quarter-wave driven element resonated at  = 597 μm, we estimated the wavelength to be 2.388 mm, which is comparable (within 4%) to our result from (2), and denoted this length as λ. A reflector was iteratively positioned from 0.01λ to 0.25λ in increments of 0.01λ away from the dipole. We observed S11 and gain. The reflector width wy was identical to the dipole (15 μm) and the length was set to y = 0.55λ, as suggested by [31]. Figure 8 shows a comparison of S11 of the Yagi antenna as the reflector

Fig. 9. Gain of a dipole vs. a .25λ-spaced reflector Yagi. The left plot is elevation (φ = 90 ◦ ) and the right is azimuth (θ = 90 ◦ ). Radial power units are in dBi.

was moved away from the dipole. Note the S11 resonance is shifted to a lower frequency when a reflector is added and the minimum S11 occurred when the Yagi reflector was 0.11λ away from the dipole. To bring the resonance back up to 60 GHz using a 0.11λ spaced reflector, each driven element was scaled down to 574 μm in order to resonate at the appropriate frequency, denoted in Figure 8. Gains also increased slightly with the addition of the reflector, which is consistent with antenna theory [31]. Gains also increased as the reflector was moved away from the dipole. At spacings between 0.20λ and 0.25λ, the maximum gains were very similar, with a reflector distance of 0.25λ having the highest gain at the horizon, shown in Figure 9. At distances larger than 0.25λ, gain was further diminished. Thus, it appears Yagi antennas with a 0.25λ reflector spacing exhibit both a reasonable S11 to a 50Ω source impedance and maximum horizon gain. With a 0.25λ spacing between the driven element and the reflector, we investigated the role of reflector width in Yagi performance. The spacing was held constant at 0.25λ from the edge of the driven element to the edge of the reflector. S11 decreased slightly by 1 dB overall as the reflector width was increased from 15 μm to 160 μm. We noted incremental gain increases as width was increased, differing only by 0.5 dB over the entire range of widths. This shows that the width of the reflector conductor does not appreciably impact gain or

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Fig. 12.

S11 (dB) parameter as the Yagi antenna is moved across the chip.

Fig. 10. S11 changed drastically as the 60 GHz on-chip Yagi antenna was moved to different locations on the IC. “Edge” denotes right edge, and “Edge Edge” denotes lower right corner. “Dipole” is the 597 μm dipole placed at the center.

Fig. 13. Antenna gains as the Yagi antenna is moved across the chip. The left plot is elevation (φ = 90 ◦ ) and the right is azimuth (θ = 90 ◦ ). Radial power units are in dBi. The radiation plots from Figure 9 are reproduced here.

Fig. 11. Reactance (the imaginary part of impedance) was measured for each antenna. Note that the center-located Yagi had a reactance close to zero and provided the best S11 response at 60 GHz.

impedance matching of the on-chip Yagi. As we will show subsequently, this does not hold true for rhombic antennas. Next, we investigated how Yagi performance changes as the antenna is moved across the chip. We used the 0.25λspaced reflector with width 160 μm. We placed the antenna at the center, right edge, and lower right corner of the chip as seen in Figure 7. We noted large variations in S11 as the Yagi antenna moved from the center of the chip to the edges, as seen in Figure 10. The minimum S11 occurred at frequencies above 60 GHz as shown. Adjusting the lengths of the driven elements gave minimum S11 at 60 GHz, though did not provide an acceptable impedance match (S11 is larger than -10dB, even at the minimum). This emphasizes the value of choosing the appropriate location for on-chip antennas. Figures 12 and 13 show the resulting S11 and gain changes as the antenna is moved, respectively with adjusted impedance. The performance is compared to that of a dipole at the center of the chip. The 2-element Yagi along the right corner of the chip achieved the highest gain of -3.55 dBi, a front-to-back ratio of 10.4 dB, and maximum radiated intensity at 20 ◦ above the horizon. The efficiency was 15.8%, which is much greater than the numbers reported in [27], [26], [25]. By moving the Yagi antenna to an edge, maximum gains improved by 7.65 dB compared to the Yagi located at the center of the chip and by 10.05 dB over a dipole at the center of the chip.

Impedance transformation components may be necessary to improve the impedance match to an acceptable level. The impedances of the Yagi antennas at each location were extracted (Figure 11). We noted that the centered Yagi’s reactance close to zero provided excellent S11, and we proceeded to adjust the 50 Ω source impedance by the respective amounts for the edge and corner Yagi. The source impedance fed to the Yagi along the edge was adjusted to 50 + j33 Ω and the source impedance fed to the Yagi at the corner was adjusted to 50 + j60 Ω. E. On-chip rhombic antenna at 60 GHz The rhombic antenna is a diamond shaped broadband directional antenna commonly used in the 3 - 30 MHz frequency range by shortwave broadcast stations and ham radio operators. Large rhombic structures are constructed several meters above ground. Here we consider scaling them to onchip solutions. To implement a true rhombic antenna, each leg of the antenna must be longer than two wavelengths [34]. This poses a problem for on-chip antenna designers: if λ in the material is approximately 2.5 mm, we are barely able to fit a leg of length 2λ on the edge of our 5 mm chip, although larger chips could easily be fabricated for more directive passive antennas. We considered a rhombic antenna along the perimeter of the chip where each leg length is approximately 4.9 mm (nearly 2λ) as shown in Figure 14. The rhombic and loop antennas were fed with a 60 GHz source and a 50 Ω source impedance. Two primary design parameters of a rhombic antenna in free space are the angle γ (indicated in Figure 14) and the height

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(a) Gain vs. angle γ. Maximum horizon gain observed at 39 ◦ . Fig. 14. Top view of a simulated 60 GHz on-chip rhombic antenna. The rhombic angle γ and trace width are indicated. The point where the antenna is connected to the 60 GHz source is denoted ”Feed Points”.

above ground. The ground height is analogous to the substrate thickness of the chip in our model and can be optimized using wafer thinning techniques. A third rhombic design parameter, exclusive to small scale antennas such as an on-chip antenna, is trace width (indicated in Figure 14. These three design parameters were varied to ascertain the performance of onchip rhombic antennas operating at 60 GHz. The first design parameter tested was the rhombic angle, γ. The substrate thickness was held constant at 750 μm, feed points were separated by 3 μm, and trace width was 10 μm. The angle γ, was incremented from 5 ◦ to 45 ◦ . Antenna gain at the horizon (φ = 90 ◦ , θ = 90 ◦ ) as well as maximum gain were observed. The results in Figure 15(a) show that the angle of largest horizon gain is γ = 39 ◦ . Using γ = 39 ◦ , the substrate thickness was decreased from 750 μm to 50 μm. The results shown in Figure 15(b) demonstrate that horizon gain increases as the substrate thickness is decreased. An optimal value for horizon gain is observed at 110 μm thickness which is λ/23 (λ with respect to r = 3.9). A thinner substrate allows higher gains and efficiencies since the degrading effects of the lossy silicon substrate are reduced. Using both a γ = 39 ◦ rhombic angle, and a 110 μm substrate thickness, the trace width of the on-chip rhombic was increased from 10 μm to 1900 μm. The results are shown in Figure 15(c). The maximum horizon gain occurs with a trace width of 1445 μm (about 57%λ) with a gain nearly -3 dBi. The angle of maximum gain begins to shift from the horizon as trace width increases. Generally, free space rhombic antennas are constructed of electrically thin copper wires, so the thickness of these wires is not a design parameter. However, repeated tests have shown that on-chip rhombic antenna performance is enhanced with thicker trace widths. Figure 16 shows a comparison between a conventional rhombic antenna with thin trace widths and a higher gain rhombic antenna with thicker trace widths. Azimuth and elevation radiation plots are presented in Figure 16. The rhombic antenna with trace width 200 μm achieves a horizon gain of -8 dBi while the rhombic with trace width = 1445 μm can achieve a greater horizon gain close to 0 dBi.

(b) Gain vs. substrate thickness. Maximum gain observed at 110 μm.

(c) Gain vs. trace width. Maximum horizon gain observed at 1445 μm. Fig. 15. Gain of the 60 GHz on-chip antenna as a function of (a) angle γ, (b) substrate thickness, and (c) trace width. Maximum gain occurred at an angle of 39 ◦ , substrate thickness of 110 μm, and trace width of 1445 μm. ”Max Gain” denotes the maximum antenna gain while ”Horizon Gain” denotes the gain at φ =90 ◦ , θ =90 ◦ ).

The rhombic antenna has been optimized with respect to horizon gains; however, to transfer maximum power to the antenna, the S11 should be minimized at 60 GHz. If a matching network is not available to minimize S11, the width of the feed points can be adjusted. The rhombic feed width was adjusted to 660 μm (26% of λ) to obtain an acceptable impedance match to the standard 50 Ω source impedance. This caused the S11 to decrease to a flat -13 dB and thus allow most of the available power to be accepted by the antenna when transmitting. Additionally, the horizon gain of the antenna slightly increased from -3 dBi to -1.27 dBi with the increased feed width. The S11 of -13 dB for the on-chip rhombic antenna

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Fig. 17. Top view of a simulated 60 GHz on-chip square loop antenna. Three design parameters namely, the leg length, the trace width and the feed width are indicated.

Fig. 16. Comparison of two 60 GHz on-chip rhombic antennas. Increasing trace widths increases horizon gains, as seen in the radiation plots (φ = 90 ◦ , θ = 90 ◦ , radial units in dBi). The wide rhombic antenna showed gains increased by 6-8 dBi when trace widths were increased from 200 μm to 1445 μm.

was flat across the entire 57-64 GHz band which shows wide bandwidth. The optimized rhombic antenna with radiation pattern is shown in Figure 16. Horizon gain was -1.27 dBi and overall maximum gain was -0.2 dBi. The radiation efficiency was 85%, due primarily to a thinned lossy substrate. These gains occurred with γ = 39 ◦ , 110 μm substrate thickness, 1445 μm trace width, and a feed width of 660 μm. Although the simulation results are promising for the rhombic, the size of the antenna and the area used by it on the chip may cause electromagnetic interference with circuit components, thus suggesting several rhombics may best be packaged as a stand alone passive chip. F. On-chip loop antenna at 60 GHz The loop antenna is a simple and versatile antenna type used extensively in AM radio and military applications. Loop antennas can be classified into two categories: electrically small, with circumferences (C) less than one-tenth of a wavelength (C < λ/10), and electrically large, whose circumference is approximately a free-space wavelength (C ∼ λ) [35], [36]. The gain of a loop antenna is directly proportional to its area; the larger the loop, the greater the gain [31], [35]. Small loop antennas are therefore poor radiators, and are seldom used for transmission in radio communications. They are, however, employed at the receiving station because of their lower loss resistance, thus exhibiting higher signal-to-noise ratio. We examined the performance of a large square loop antenna on chip, with overall lengths between 2λ and 4λ. Antenna circumferences than these lengths approach rhombic sizes which are discussed in the preceding section. We considered a square loop antenna at an edge of the chip, where each leg length could vary between 1.25 mm (λ/2) and 2.5 mm (λ), as shown in Figure 17. The antenna was fed with a

60 GHz source and a 50 Ω impedance. The design parameters of an on-chip loop antenna include the leg length, the substrate thickness, the trace width, and the distance between the feed points. These parameters, indicated in Figure 17, were varied in order to obtain the optimal performance of the 60 GHz onchip loop antenna. The first design parameter examined was the substrate thickness. Since the maximum gain in the rhombic antenna was observed for a trace width of 1445 μm, we scaled this dimension by a factor of 4 (ratio of rhombic leg lengths to loop leg lengths = 2λ:λ/2 = 4:1), to obtain a starting value of the trace width for the loop, equal to 360 μm. The feed width was held constant at 3 μm. The substrate thickness was incremented from 50 μm to 700 μm, and the antenna gain at the horizon as well as the maximum gain were observed, for five different leg lengths between λ/2 and λ. The results in Figure 18 show that the maximum gains are obtained for substrate thicknesses between 100 μm and 300 μm. Hence, we chose an average value of 200 μm for the substrate thickness for further analysis. Using the substrate thickness as 200 μm, trace width was then varied for different leg lengths. Figure 19 shows the variation of the maximum and the horizon gain with the trace width for a λ leg length loop antenna. While the maximum gain peaks at a trace width of 1 mm, the horizon gain achieves a peak at a trace width of 0.82 mm. Similar experiments were completed for the leg lengths and the trace widths, with the parameters resulting in the optimal maximum and horizon gain recorded. We observed that the maximum gain begins to shift from the horizon as the trace width increases. Figure 20(a) shows the variation of these optimal trace widths with respect to leg length. This demonstrates a design guideline that can be used when designing 60 GHz on-chip loop antennas of a specific length. For example, from the figure, a trace width of 600 μm would result in the maximum horizon gain for a 2 mm (4λ/5) leg length loop antenna. Using the optimal trace widths, the maximum and horizon gain variation with leg length is shown in Figure 20(b). The gains increase with the increasing leg length. This is an expected result as the loop gains are directly proportional to the loop area [35].

GUTIERREZ et al.: ON-CHIP INTEGRATED ANTENNA STRUCTURES IN CMOS FOR 60 GHZ WPAN SYSTEMS

(a) Max. Gain vs substrate thickness for different leg lengths

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(a) Trace widths resulting in best maximum and horizon gain vs leg length. A λ/2 leg length loop antenna exhibits best gains at a trace width of 320 μm.

(b) Horizon Gain vs. substrate thickness for different leg lengths

(b) Maximum and Horizon Gain vs leg length, using the trace widths given by Figure 20(a). A λ leg length loop exhibits a maximum gain of -3.5 dBi and a horizon gain of -4.1 dBi.

Fig. 18. (a) Max Gain and (b) Horizon Gain variations with substrate thickness for 5 different leg lengths between λ/2 and λ. Trace width and feed width equal 360 μm and 3 μm respectively. Maximum gains are obtained for substrate thicknesses between 100 μm and 300 μm.

Fig. 20. A useful guideline in terms of (a) optimal trace widths for a specific leg length loop antenna and (b) the respective gains obtained. The λ leg length loop antenna exhibits the maximum gain of -3.5 dBi at 1 mm trace width.

Fig. 19. Gain vs trace width for a λ leg length loop antenna. The maximum gain and the horizon gain attain peaks at trace widths equal to 1 mm and 0.82 mm, respectively.

Using the optimal loop antenna obtained with dimensions λ leg length, 1 mm trace width, and 200 μm substrate thickness, we increased the feed width from 3 μm to 340 μm. As observed in rhombic antennas, the antenna gains increased with increasing feed widths, as shown in Figure 21. The maximum gain and the horizon gain equaled -1.2 dBi and -3.4 dBi, respectively, at a feed width of 340 μm. Increasing the feed widths minimized the S11 at 60 GHz and hence

Fig. 21. Gain vs feed width for a λ leg length loop antenna. The maximum gain and the horizon gain attain peaks at feed width equal to 340 μm.

ensured better power transfer to the antenna. Figure 22 shows the variation of the S11 parameter for different feed widths, the minimum being -23 dB for a feed width of 340 μm. Similar to the rhombic antenna, the bandwidth of the on-chip loop antenna is wide and spans the entire 57-64 GHz frequency band. The optimized loop antenna with radiation pattern is shown in Figure 23. The overall gain obtained was equal to -1.2 dBi, while the horizon gain equal to -3.5 dBi. The radiation efficiency was 77%. The optimal loop antenna results were

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Fig. 24.

Measurement facilities in the WNCG lab at UT Austin

Fig. 25.

Proposed far-field measuring capability.

Fig. 22. S11 plots for different feed widths for a λ leg length loop antenna. The minimum S11 obtained is equal to -23 dB for a feed width of 340 μm.

Fig. 23. Radiation plot of the optimized on-chip loop antenna (φ = 90◦ , θ = 90◦ , radial units in dBi)

obtained with 2.5 mm (λ) leg length, 1 mm trace width, 200 μm thick substrate, and 340 μm feed width. We also investigated how the performance of the loop antenna changes as it is moved across the chip. We found similar gain and directivity patterns at the edges, center and the sides of the chip. This is in contrast to the behavior of the on-chip Yagi antennas, whose performance varied as they were moved across the chip. This implies that loops can be fabricated anywhere on the chip with no degradation in performance which would be useful for fabricating phased loop-arrays, when multiple loops with similar performance can be phased together to achieve a high gain and directivity at the horizon. Since the area required by a loop antenna is 25% that required by a similar rhombic antenna, loop antennas will have many useful applications in integrated antenna technology. IV. FACILITIES FOR O N -C HIP A NTENNA W ORK AT THE U NIVERSITY OF T EXAS AT AUSTIN The Wireless Networking and Communications Group (WNCG) at The University of Texas has invested approximately $1,000,000 to build a state-of-the-art measurement facility for RF circuitry and on-chip antennas up to 67 GHz (see Figure 24). The facility includes a probe station consisting of several devices for making in-situ measurements on circuit substrates, and allows for thorough characterization of VSWR, gain, coupling losses, as well as other characteristics. By using the probe station and vector network analyzer, it is possible to measure signal strengths transmitted by the insitu IC antenna which are received by a small conical horn antenna. We can find the minimum far-field distance, R, given by [37],

R=

2D2 λ

(3)

where D is the largest antenna dimension. With a maximum dimension of 5 mm (constrained by the chip) and a λ of 5 mm, R is only 10 mm. Hence, a large anechoic chamber or open space is not required for far-field measurements. However, the far field range of the receiving antenna must also be taken into account when determining the appropriate spacing between the two antennas. In order to confirm the simulations discussed above, as well as future on-chip antenna simulations, we are constructing an automated antenna measurement system that makes use of a rotating conical horn antenna. The system in Figure 25 is based on the system described in [38]. In our system, the receiving conical antenna rotates on an axis at a constant distance from the probe-fed IC antenna, acquiring field measurements for one cut of the radiation pattern, where the φ (azimuth) angle is fixed, while the θ (elevation) angle is incrementally stepped. This rotation is automated by a computer-controlled motor that accurately records position data while received power is measured. When one rotational “cut” is completed, the base of the rotation is moved as indicated along the plate edge, changing the φ angle and repeating the θ angle sweep. This system allows us to construct a far field pattern for elevation angles θ = 0 to 80◦ , and all azimuth φ angles. It is crucial that all reflective surfaces and other possible interferers, especially the probe station, be covered with radioabsorbing substance, as in [39]. Pre-test and calibration will

GUTIERREZ et al.: ON-CHIP INTEGRATED ANTENNA STRUCTURES IN CMOS FOR 60 GHZ WPAN SYSTEMS

account for losses from cables, probe tips, and other elements in the measurement system. Deconvolution of radiation from the probe tips, measured while feeding dummy loads, will allow additional multipath effects to be removed. Wideband channel sounding methods may additionally be used here to resolve true patterns. V. C ONCLUSION We have presented various 60 GHz passive antennas simulated for implementation on an integrated circuit. Typical CMOS metals, dielectrics, and substrates were used. Antennas were designed to fit on an IC die size of 5mm x 5mm. The antennas implemented were the dipole, Yagi, rhombic, and loop antennas. We found key relationships between the dipole and the Yagi element spacing and found antenna performance is maximized when the antennas are placed at the edge of the die. Based on S11, the Yagi antenna resonated best with a 0.11λ reflector spacing. When moving from the center of the chip to the right edge, the maximum gains of both the dipole and Yagi antenna increased by nearly 7 dB. At the corner of the chip, the dipole and the 2-element Yagi had maximum gains of -6.7 dBi and -3.5 dBi, respectively. A novel application of the rhombic antenna to IC technology was also explored. Here, we found the optimal angle, substrate thickness and trace width for implementing rhombic antennas in CMOS technology. Using these optimal parameters, simulations showed that it is possible to achieve a maximum antenna gain of -0.2 dBi and horizon gain of 1.27 dBi, the highest reported for any on-chip antenna to date. Similar experiments were performed on a loop antenna, approximately a quarter of the rhombic antenna’s size, yielding a maximum gain of -1.2 dBi. While our results show higher gains than previously reported, on-chip antennas tend to have very low efficiencies and pose a unique challenge for antenna and chip designers. However, integrating antennas with circuitry will greatly advance communications technology by lowering costs and providing unprecedented flexibility for WPAN devices. R EFERENCES [1] T. Manabe, Y. Miura, and T. Ihara, “Effects of antenna directivity and polarization on indoor multipathpropagation characteristics at 60 GHz,” IEEE J Select. Areas Commun., vol. 14, no. 3, pp. 441–448, 1996. [2] P. Smulders, “Exploiting the 60 GHz band for local wireless multimedia access: prospects and future directions,” IEEE Commun. Mag., vol. 40, no. 1, pp. 140–147, Jan 2002. [3] P. Smulders, H. Yang, and I. Akkermans, “On the Design of Low-Cost 60-GHz Radios for Multigigabit-per-Second Transmission over Short Distances [Topics in Radio Communications],” IEEE Commun. Mag., vol. 45, no. 12, pp. 44–51, December 2007. [4] L. Ragan, A. Hassibi, T. S. Rappaport, and C. Christianson, “Novel On-Chip Antenna Structures and Frequency Selective Surface (FSS) Approaches for Millimeter Wave Devices,” IEEE Vehicular Technology Conference 2007, pp. 2051–2055, 30 2007-Oct. 3 2007. [5] C. L. Park and T. S. Rappaport, “Short-Range Wireless Communications for Next-Generation Networks: UWB, 60 GHz Millimeter-Wave WPAN, And ZigBee,” IEEE Wireless Commun., vol. 14, no. 4, pp. 70–78, August 2007. [6] R. Daniels and R. Heath, “60 GHz wireless communications: emerging requirements and design recommendations,” IEEE Veh. Technol. Mag., vol. 2, no. 3, pp. 41–50, Sept. 2007.

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[34] J. Volakis, Antenna Engineering Handbook, 4th ed. McGraw Hill, 2007. [35] C. A. Balanis, Antenna Theory: Analysis and Design, 3rd ed. Wiley, 2005. [36] J. D. Kraus, Antennas, 1st ed. Mcgraw-Hill Electrical and Electronic Engineering Series, 1950. [37] T. S. Rappaport, Wireless Communications: Principles and Practice, 2nd ed. Prentice Hall, 2002. [38] R. N. Simons, “Novel On-Wafer Radiation Pattern Measurement Technique for MEMS Actuator Based Reconfigurable Patch Antennas,” NASA STI/Recon Technical Report N, vol. 2, Oct. 2002. [39] J. Akkermans, R. van Dijk, and M. Herben, “Millimeter-wave antenna measurement,” European Microwave Conference, 2007, pp. 83–86, Oct. 2007.

Felix Gutierrez, Jr. (S’ 08) received the B.S.E.E. degree from the University of Texas at Austin in 2006 and the M.S. degree in electrical engineering from Texas A&M University in 2008. He is currently pursuing a Ph.D. degree at the University of Texas at Austin. Mr. Gutierrez is a Baumberger Endowment scholar, Radio Club of America scholar, Graduate Diversity fellow, and a Cockrell School of Engineering fellow. Mr. Gutierrez is one of five individuals awarded the 2009 Marconi Young Scholar award by the Marconi Society. Mr. Gutierrez is a member of the Wireless Networking and Communications Group (WNCG) and has conducted undergraduate and graduate research in the area of wireless communications. His research interests include antenna design, radio frequency integrated circuits, communication systems, and an array of other areas his curiosity desires.

Shatam Agarwal received the B. Tech degree in electrical engineering from Indian Institute of Technology Kanpur, in 2004. He is currently working towards his M.S. degree in electrical and computer engineering at the University of Texas at Austin. His research interests include Analog/RF IC design and millimeter-wave circuit design.

Kristen Parrish (S’ 07) received the B.S. degree in Electrical Engineering (magna cum laude) from Rose-Hulman Institute of Technology (Terre Haute, IN) in 2008. She is currently working toward the M.S. degree at the University of Texas at Austin, where she is supported in part by a fellowship from the Cockrell School of Engineering. Ms. Parrish has held summer intern positions at Raytheon Technical Services Company (Indianapolis, IN) and LGS Innovations (Florham Park, NJ). She is currently completing an internship at Texas Instruments (Dallas, TX). Her research interests include RFIC and packaging design, electromagnetic theory and simulation, and communication systems.

Theodore S. Rappaport is the William and Bettye Nowlin Chair in Engineering at the University of Texas at Austin and is the founding director of the Wireless Networking and Communications Group (WNCG) at the university’s Austin campus, a center he founded in 2002. Prior to joining UT Austin, he was on the electrical and computer engineering faculty of Virginia Tech where he founded one of the world’s first university research and teaching centers dedicated to the wireless communications field. Prof. Rappaport has been a pioneer in the fields of radio wave propagation and wireless communication system design, and his work has influenced many international wireless standard bodies. He is one of the world’s most highly cited authors in the wireless field, having authored or co-authored over 200 technical papers, 100 US and international patents, and several books. In 2006, Rappaport was elected to serve on the Board of Governors of the IEEE Communications Society (ComSoc), and was elected to the Board of Governors of the IEEE Vehicular Technology Society (VTS) in 2008. In 1999, his pioneering work on site-specific RF propagation and system design received the IEEE Communications Society Stephen O. Rice Prize Paper Award. In 1989, he founded TSR Technologies, Inc., a cellular radio/PCS software radio manufacturer that he sold in 1993 to what is now CommScope, Inc (NYSE: CTV). In 1995, he founded Wireless Valley Communications Inc., a site-specific wireless network design and management firm that he sold in 2005 to Motorola, Inc. (NYSE: MOT). Rappaport has testified before the US Congress, has served as an international consultant for the ITU, has consulted for over 30 major telecommunications firms, and works on many national committees pertaining to communications research and technology policy. He is a highly sought-after consultant and technical expert. When he is not working or teaching, he enjoys singing, marathon training, amateur radio (N9NB), and traveling. He received B.S., M.S., and Ph.D. degrees in electrical engineering from Purdue University in 1982, 1984, and 1987, respectively.