IEEE 3D System Integration Conference 2016 Technical Program November 9-11, 2016, San Francisco, California, USA
Wednesday, November 9th 07:30 – 08:30 Breakfast 08:30 – 09:30 Keynote: John Shalf – Lawrence Berkeley Labs
Metropolitan II
Title: Exascale Computing 09:30 – 10:30 Session I 3DIC Processes I:
Session Chair – Chuan Seng Tan, NTU
Metropolitan II (20 minute papers) •
Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bes, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June rebibis, Andy Miller,“Die to Wafer 3D stacking for below 10um pitch microbumps”, IMEC, Belgium . (presented by Anne Jourdain).
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Takafumi Fukushima, “New Concept of TSV Formation Methodology Using Directed SelfAssembly”, Tohoku University, Japan
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Cesar Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Geert Van der Plas , Gerald Beyer, Eric Beyne, Joeri De Vos, “High-Density and Low-Leakage Novel Embedded 3D MIM capacitor on Si Interposer”, IMEC, Belgium
10:30 – 11:00 Break
Metropolitan Foyer
11:00 – 12:20 Session II Design and Applications: Session Chair – Prof. T. Tanaka, Tohoku Univesrity Metropolitan II (20 minute papers) •
Kentaro Akiyama, “A Front-illuminated Stacked Global-Shutter CMOS Image Sensor with Multiple Chip-on-Chip Integration”, Sony Semiconductor Solutions Corporation, Japan
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Hantao Huang, Leibin Ni, Hao Yu,“A 3D Multi-layer CMOS-RRAM Accelerator for L2-Norm based Learning on Neural Network”, Nanyang Technological University, Singapore. Presented by Yuhao Wang.
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Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, Rhett Davis, Paul Franzon,“Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor”, Intel Corporation, USA, North Carolina State University, USA, NVIDIA Corporation, USA
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Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Pascal Vivet, Alexis Farcy, Alexandre Arriordaz, Jean Michailos, Severine Cheramy, “ITAC: a complete 3D integration test platform”, CEA-LETI, France, MINATEC, France, ST Microlectronics, France, Mentor Graphics, France
12:20 – 13:30 Lunch
Metropolitan III
13:30 – 15:10 Session III Thermal Analysis : Session Chair – Rhett Davis, NC State
Metropolitan II
(20 minute papers) •
Cristiano Santos, Pascal Vivet, Sebastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, Lee Wang, “Thermal Performance of CoolCube™ Monolithic and TSV-based 3D Integration Processes”, CEA-LETI, France, MINATEC, France, ST Microlectronics, France, Mentor Graphics, USA
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Michael Scheuermann, “Thermal Analysis of Multi-Layer Functional 3D Logic Stacks”, IBM, USA
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Rafael Prieto Herrera, Perceval Coudrain, Jean-Philippe Colonna, Christian Chancel, Giovanni Romano, Severine Cheramy, Alexis Farcy, “Heat Spreading Packaging Solutions for Hybrid Bonded 3D-ICs”, Université de Grenoble & STMicroelectronics, France, CEA-LETI, France
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Kumail Khurram, Asisa Kumar Panigrahi, Satish Bonam, ShivGovind Singh, “Novel Inter Layer Dielectric and Thermal TSV material for enhanced heat mitigation in 3D IC”, Indian Institute of Technology, Hyderabad, India, Department of Electronics & Information Technology (DeitY), Govt. of India, India
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Yang Zhang, Xuchen Zhang, William Wahby, and Muhannad S Bakir “Design Considerations for 2.5-D and 3-D Integration Accounting for Thermal Constraints ” , Georgia Institute of Technology, USA
15:10 – 15:40 Break
Metropolitan Foyer
15:40 – 16:40 Session IV 3DIC Processes II: Session Chair - Prof. Mitsu Koyanagi, Tohoku Univ. (20 minute papers) •
Montserrat Fernández-Bolaños, Wolfgang Vitale, Mihai Adrian, Amin Enayati, Ilja Ocket, Walter Raedt, Armin Klumpp; Reinhard Merkel, Josef Weber, Peter Ramm, “3D TSV Based High Frequency Components for RF IC and RF MEMS Applications”, Ecole Polytechnique Federale de Lausanne, Switzerland, E&C Anechoic Chambers NV, IMEC & ESAT-TELEMIC, KU Leuven, Belgium, IMEC, Belgium, Fraunhofer EMFT, Germany,
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Anne Jourdain, “Extreme wafer thinning optimization for via last applications”, IMEC Belgium and SPTS, UK
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Severine Cheramy, Amandine Jouve, Lucile Arnaud, Claire Fenouillet, Perrine Batude, Maud Vinet , CEA-Leti, CEA, France, France, CEA, LETI, MINATEC Campus, France
16:40 – 18:00 Panel Session - “Fill and Drill” What is next in 3DIC? Organizer: Phil Garrou – MCNC Moderator: Bob Patti, Nhanced Semi Panelists: Mitsu Koyanagi, Tohoku University; Subu Iyer, UCLA; Joeri Di Vos, IMEC; Dev Guptya, APSTL 18:00 – 20:00 Reception
Thursday, November 10th 07:00 – 08:00 Breakfast 08:40 – 10:00 Session I 3DIC Processes III:
Session Chai - Nagesh Vodrahalli, All-via
Metropolitan II (20 minute papers) •
Suraj Singh, Asisa Kumar Panigrahi, ShivGovind Singh, “Analysis of Graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC Technology”, Indian Institute of Technology Hyderabad, India, Department of Electronics & Information Technology (DeitY), Govt. of India
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Asisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna, ShivGovind Singh, “Low Temperature CMOS Compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC Integration”, Indian Institute of Technology Hyderabad, India
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Murugesan Mariappan, “Improving the Integrity of Ti Barrier/Adhesion Layer for Via-Last TSV integration”, Tohoku University & GINTI, Japan
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Suraj Patil, Asisa Kumar Panigrahi, Satish Bonam, C. Hemanth Kumar, ShivGovind Singh , “Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration”, Indian Institute of Technology Hyderabad, India, Department of Electronics & Information Technology (DeitY), Govt. of India
10:00 – 10:30 Break
Metropolitan Foyer
10:30 – 12:30 Session II Design and Applications II: Session Chair –Dr. Pascal Vivet, CEA-LETI Metropolitan II
(20 minute papers) •
Gérald Cibrario; Ben Salem Nour, “From 2D to Monolithic 3D Predictive Design Platform: An Innovative Migration Methodology for Benchmark Purpose”, CEA, LETI, MINATEC Campus, France, ST Microelectronics, France
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Ryusuke Egawa, “A Power-Aware LLC Control Mechanism for 3D-Stacked Memory Subsystems”, Tohoku University Japan, Japan,
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Keith Felton, “Silicon-Package Co-Verification for 2.5D/3D Applications”, Mentor Graphics Inc, USA
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Gilad Yahalom; Stacy Ho; Alice Wang; Uming Ko; Anantha Chandrakasan, “Analog-Digital Partitioning and Coupling in 3D-IC for RF Applications”, Massachusetts Institute of Technology, USA, MediaTek, USA ,
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Makoto Motoyoshi; Kohki Yanagimura; Taikoh Fishimi; Junichi Takanohashi; Murugesan Mariappan; Masahiro Aoyagi; Mitsumasa Koyanagi, “3 Dimensional Stacked Pixel Detector and Sensor Technology Using less than 3-μmφ Robust Bump Junctions”, Tohoku-MicroTec Co., Ltd, Japan, Tohoku University & GINTI, Japan, Tohoku University, Japan
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Andy Heinig, “Interposer Based Integration to Achieve High Speed Interfaces for ADC application”, Fraunhofer IIS/EAS, Germany
12:00 – 13:00 Lunch and TPC Meeting
Metropolitan III
13:00 – 14:30 Special Session: Dielet Processing Organizer: Paul Franzon, NCSU Moderator: Dan Radack Presenters: Chris Bowers Subramania Iyer Mitsu Koyanagi Pascal Vivet
X-Celiprint UCLA GINTI, Tohuku University CEA LETI
14:30 – 14:50 Break
14:50 – 16:05 Session III Bonding:
Metropolitan Foyer
Session Chair – Dr. Dev Gupta, APSTL
Metropolitan II
(15 minute papers) •
Joeri De Vos, Lan Peng, Alain Phommahaxay, Andy Miller, Eric Beyne, Florian Kur, Thomas Wagenleiter, Markus Wimplinger, Thomas Uhrmann, “Importance of alignment control during permanent bonding and its impact on via- last alignment for high density 3D interconnects”, IMEC, Belgium
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Seniz E Kucuk Eroglu, Cho Woo-Yeong, Yusuf Leblebici, “Copper TSV-Based Die-Level ViaLast 3D Integration Process with Parylene-C Adhesive Bonding Technique”, EPFL, Switzerland, Samsung, Korea
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Kangwook Lee, “Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5D/3D integration applications”, Tohoku University, Japan
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Hao-Wen Liang, Hsiu-Chi Chen, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen, “The Influence of Device Morphology on Wafer-Level Bonding with Polymer-Coated Layer”, National Chiao Tung University, Taiwan, Kingyoup Optronics Co., Ltd, Taiwan
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Yu-Tao Yang, Yu-Chen Hu, Kuan-Neng Chen,“ Reliability Investigation and Mechanism Analysis for a Novel Bonding Method of Flexible Substrate in 3D Integration”, National Chiao Tung University, Taiwan
16:05 – 18:20 Session IV Reliability and Stress: Session Chair – Dr. Masahiro Aoyagi, AIST (15 minute papers)
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Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Gerald Beyer, Eric Beyne, Mohand Brouri, “Continuity and Reliability Assessment of a scalable 3x50µm and 2x40µm Via-middle TSV Module”, IMEC, Belgium
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Hideki Kitada, “Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis”, Fujitsu Limited, Japan
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Luke England, Rahul Agarwal, Sukeshwar Sukeshwar, Daniel Smith, “Impact of TSV Integration on 14nm FinFET Device Performance”, GlobalFoundries, USA
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Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka, “Drastic Reduction of Keep-Out-Zone in 3DIC by Local Stress Suppression with Negative-CTE Filler”, Tohoku University, Japan
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Ephraim Suhir, Sung Yi “Predicted Thermal Stresses in a TSV Design”, Portland State University, USA
19:00 – 21:00 Banquet
Friday, November 11th 07:30 – 08:30 Breakfast 08:30 – 09:50 Session I Power and Signal Integrity:
Session Chair – Nagesh Vodrahalli, All-via
Metropolitan II (20 minute papers) •
Makoto Suwada, “Considerations of TSV effects on next-generation super-high-speed transmission and Power Integrity design for 300A-class 2.5D and 3D package integration”, FUJITSU, Japan
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Subin Kim, Youngwoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim, “Design and Analysis of On-interposer Active Power Distribution Network for an Efficient Simultaneous Switching Noise Suppression in 2.5D IC”, Korea Advanced Institute of Science and Technology, Korea
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Ye Lin, Chuan Seng Tan, “Through Silicon Via (TSV) with Embedded Capacitor as On-chip Energy Storage Element”, Nanyang Technological University, Singapore
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C. Hemanth Kumar, Asisa Kumar Panigrahi, Om Krishan Sing, ShivGovind Singh, “Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC”, Indian Institute of Technology Hyderabad, India
09:50 – 10:20 Break
Metropolitan Foyer
10:20 – 11:40 Session II 3DIC Design and CAD: Session Chair – Herb Richter Metropolitan II
(20 minute sessions)
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Guillaume Berhault, François Galea, Lilia Zaourar, Melanie Brocard, Sebastien Thuries, “3DIP: An Iterative Partitioning Tool For Monolithic 3D IC”, CEA-LETI, France
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Rosa R Lahiji; Timothy Lee; Warren Snapp, “3D integration and Challenges for Advanced RF and Microwave Systems: EDA Perspective”, The Boeing Company, USA
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Fang Qiao; Ilgweon Kang; Daniel Kane; Chung-Kuan Cheng, “3D Floorplan Representations: Corner Links and Partial Ordering”, University of California, San Diego, USA
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William Wahby, Thomas Sarvey, Hardik Sharma, Hadi Esmaeilzadeh, and Muhannad S. Bakir, “The Impact of 3D Stacking on GPU-Accelerated Deep Neural Networks: an Experimental Study”, Ga. Tech, Atlanta, USA
11:40 – 12:40 Session III 3DIC Processes: Session Chair – Prof. Takafumi Fukushima, Tohoku University Metropolitan II (20 minute sessions) •
Brian Mattis, “Frontside mid-level TSV integration for high-density 3D applications”, Novati Technologies, USA
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Naoya Watanabe, Hidekazu Kikuchi, Azusa Yanagisawa, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Akio Nakamura, “Wet Cleaning Process for High-Yield Via-Last TSV Formation”, National Institute of Advanced Industrial Science and Technology, Japan, LAPIS Semiconductor Co., Ltd., Japan, AIST, Japan
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Reynard Blasa, “High Density Backside Tungsten TSV for 3D Stacked ICs”, Novati Technologies, USA
12:40 – 13:40 Lunch
Metropolitan III
13:40 – 17:00 Tutorials “3DIC Technology and Design,” Paul Franzon, NCSU “Building an EcoSystem for Multi-die ICs, As Foundation for “System Scaling”, Herb Richter, EDA2ASIC Consulting 14.10 – 14.30 Break
