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Student, Perfect Student ID: 9999 Exam ID: 10656 Final Exam CS-343/Vickery December 16, 2004 Page 1 of 7 NOTE: It is my policy to give a failing gr...
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Student, Perfect Student ID: 9999 Exam ID: 10656

Final Exam CS-343/Vickery

December 16, 2004 Page 1 of 7

NOTE: It is my policy to give a failing grade in the course to any student who either gives or receives aid on any exam or quiz. INSTRUCTIONS: Mark the best answer for each question on your answer sheet. All questions count equally; the number of points given is a relative weight, not an absolute number. 1. A. B. C. D. E.

(5 Points) A non-pipelined processor has a 250 MHz clock. If the processor is redesigned to use a perfectly balanced pipeline with depth 6, what would be the clock speed of the new processor? Approximately 400 MHz. Approximately 1.00 GHz Approximately 1.25 GHz Approximately 1.50 GHz Approximately 1.75 GHz

A. B. C. D. E.

(5 Points) Continuing from the previous question, what would be the expected speedup due to pipelining? 4.0 5.0 6.0 7.0 8.0

A. B. C. D. E.

(5 Points) What would be the expected speedup expressed as a percentage? 300% 400% 500% 600% 700%

A. B. C. D. E.

(5 Points) What will be the relationship of the CPI without pipelining to the CPI with pipelining? (Don’t ask me what CPI stands for; that’s what I’m testing!) No change The pipleined CPI will be 6 times the unpipelined CPI. The unpipelined CPI will be 6 times the pipelined CPI. It depends on the hit ratio. It depends on the miss ratio.

A. B. C. D. E.

(5 Points) What will happen to the instruction latency as a result of introducing the pipeline? The latency will remain unchanged. The latency will decrease from 6 cycles to one cycle as a result of using the pipeline. The latency will increase from one cycle to 6 cycles as a result of using the pipeline. The latency will depend on the opcode of the instruction. The latency will depend on the throughput.

A. B. C. D. E.

(5 Points) What will happen to the instruction throughput as a result of introducing the pipeline? The throughput will remain unchanged. The throughput will increase by a factor of 6 as a result of using the pipeline. The throughput will decrease by a factor of 6 as a result of using the pipeline. The throughput will depend on the number of instructions in the program. The throughput will depend on the latency.

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Final Exam CS-343/Vickery

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(5 Points) What is a data hazard? A. When there are not enough functional units to meet the demands of all the instructions in a pipeline. B. When an instruction in a pipeline is a branch and partially executed instructions following it in the pipeline aren’t supposed to be executed. C. When an instruction needs the result of a previous instruction, but the previous instruction is still in the pipeline and its result hasn’t been written back to the registers yet. D. When a pipeline result is invalid because of arithmetic overflow. E. When an arithmetic calculation produces a carry out of the leftmost position.

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(5 Points) What is a control hazard? A. When there are not enough functional units to meet the demands of all the instructions in a pipeline. B. When an instruction in a pipeline is a branch and partially executed instructions following it in the pipeline aren’t supposed to be executed. C. When an instruction needs the result of a previous instruction, but the previous instruction is still in the pipeline and its result hasn’t been written back to the registers yet. D. When two instructions try to read from the same register at the same time. E. When a single instruction tries to read from two different registers at the same time.

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(5 Points) What is a structural hazard? A. When there are not enough functional units to meet the demands of all the instructions in a pipeline. B. When an instruction in a pipeline is a branch and partially executed instructions following it in the pipeline aren’t supposed to be executed. C. When an instruction needs the result of a previous instruction, but the previous instruction is still in the pipeline and its result hasn’t been written back to the registers yet. D. When a program has illegally nested loops that the pipeline can’t handle. E. When the program has illegally nested loops that the compiler has to fix.

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(5 Points) What is a pipeline stall? A. When instructions are not allowed to move through the pipeline for one or more clock cycles due to a data or structural hazard. B. When instructions enter the pipeline too fast. C. When instructions exit the pipeline too fast. D. When the same instruction enters and exits the pipeline in a single clock cycle. E. When an instruction later in the pipeline causes an earlier instruction to produce the wrong answer.

11. A. B. C. D. E. 12.

(5 Points) What is the relationship between a pipeline bubble and a pipeline stall? A bubble is a stall that doesn’t cause a delay. A stall is a bubble that doesn’t cause a delay. A bubble can only occur if there is a control hazard. A stall can only occur if there is a control hazard. They are the same thing.

(5 Points) What is result forwarding? A. A mechanism for dealing with control hazards in which one branch instruction nullifies another branch instruction. B. A mechanism for dealing with structural hazards in which one branch instruction nullifies another branch instruction. C. A mechanism for dealing with data hazards by obtaining the result of a previous instruction from an internal buffer instead of waiting for it to be written back to a register. D. A mechanism for dealing with structural hazards in which an arithmetic instruction nullifies a branch instruction that has not yet left the pipeline. E. A mechanism for dealing with structural hazards in which an arithmetic instruction nullifies a branch instruction that has already left the pipeline.

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A. B. C. D. E.

(5 Points) What is the name for the technique in which both forks following a branch are executed in parallel, and the unused fork is discarded once the result of the branch condition has been determined? Delayed branch Speculative execution Twin forks Negative forks Positive forks

A. B. C. D. E.

(5 Points) How many pipeline registers are used in an n stage pipeline? 0 1 n–1 n n+1

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(5 Points) How many bits must each pipeline register hold? A. 32 B. Enough to control all the parts of the datapath in the next stage of the pipeline. C. Enough to control all the parts of the datapath in the next stage of the pipeline plus enough to control further stages in the pipeline, such as the destination register number. D. Enough to hold the result of the ALU operation in the previous stage of the pipeline. E. Enough to hold the opcode and register numbers of the instruction being executed.

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(5 Points) Most pipelined processors improve performance by adjusting the number of pipeline stages depending on the opcode of the instruction being executed. A. True B. False

17. A. B. C. D. E.

(5 Points) What is the number of pipeline stages in the MIPS processor design of Chapter 6? 0 1 5 20 50

A. B. C. D. E.

(5 Points) What is the approximate number of pipeline stages in Intel Pentium IV processors? 0 1 5 20 50

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(5 Points) Are you having fun yet? A. Yes, Dr. Vickery.

20. A. B. C. D. E.

(5 Points) What is the purpose of using a memory hierarchy? It is a way to manage the tradeoffs between memory capacity, cost per bit, and access time. It is a way to optimize memory capacity without regard to cost or access time. It is a way to optimize memory cost without regard to capacity or access time. It is a way to optimize memory access time without regard to cost or capacity. It is a way of extending the non-volatile nature of disks to main memory and the registers.

A. B. C. D. E.

(5 Points) What is the essential difference between SRAM and DRAM with regard to their roles in a memory hierarchy? SRAM has a larger capacity than DRAM with the same cost. DRAM is faster than SRAM with the same cost. SRAM is slower than DRAM with the same capacity DRAM is more expensive than SRAM with the same speed. SRAM is faster, smaller, and costs more per bit than DRAM.

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Final Exam CS-343/Vickery

A. B. C. D. E.

(5 Points) Which type of device would be most appropriate for a cache memory? SRAM DRAM Flash Disk Tape

A. B. C. D. E.

(5 Points) Why is disk so much slower than RAM? Because it is non-volatile (doesn’t lose information when turned off). Because of network delays. Because of bus delays. Because of mechanical delays. It’s not slower, it’s faster.

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For the following questions, assume a processor uses byte addressing, has a word size of 4 bytes, a virtual address space of 4GB bytes, and a physical address space of 1 GB. Help: All questions asking about cache refer to physical addresses, not virtual addresses. For all questions, the cache can hold 64K bytes, and each cache block can hold 16 bytes. Page size is 1024 words. 24. A. B. C. D. E.

(5 Points) How wide is a virtual address? 30 bits 32 bits 230 bits 232 bits 232 bytes

A. B. C. D. E.

(5 Points) How wide is a physical address? 30 bits 32 bits 230 bits 232 bits 230 bytes

A. B. C. D. E.

(5 Points) How many bits in the byte offset field of an address? (The answer is the same whether the address is physical or virtual.) 0 1 2 4 8

A. B. C. D. E.

(5 Points) How many cache blocks are there? 1K 2K 4K 8K 16K

A. B. C. D. E.

(5 Points) Assume the cache is 4-way set associative. How wide are the tag, cache index (set number), block-offset, and byte-offset fields, in that order from left to right? 16, 10, 2, 2 14, 12, 2, 2 12, 12, 4, 2 12, 12, 2, 4 8, 8, 8, 8

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(5 Points) Assume the cache is fully associative. How wide is the cache index field? 0 bits 10 bits 12 bits 14 bits 16 bits

A. B. C. D. E.

(5 Points) How many virtual pages are there? 10 210 20 220 232

A. B. C. D. E.

(5 Points) How many physical pages are there? 10 210 20 220 218

A. B. C. D. E.

(5 Points) How many entries are there in a page table? 10 210 20 220 18

A. B. C. D. E.

(5 Points) Under what conditions would a “valid” bit be false? When there was overflow. When there was an interrupt. When a page or block has not yet been loaded into this level of the hierarchy. Whenever there is a cache hit. When the network is down.

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(5 Points) Under what condition would a “dirty” bit be true? A. When a block or page has been modified but not written back to the next lower level of the hierarchy yet. B. When a block or page is causing a pipeline stall. C. When the TLB is empty. D. When the TLB is full. E. When there is no TLB available.

35. A. B. C. D. E. 36.

Final Exam CS-343/Vickery

(5 Points) What is a TLB? A mechanism for translating disk addresses into cache block numbers. A cache that holds part of a page table. A page table that holds part of a cache. A part of the kernel that is executed when there is an interrupt. The smallest amount of information that can be read from or written to a disk.

(5 Points) Which statement is true about a page table? A. All programs share a single page table. B. A page table is part of the CPU. C. The kernel is responsible for putting information in the page table and the CPU uses the information to translate virtual addresses to physical addresses. D. The CPU is responsible for putting information in the page table and the kernel uses the information to decide which process to schedule. E. The page table is managed completely by the CPU, but the kernel can store a copy on disk when there is a mistake.

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A. B. C. D. E.

(5 Points) If a hit takes one cycle to complete and the cache miss penalty is 100 clock cycles, what is the average number of clock cycles per memory access for a processor with a hit ratio of 0.9? (Pick the closest answer.) 100.9 10.90 1.900 9.100 9.010

A. B. C. D. E.

(5 Points) What is the advantage of an interleaved memory design? The processor doesn’t have to wait for the kernel to decide which page to load. The kernel doesn’t have to do a context switch when there is an interrupt. The bandwidth between the processor and memory is higher. The bandwidth between the memory and the disk is lower. Multiple banks of memory can be accessed in parallel, which is faster.

A. B. C. D. E.

(5 Points) What is the bandwidth of a bus? The sum of the number of address wires and the number of data wires. The number of address wires. The number of data wires. The number of data wires times the clock speed of the bus. The log base 2 of (the number of address wires plus the number of data wires).

A. B. C. D. E.

(5 Points) Which of the following statements is true? A sector is the same thing as a page. The sector size is always an integer multiple of the page size. The page size is always an integer multiple of the sector size. There is no relationship between the size of a page and the size of a sector. Sectors are parts of physical memory, but pages are in cache.

A. B. C. D. E.

(5 Points) What is the purpose of reference bits? They are used to tell whether a disk drive will have rotational delay or not. They are used to tell whether a page needs to be written back to disk or not. They are used to tell whether a cache block needs to be written back to RAM or not. They tell whether a page is in SRAM or DRAM. They are used in implementing Least Recently Used replacement algorithms.

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(5 Points) What is the difference between write back and write through? A. With write back, main memory is updated immediately, but with write through, the memory is updated only when the block is replaced. B. With write through, main memory is updated immediately, but with write back, the memory is updated only when the block is replaced. C. With write through, the block is replaced when it is written, but with write back, it is replaced when it is read. D. With write through, the block is replaced when it is read, but with write back, it is replaced when it is written. E. They are two names for the same thing.

43. A. B. C. D. E.

(5 Points) What is a split cache design? A design in which part of the cache resides in main memory. A design in which part of the page table resides on disk. A design with separate instruction and data caches. A design with separate caches for disk and main memory. A design with multiple cycles per cache access.

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(5 Points) A cache miss caused by the first access to a block that has never been in the cache is called: F. A compulsory or cold start miss. G. A capacity miss. H. A conflict or collision miss. I. A conflict of interest miss. J. A missed opportunity.

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A. B. C. D. E.

(5 Points) A cache miss that occurs in a set-associative or direct-mapped cache when multiple block compete for the same set and that are eliminated in a fully associative cache of the same size is called: A compulsory or cold start miss. A capacity miss. A conflict or collision miss. A conflict of interest miss. A missed opportunity.

A. B. C. D. E.

(5 Points) Which statement describes page faults most accurately? The kernel detects page faults, and signals the CPU so it can obtain the correct page from disk. The CPU detects page faults, and signals the kernel so it can obtain the correct page from disk. The disk detects page faults, and signals the kernel so it can obtain the correct page from the CPU. The disk detects page faults, and signals the CPU so it can obtain the correct page from the kernel. Page faults are ignored whenever performance is important.

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