Verilog Model for DLX Processor

DLX Data Path Architecture Verilog Model for DLX Processor • DLX processor is introduced in Patterson and Hennessy’s book “Computer Architecture - A ...
Author: Martina Russell
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DLX Data Path Architecture

Verilog Model for DLX Processor • DLX processor is introduced in Patterson and Hennessy’s book “Computer Architecture - A Quantitative Approach” Morgan Kaufmann Publisher, 1990.

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DLX Control Unit

Data Path Building Blocks • • • •

Latch Register register with one output port : A_reg, B_reg register with two output ports : temp_reg, IAR_reg • register with three output ports: MDR_reg, MAR_reg, PC_reg • register_file 3

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Data Path Building Blocks

Control Unit Building Blocks

• mux • memory_32 • ALU

• ROM : • • • • •

decode_1_ROM, decode_2_ROM, microcode_ROM source_decode destination_decode micro_addr_select register : micro_PC_reg mux : dest_mux

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Verilog Modules for Building Blocks module latch (data_out, data_in, clk); parameter word_width = 32; output data_out; input data_in, clk; reg [word_width - 1 : 0] contents; wire [word_width - 1 : 0] data_in, data_out; wire clk; initial contents = 0; assign data_out = contents ; always @(posedge clk) contents = data_in; endmodule

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Verilog Modules for Building Blocks

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module register (data_out, data_in, latch, clk ); parameter word_width = 32; output data_out; input data_in, latch, //control signal that causes the input to be latched clk; reg [word_width - 1 : 0] contents; wire [word_width - 1 : 0] data_in, data_out; wire latch, clk; initial contents = 0;

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Verilog Modules for Building Blocks

Verilog Modules for Building Blocks module register_1_port (data_out, data_in, latch, enable, clk); parameter word_width = 32; output data_out; input data_in, latch, //control signal to latch the input enable, // enable the data_out clk; wire [word_width - 1 : 0] data_in, data_out, reg_out;

assign data_out = contents; always @(posedge clk) if (latch) contents = data_in; endmodule

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Verilog Modules for Building Blocks

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Verilog Modules for Building Blocks

wire latch, enable, clk; register r (reg_out, data_in, latch, clk); assign data_out = (enable) ? reg_out : 32'bz ; endmodule

module register_2_port (data_out_1, data_out_2, data_in, latch, enable_1, enable_2, clk); parameter word_width = 32 ; output data_out_1, //first output port. data_out_2; //second output port. input data_in, latch, enable_1, enable_2, clk; wire [word_width - 1 : 0] data_in, data_out_1, data_out_2, reg_out; wire latch, enable_1, enable_2, clk; 11

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Verilog Modules for Building Blocks

Verilog Modules for Building Blocks

register r(reg_out, data_in, latch, clk); assign data_out_1 = (enable_1) ? reg_out : 32'bz, data_out_2 = (enable_2) ? reg_out : 32'bz; endmodule

module register_3_port (data_out_1, data_out_2, data_out_3, data_in, latch, enable_1, enable_2, clk); parameter word_width = 32; output data_out_1, data_out_2, data_out_3; input data_in, latch, enable_1, enable_2, clk; wire [word_width - 1 : 0 ] data_in, data_out_1, data_out_2, data_out_3, reg_out; wire latch, enable_1, enable_2, clk; 13

Verilog Modules for Building Blocks

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Verilog Modules for Building Blocks

register r (reg_out, data_in, latch, clk); assign data_out_1 = (enable_1) ? reg_out : 32'bz, data_out_2 = (enable_2) ? reg_out : 32'bz, data_out_3 = reg_out; endmodule

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module register_file (data_out_1, data_out_2, source_1, source_2, data_in, dest, latch, latch_last_reg, clk); parameter word_width = 32, file_addr_width = 5, reg_file_size = 32; output data_out_1, data_out_2; // first and second output port input source_1, //address for source register 1 source_2, //address for source register 2 data_in, //input to the register dest, //address for the dest. register 16

Verilog Modules for Building Blocks

Verilog Modules for Building Blocks

latch, //control signal to latch input in dest. reg. latch_last_reg, //cause input to be latched in the R[31]. clk; reg [word_width - 1 : 0 ] registers [reg_file_size - 1 : 0]; wire [word_width - 1 : 0 ] data_in, data_out_1, data_out_2; wire [file_addr_width - 1 : 0 ] source_1, source_2, dest; wire latch, latch_last_reg, clk; integer i; 17 initial

Verilog Modules for Building Blocks

begin for (i=0; i> s2 ) : 32'bz, 28

Verilog Modules for Building Blocks

Verilog Modules for Building Blocks

temp = (alu_op == 8) ? ((s1[word_width -1] == 0) ? (s1 >> s2 ) : ((s1 >> s2 ) | (~(32'b0)