Verilog HDL
In-Cheol Park Dept. of EE, KAIST
Introduction to Verilog HDL
Designed as a proprietary verification/simulation tool in 1983/1984 IEEE standard 1364 in 1995 Similar to C language 4 value logic (0, 1, x, z) HDL which provides a wide range of levels of abstraction
Architectural, Algorithmic, RTL, Gate, Switch
Mixed level modeling and simulation Interactive usage Gate Hierarchical specification Switch 2
Behavioral Behavioral
Verilog Spans a Wide Range of Modeling Levels
Increasing level of abstraction
Architectural
always #($dis_poisson(seed,32)) begin if $q_full(qid) $q_remove(qid,job,job_id,status); else fill_queue; end
Algorithmic
RTL
always @(fetch_done) begin casez(IR[7:6]) 2’b00: LDA(acc,IR[5:0]); 2’b01: STR)acc,IR[5:0]); 2’b10: JMP(IR[5:0]); 2’b11: ; // NOP endcase end
Gate
Switch
assign rt1=(11 & buserr) | zero; assign sub=rt1 ^| op; assign out1=i1 & i2 | op;
behavioral (non-structural) gate/switch (structural) 3
Module & Hierarchy Example(1/4) module board(); wire [3:0] count; wire clock,f,af; m16 counter(count, clock, f, af); m555 clockGen(clock); always @(posedge clock) $display($time,,”count=%d, f=%d,af=%d”, count, f, af); endmodule board value
fifteen altFifteen
clock m16
m555 d
c
b
4
a
Module & Hierarchy Example(2/4) // m16: 16-bit counter module m16 output input output ); dEdgeFF
( wire wire wire
[3:0]
a(value[0], b(value[1], c(value[2], d(value[3],
value, clock, fifteen, altFifteen
clock, clock, clock, clock,
~value[0]), value[1]^value[0]), value[2]^&value[1:0]), value[3]^&value[2:0]);
assign fifteen = value[0] & value[1] & value[2] & value[3]; assign altFifteen = &value; endmodule
5
Module & Hierarchy Example(3/4) // dEdgeFF: D flip-flop
// m555: clock generator
module dEdgeFF ( output reg input wire );
module m555 ( output reg );
q, clock, data
clock
initial #5 clock = 1;
always@(negedge clock) #10 q = data;
always #50 clock = ~clock;
endmodule
endmodule
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Module & Hierarchy Example(4/4) // m16Behav: behavioral model of m16 module m16Behav( output reg [3:0] value, input wire clock, output reg fifteen,altFifteen ); initial value = 0;
always @(negedge clock) begin #10 value = value+1; if (value == 15) begin altFifteen = 1; fifteen = 1; end else begin altFifteen = 0; fifteen = 0; end end endmodule
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Module Definition
Modules definition
All module start with the keyword module followed by
module name the list of inputs and outputs and end with the keyword endmodule
All the inputs and outputs are defaulted to wire // module definition module module_name ( input in1, input in2, output out, ... ); endmodule 8
Description Styles
Structural Style
Verilog logic primitives
Built into the language and have pre-defined functions and is an instance of an AND gate as well as or, nand, nor, not and others // structural module AND2 ( input in1, input in2, output out ); and u1 (out, in1, in2); endmodule
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Description Styles
Data flow Style
Modeling only combinational functions Whenever any of the inputs changes, the output is recalculated and updated Continuous assignment statement assign // data flow module AND2 ( input in1, input in2, output out ); assign out = in1 & in2; endmodule
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Description Styles
Behavioral Style
Behavioral instance: always
The expression @(in1, in2) instruct the simulator to wait until either in1 or in2 has changed
Provides high-level language
Some of the modules may be unrealizable in hardware // behavioral module AND2 ( input wire in1, input wire in2, output reg out ); always @(in1, in2) out = in1 & in2; endmodule 11
Testing the Module
The module test_and2 has an instance of the module under test AND2 initial block construct is similar to the always construct, and both can have behavioral statement inside them $display statement display the value of variables
module test_and2; reg i1, i2; wire o; AND2 u2(i1, i2, o); initial begin i1 = 0; i2 = 0; #1 $display(“i1 = %b, i2 = %b, o = %b”, i1, i2, o); i1 = 0; i2 = 1; #1 $display(“i1 = %b, i2 = %b, o = %b”, i1, i2, o); end endmodule
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Hierarchical Specification
Hierarchical Specification
Basic unit is the module All description of structural and non-structural functionality must appear within modules Modules communicates with outside world through ports
input port output port inout port
Port signals can be used in gates, switches, and procedural blocks
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Hierarchical Specification
Module instance: a copy of a module
Each instance is a complete, independent, concurrently active copy of a module
Supports hierarchical structural descriptions Module parameters can be assigned on an instance by instance basis Every level of hierarchy has its own scope
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Port Connection
positional port connection
missing port connection
named port connection
skip with comma unconnected input ports are ‘z’ unconnected output ports are simply unused
e.g. my_gate g1(.o(out), .i1(in1), .i2(in2));
connection size difference
unsigned right justification or truncation unsized expression is machine’s integer size
usually 32 bits e.g. 12, `b101 16
Port Connection Rules
A module input port must be a net data type. The connection to a module output must be a net data type at the higher level. A module inout port must be a net both inside the module and outside the module. A gate output must be a net data type. The left hand side of a continuous assignment must be a net data type. The left hand side of a procedural assignment must be a reg data type.
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New Features in Verilog 2001 Port definition can be included in the module declaration
module Mux4(in0, in1, in2, in3, out, sel);
module Mux4(
input wire in0, in1, in2, in3;
input wire in0,in1,in2,in3,
output reg out;
output reg out,
input wire [1:0] sel;
input wire [1:0] sel);
always @ (in0 or in1 or in2 or in3 or sel)
always @ *
case(sel) in0 in1 in2 in3
case(sel) 2’d0: out = = = != = = = != = & ^ ^~ | && || ? : (ternary operator)
highest precedence
lowest precedence
Bit length
unsized constant number sized constant number i op j where op is: +-*/%& | ^ ^~ +i and -i ~i i op j where op is === != = = = != && || > >= > j i
