Using the Xilinx picoblaze NOR Flash Programmer for Zefant FPGA Modules
Autoren:
Stephan Schirrmann Karlheinz Woschée
Dokument-Nr.
20080514-101
Dateiname:
pico-flashprog_zefant_instructions.doc
Version:
V0.2
Erstellt:
03.05.2007 05:58:00
Zuletzt gespeichert:
01.06.2008 14:22:00
© 2008 Simple Solutions, Stephan Schirrmann. All rights reserved. All trademarks, registered trademarks, patents, and disclaimers are the property of their respective owners. All specifications are subject to change without notice.
pico-flashprog_zefant_instructions.doc Contents
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1 Contents 1 2 3
Contents ...................................................................................................................2 Introduction...............................................................................................................3 Instructions for Users................................................................................................3 3.1 General Usage of the Flash Programmer..........................................................3 3.1.1 Prerequisites ..............................................................................................3 3.1.2 Hardware setup..........................................................................................4 3.1.3 Starting the Flash Programmer ..................................................................6 3.1.4 Controlling the Flash Programmer .............................................................6 3.1.5 Additional Notes about Flash Memories.....................................................8 3.2 Flashing FPGA configuration files – Generate a MCS file.................................9 3.3 Initializing the FPGA from flash .......................................................................10 3.3.1 Zefant-XS3 ...............................................................................................10 3.3.2 Zefant-LC3E.............................................................................................11 4 Instructions for Programmers .................................................................................11 4.1 Required Tools ................................................................................................12 4.2 Steps to generate the Flash Programmer .......................................................12 5 Version History .......................................................................................................12
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pico-flashprog_zefant_instructions.doc Introduction
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2 Introduction Xilinx published a picoBlaze based „PicoBlaze RS-232 StrataFlash Programmer” for their Spartan-3E 1600E MicroBlaze Development Board, written by Ken Chapman. The original project is available here: http://www.xilinx.com/products/boards/s3e1600e/reference_designs.htm http://www.xilinx.com/products/boards/s3e1600e/PicoBlaze_NOR_FLASH_programmer_1600E_rev1.pdf http://www.xilinx.com/products/boards/s3e1600e/SP3E1600E_picoblaze_nor_flash_prog.zip
With very little changes this code can also be used to program the onboard flash memory of the Zefant FPGA modules. Very much like our original Microblaze based “Serial Flash Programmer” it is a configuration of the FPGA which is controlled by a PC running a terminal program and connected to the hardware over RS232. The adapted code for all Zefant modules is available here: https://gforge.simple-solutions.de/projects/pico-flashprog/
Please note that you can use different I/O pins for RS232 RX/TX if you follow the instructions below.
3 Instructions for Users 3.1
General Usage of the Flash Programmer
3.1.1 Prerequisites To reproduce the shown steps, you will need the following: • • • • • • •
Zefant FPGA module Zefant TopDown Baseboard or RS232 level shifter or USB-RS232 adapter Power supply JTAG download cable Xilinx ISE toolchain (of which only iMPACT us needed here) Terminal program Serial connection between PC and FPGA module
For use as terminal program on Windows TeraTerm is recommended, which is less annoying than HyperTerminal: Original version: http://hp.vector.co.jp/authors/VA002416/teraterm.html Improved Version 3.1.3: http://www.ayera.com/teraterm/
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3.1.2 Hardware setup 3.1.2.1 Zefant-XS3
Fig 3-1: Zefant-XS3
3.1.2.2 Zefant-LC3E The Zefant-LC3E does not contain a RS232 transceiver, so it has to be added externally. You can do that yourself on your baseboard or discretely, or you can order our USB-RS232-Adapter which is shown on the picture. You get a virtual RS232 port over USB then.
Fig 3-2: Zefant-LC3E (please note, that the JTAG cable is not connected on this picture)
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The following pins are used for RS232 RX/TX by default: LC3 Pin X801 / Pin 32 X801 / Pin 31
FPGA Pin P116 P117
Signal name RS232_RXD RS232_TXD
Note Data from FPGA to PC Data from PC to FPGA
Don’t forget to connect a GND also, which is available on Pin 40 of all BTB connectors. If you want to use different I/Os for RX/TX, change these lines in the LC3E pin constraints file (flash_programmer_lc3e_fpga.ucf) accordingly: NET "RS232_TXD" LOC = "P117" NET "RS232_RXD" LOC = "P116"
| IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4; # DTE TX | IOSTANDARD = LVTTL; # DTE RX
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3.1.3 Starting the Flash Programmer The Bitfiles for all supported modules are located in the /Bitfiles directory of the project. If you downloaded the Source distribution, you can generate all Bitfiles by executing the /Sources/common_FPGA/generate_bitfiles.cmd batch file. For the Zefant LC3E-250 for example the correct bitfile will be /Bitfiles/lc3e_fpga/FPGA/ flash_programmer_lc3e_fpga_250e.bit Download this file to the FPGA over JTAG with Impact like you’d do with any other FPGA bitfile. 3.1.4 Controlling the Flash Programmer The flash programmer is controlled over the serial port. The serial parameters are 115200/8/n/1, Flow control is Xon/Xoff:
Fig 3-3: Serial Port Setup
Don’t forget to select the correct serial port. If you are using the RS232-USB-Adapter, you can select the desired port in the system control panel. 3.1.4.1 Flash Programmer Commands This chapter has been copied from the original Picoblaze Flash Programmer documentation, Ken Chapman, pages 9-13 (see chapter 2 Introduction). • •
•
H - Help command displays the simple menu again. I - Read Identification code of the Intel flash memory. This command is a good way to confirm communication with the NOR flash is working. The response is for example 89 18 where ’89’ is the Device Manufacturer Code (Intel) and ’18’ is the Memory ID code for the 128Mbit size device (please see flash data sheet for more details). S – Read the status register of the Intel flash memory. The 8-bit status register is used during programming and erase operations. The MSB (bit7) indicated when the memory is ready (1) or busy (0). The lower bits all indicate errors of some kind and therefore the only desirable response ’80’ hex. This design performs no
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pico-flashprog_zefant_instructions.doc Instructions for Users
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error checking or clearing but you could add these functions if required (please see flash data sheet for more details). E – Erase command will erase ALL of the 128Mbit memory. Note that the device will be completely erased using this command and hence you will be asked to confirm the operation with an upper case ‘Y’. The 128Mbit device is organised into 128 blocks each of 128K-bytes. Each block could take up to 4 seconds to erase although typically it takes only 1 second. Therefore at best this command will take the best part of 2 minutes to complete and at worst could take over 8 minutes (please see Intel data sheet for more details). B – Erase Blocks command will erase blocks 0 to 2 only. This covers the address range 000000 to 05FFFF. This command is faster that the ‘E’ command and will leave the upper memory unchanged. You will be asked to confirm the operation with an upper case ‘Y’. The erase blocks command can take up to 12 seconds per sector (4 seconds per block). Typically this command will take 3 seconds to complete. P - This is the most important command as it will allow you to program the flash device with a configuration bit stream suitable for your FPGA to load from at power up, pressing the PROG button or using multi-boot techniques. In chapter 3.2 we will consider how to prepare an MCS. After you have entered the ‘P’ command you have to send a text file with your terminal program (e.g. .mcs file). Programming will take up a few minutes, depending on size. The programming will complete with ‘OK’ and a return to the > prompt. R – The read command allows you to observe 256 consecutive bytes stored in the flash memory. After entering the ‘R’ command you will be prompted to enter a start address. You should then enter a 6 digit hexadecimal value 000000 to FFFFFF. Entering an illegal hex character will result in the ‘address=‘ prompt being repeated. W - The write byte command allows you to write a single byte at any address. After entering the ‘W’ command you will be prompted to enter an address. You should then enter a 6 digit hexadecimal value 000000 to FFFFFF. Entering an illegal hex character will result in the ‘address=‘ prompt being repeated. You will then be prompted to enter the data value and you should enter a 2 digit hexadecimal value 00 to FF. Entering an illegal hex character will result in the ‘data=‘ prompt being repeated.
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3.1.5 Additional Notes about Flash Memories It’s important to know 2 things: 1) When a flash memory is empty it contains all FFs, not zeroes. During programming, only set bits can be reset, so only FFs can be overwritten. So it’s required to erase the flash memory before programming, which set’s all bits to ‘1’ in the erased block. 2) Flash memories are organized in blocks. Programming can be performed bytewise, but erasing is only possible block-wise. The “StrataFlash J3” chip used on the Zefant module is organized in 128kByte blocks, so you always have to erase 128kBytes at a time:
Fig 3-4: Blocks in flash memory
The various Zefant modules contain the following flash chips: FPGA Module
Flash chip
ZLC3E-100 ZLC3E-250 ZXS3-0400 ZXS3-1000 ZXS3-1500 ZXS3-2000 ZNANO-0400 ZNANO-1200
28F320J3 28F320J3 28F320J3 28F320J3 28F128J3 28F128J3 28F128J3 28F128J3
Flash capacity 32Mbit / 4MByte 32Mbit / 4MByte 32Mbit / 4MByte 32Mbit / 4MByte 128Mbit / 16MByte 128Mbit / 16MByte 128Mbit / 16MByte 128Mbit / 16MByte
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Number of blocks 32 32 32 32 128 128 128 128
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pico-flashprog_zefant_instructions.doc Instructions for Users
3.2
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Flashing FPGA configuration files – Generate a MCS file
You have to generate a MCS file from your FPGA Bitstream if you want to initialize your FPGA from the flash mermory. Generating a MCS file is explained in a few steps. This chapter has been copied from the original Picoblaze Flash Programmer documentation, Ken Chapman, pages 14-18 (see chapter 2 Introduction). 1. Select ‘Generate PROM’ in Project Manger. 2. This launches iMPACT in which you need to select the PROM File Formatter mode. (You probably need to expand the upper left window as shown here or pan down to see it). 3. Select ‘Generic parallel PROM’ ‘MCS’ file format and provide a file name and location. Then click two times on ‘Next’. 4. Select the density from the drop down list (A 128Mbit device equates to 16Mbytes and then click ‘Add’ so that it appears in the centre box (see Fig 3-5). That’s all, click on ‘Next’. 5. Confirm the Summary Page with ‘Finish’. 6. You are now presented with a picture of the PROM contents and an ‘Add Device’ box encouraging you to add your first device. Click ‘OK’ to continue. (If the ‘Add Device’ box does not appear, then right click where it is marked ** below and select ‘Add Xilinx Device…’ and navigate to the required configuration BIT file, select the file then click ‘Open’.). 7. Right click on the white background or where it is marked ** below (older iMPACT versions) and select ‘Generate File…’, the file is written to the directory specified in step 3 and the process is complete (see Fig 3-6). 8. Now see at chapter 3.1.4.1 for the programming commands.
Fig 3-5: Specify Xilinx PROM Device
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Fig 3-6: PROM File Formatter
3.3
Initializing the FPGA from flash
To be able to configure the FPGA from the flash contents the module has to be set up correctly. This is platform dependent, so it’s described for each module type here. 3.3.1 Zefant-XS3 A CPLD configuration supplied with the Flash Programmer can initialize the FPGA from flash in the parallel SelectMAP mode. Basically it counts up the addresses and waits until the FPGA has accepted the bytes from the flash data lines. The Jedec file can be found at /cpld/flashprog_xs3_cpld.jed The behaviour of the CPLD code can be controlled by DIP switch #1:
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pico-flashprog_zefant_instructions.doc Instructions for Programmers
DIP switch #1 setting ON OFF
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Boot Mode Initialize FPGA from flash JTAG only
3.3.2 Zefant-LC3E To boot from parallel flash memory, the mode pins of the FPGA have to be set to BPI mode. These pins are connected to the onboard DIP switches: DIP switch Signal 1 M0 / A2x 2 M1 3 M2 4 “SWITCH3”
Functionality Mode 0 M1 M2 free I/O
Please note that “ON” on the DIP switch generates a “low”/”0” on the signal. So, if you want to set the mode pins to “010”, set the switches to “101x” as shown here:
There are 2 BPI modes. One boots from 0 upwards in flash address range, the other from top downwards. DIP switch setting 1 2 3 4 1 0 1 x 1 0 0 x
Functionality M[2:0]=010 / Boot from 0x000000 upwards M[2:0]=011 / Boot from 0xFFFFFF downwards
So, you can leave 2 bitfiles in parallel flash simultaneously and select from which to boot by DIP switch 3.
4 Instructions for Programmers See at chapter 2 ‘Instructions’ for a general introduction. You will find all needed files in /Sources/common_FPGA/. For the Zefant-XS3 there is also a CPLD-Project located in /Sources/xs3_CPLD/.
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pico-flashprog_zefant_instructions.doc Version History
4.1
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Required Tools
The required tools are the same as above (see ‘Prerequisites’). 4.2
Steps to generate the Flash Programmer
There are two options to generate the Bitfiles. First of all the common points will be described. The file flash_programmer.vhd is the top level entity, here you have to adapt the frequency divisor in line 73 for your baud rate, depending on FPGA clock (UARTDIV = FPGA clock / 1843200Hz – 1). The line below is for 66 MHz FPGA clock. constant UARTDIV
•
•
: std_logic_vector(5 downto 0) := "100011";
If you start ISE with Flash_Programmer.ise you have to exchange (if necessary) the UCF with the suitable UCF, located in the same directory. Of course you have to change your FPGA-settings in the Project, if you use another model as configured. The other way to build the Bitfiles (after you have made changes to the VHDL code) is to execute the generate_bitfiles.cmd batch file. Here, all possible Bitfiles are generated and all settings are made for you. All files will be saved in /Bitfiles/ directory (empty before first run). Lets take a short look at the batch file: o Each Bitfile represents a block of 9 lines of code. The first 4 lines are deleting old projects files, which are affecting later builds. The next 5 lines are generating the Bitfile. There are three lines of particular interest. o xst -ifn *.txt -intstyle xflow This line describes the ISE XST synthesis options. All options are located in the textfile (e.g. fp_xc3s400_fg456.txt). o ngdbuild flash_programmer.ngc -p xc3s400-4-fg456 -uc *.ucf In this line the specified UCF file is loaded. o In the last line of a block (beginning with ‘bitgen’) the Bitfile is generated and placed at directory defined at the end of the command.
5 Version History Date 2008-05-14 2008-05-30
Version V0.1 V0.2
Comments Document created Added Chapters: Instructions for Programmers, Flashing FPGA configuration files – Generate a MCS file, Flash Programmer Commands
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