USB 3.0. Gervais Fong PHY Product Marketing Manager Eric Huang Digital Product Marketing Manager

USB 3.0 朝長宜央 日本シノプシス Gervais Fong PHY Product Marketing Manager Eric Huang Digital Product Marketing Manager 1 The Need for SuperSpeed USB Target A...
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USB 3.0 朝長宜央 日本シノプシス Gervais Fong PHY Product Marketing Manager Eric Huang Digital Product Marketing Manager

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The Need for SuperSpeed USB Target Applications

Media Storage

Media Creators

Media Players

Set-Top Boxes

Digital TVs

Create, Store and Carry More! Faster Sync-and-Go for Work and Play 3

Mobile Internet Devices

10x Faster Than USB 2.0 27GB HD Video Transfer USB 2.0 ~ 14 minutes USB 3.0 ~ 70 seconds

Complete IP Solution From the Leader in USB IP for 7 Years in a Row* Gartner/Dataquest 2008 4

SuperSpeed USB Market Adoption* Chip Set Market ASIC Market

Consumer Deployment Early Mainstream

Driven by Consumer Products Providers Crossover Suppliers

Early Products Initial Chips Finalize Specs

2008

Computer Deployment

2009 6

2010 2011

2012

Driven by Computer Companies *Estimated

Synopsys USB 3.0 Device and TI PHY Interoperability Testing

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NEC announces USB 3.0 Host Production

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AMD with USB 3.0?

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USB 3.0 Driver Standards •  USB Attached Storage Protocol –  Class Driver Specification in USB-IF Device Working Group –  Optimizing for USB 3.0 •  Required for 10x USB 2.0 Rates

–  Good for improving USB 2.0 Transfer Rates

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Summary •  HD content driving file sizes up •  Greater volumes of content are driving the need for more storage •  Faster transfer rates in demand by consumers

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USB 3.0 Specification • 

5Gbs Super-Speed Physical Layer Data Rate – 

• 

Compatibility –  – 

• 

Effective Throughput = 4Gbs after 8b10b overhead; 8Gbs with duplex operation USB 3.0 Host supports LS, FS, HS, and SS USB 3.0 Devices support HS and SS speeds

Optimized Power Efficiency –  No host polling, no broadcasting –  Fast U1 and U2 low power states in addition to traditional suspend (U3)

• 

Cables/Connectors –  –  – 

Additional 2 pairs of shielded twisted pair for super speed duplex Additional 5 pins (2 pair + GND) added Blue Connectors and Cables

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Cable & Connector •  •  • 

- USB3.0 Specific

Additional 2 pairs of shielded twisted pair signals in USB3.0 cable for super speed duplex operation Additional 5 pins (2 pair + GND) added to the existing USB connector (on the inside) Connectors are blue colored to distinguish from USB2.0 cables

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USB 3.0 Host Specification •  xHCI •  Intel –  http://www.intel.com/ technology/usb/xhcispec.htm

•  Single Architecture –  Including HS/FS/LS –  Compare USB2.0 • 

EHCI + UHCI/OHCI

•  Software for PC –  Microsoft Windows7 SP1

•  Discrete chip –  NEC Electronics 14

USB 3.0 Driver Standards •  USB Attached Storage Protocol –  Class Driver Specification in USB-IF Device Working Group –  Optimizing for USB 3.0 •  Required for 10x USB 2.0 Rates

–  Good for improving USB 2.0 Transfer Rates

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High Speed vs. SuperSpeed USB At Receiver after 2M USB Cable

HS 480Mb/s

Transmit Compliance At TX end of cable Eye TX Std Load

500

Cable At RX end of cable RX

Without USB 3.0 Cable

400

With USB 3.0 Cable

300

mV

SS 5Gb/s

200 100 0

-100 -200 -300 -400 -500

0.2

0.4

0.6

0.8

1.0

Time (ps)

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1.2

1.4

1.6

1.8

Synopsys USB 3.0 Complete Offering

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Complete DesignWare SuperSpeed USB IP Solution From a Single Vendor • 

Configurable Device or xHCI Host Controller and PHY for integration into SoCs

• 

Verification IP for integration testing in the customer’s SoC

• 

Linux software drivers as reference

• 

Virtual Platform with SystemC Transaction- Level Models for early software development

SuperSpeed USB PHY IP

• 

Supports SuperSpeed USB (USB 3.0 and Hi-Speed USB (USB 2.0)

SuperSpeed USB Verification IP

• 

Dual Power Rails and Unified Power Format (UPF) for low power consumption

Verification Environment SoC SuperSpeed Driver IP

MCCI SW/Service

Application SuperSpeed USB Device or xHCI Host IP

DesignWare IP

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USB3.0 Roadmap – Preliminary* 2008 Q3

2008 Q4

2009 Q1

1080p 30fps Demo Device Architecture August

Mass Storage Demo Device RTL Dec

Device EA† v0.50 Feb

2009 Q2

2009 Q3

3rd Party Interop Device EA† v0.90 Apr

2009 Q4

2010 Q1

2010 Q2

SNPS PHY & Core Device GA AHB Bulk v1.00 July

Device GA AXI ISOC AddOns v1.10 Oct

Drivers

VIP Virtual Platform Device TLM Dec

Virtual Platform Host TLM May

Host GA AHB Bulk v1.00 Oct

Host EA 1† v0.50a July

PHY Tape-out

† Bulk Only & AHB - Less Error Injection - Less USB2.0 Testing 20

Host GA AXI ISOC AddOns v1.10 Jan

Hub GA v1.0 Feb

*Subject to Change

Dual Role Device v1.00 Q2

USB 3.0 based on PCI-E SERDES & USB 2.0 •  •  •  •  • 

•  • 

Reuse of USB2.0 MAC and PHY Layers from OTG to reduce tape-out risk USB3.0 Link & PHY Layers from PCIe SERDES expertise and reuse Common Upper Layer to reduce area and to meet 10x USB3.0 throughput. Reuse HS OTG modules Single Programming model for USB1.1, USB2.0, and USB3.0 to minimize drivers •  Reduces memory requirement •  Reduces development and integration cost and time Static USB3.0 or USB2.0 Connection in Device Mode Concurrent USB1.1, USB2.0, and USB3.0 traffic in Host Mode/Multiport Mode

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SoC R A M

Digital

AHB, AXI, or OCP Master Interface For DMA

AHB, AXI, or OCP Slave Interface For Register Access

Bus Interface Buffer Management List Processor and Registers

USB 2.0 MAC

USB 3.0 MAC

FS/UTMI+/ULPI 3-pin/6-pin/8-bit/16bits

PHY

USB 2.0 Path

PIPE3 8/16/32 bits

USB 3.0 Path

D+ D-

Subject to change

SSTX SSRX

USB 3.0 Architecture

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Architecture - Highlights •  Clean clock domains for ease of Integration •  Bus, RAM, USB3PHY/MAC, and USB2PHY/MAC, •  Modular interfaces and self-documented clock domain crossing •  Parameters provides tradeoff for area/performance/power •  Low MIPs requirement •  All data routing handled by HW, driver gets interrupted only after transfer completion •  Multiple Transfers and Stream queuing •  Area Optimization •  Optional Cut through and multiple-packet modes for low-area and high-latency systems •  SP-RAM or DP-RAM •  Most Registers in RAM to reduce area •  Flexible Endpoint Configuration and TxFIFO Sharing •  Power Optimization: Clock-Gating, Two Power Rail, Complete Power Down modes – Plan to have UPF flow

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Architecture •  PHY – 

USB30 PHY (PIPE-3) interface •  32bits at [email protected] or [email protected] or [email protected] –  UTMI+/ULPI PHY Interface •  HS/FS/LS •  PHY Clock – 30/48/60Mhz

SoC R A M

•  BIU – AHB or AXI or OCP –  Native Interface Exposed •  Gasket to other buses –  Data Width: 32, 64, or 128 bits –  Range: 30MHz – 400MHz

Digital

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Bus Interface Buffer Management List Processor and Registers

USB 2.0 MAC

USB 3.0 MAC

FS/UTMI+/ULPI 3-pin/6-pin/8-bit/16bits

•  FIFO DP/SP-RAMs –  Requires DP-RAM for performance/Low Mhz –  1-3 RAMs: Rx FIFO, Tx FIFO, Descriptor Cache –  >= 250 Mhz for SPRAM, >= 125 Mhz for DPRAM

AHB, AXI, or OCP Master Interface For DMA

AHB, AXI, or OCP Slave Interface For Register Access

PHY

USB 2.0 Path

PIPE3 8/16/32 bits

USB 3.0 Path

D+ D-

Subject to change

SSTX SSRX

Deliverables •  cC Configurable Common USB30 coreKit –  Device or xHCI Host Controller – SS/HS –  cC Generates Verilog RTL

•  SystemVerilog Testbench (SVTB) –  –  –  – 

AHB and USB30 Model Test connectivity with protocol examples Users can port these to their SoC VCS Supported

•  Virtual Platform (Separate) –  USB 3.0 Device Model or Host Model

•  Drivers (Separate) –  Source for Reference Linux Platform

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Subject to change

Integration Considerations •  System Bus and System Memory need to support high bandwidth –  Device: For USB2.0 to meet 480Mbs, a 32-bit AHB bus at minimum needs to run at 15MHz, whereas to meet USB3.0’s 4Gb half-duplex rate it needs to run at 125MHz or to meet 8Gbs duplex rate it needs to run at 250Mhz –  Plus additional bandwidth needed for other devices in your system –  Wider bus recommended: 64-bit or 128-bits

•  Low latency System Bus and System memory are recommended to meet throughput and to avoid large buffers –  In USB2.0, a 1024byte packet takes approximately 20uS whereas in USB3.0 it takes only 3uS. USB3.0 can also burst up to 16 packets. –  For example, if the system Latency is 6uS, then each Tx endpoint would need at least 2KB buffers. In a 5 Tx endpoint configuration the RAM requirement will 5*2KB + 4KB (for common Rx) + 2KB for Descriptor Cache/Registers ~= 16KB (100K Gates equivalent)

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PHY solution •  Again HS,FS,LS(USB2.0/1.1) and SS needed •  Is offchip PHY realistic ? –  UTMI(ULPI) and PIPE3

•  Synopsys successed over 50 tech nodes USB2.0 and PCIe PHY •  Lowest power •  Smallest Foot print •  Considering shoreline 31

Virtual Platform for USB 3.0

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It’s Like Hardware – Only Better!

Early Availability

Available before chips come back from the fab and before boards have been built and debugged

Enhanced Debugging

Full visibility and control of multi-core platform with non intrusive access to all components

Easy to Deploy

No physical boards - minimal user ramp up time and logistical efforts to distribute and maintain

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Virtual Platforms Enabling Software-Driven Product Development What Is A Virtual Platform? •  Functional model of a complete hardware device •  Binary compatible, runs unmodified software •  High simulation performance, booting up an OS in seconds

Why Deploying Virtual Platforms? •  Pre-silicon software development, reducing project schedules by 9-12 months •  Reducing risk through continuous hardware/software integration •  Expand verification scenarios by adding real software use cases

Key Requirements •  Early availability •  Software binary compatibility with real RTL •  Must behave like the real device: user interfaces, debugger connections, real-world I/O access 35

USB 3.0 Device Demonstration

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USB3.0 Demonstration1 - Description •  •  • 

USB 3.0 Test-Host with 1 ISOC IN Channel connected to USB 3.0 Device which supports ISOC endpoint Uncompressed Video buffers from the Device are sent to the host and the Host driver will display it on the PC screen USB 3.0 Device in PC –  Uncompress1080p, 30 frames per second HD video –  Driver sends uncompressed video to USB 3.0 Device controller for USB 3.0 encoding. –  USB 3.0 Device controller send through Rocket I/O PHY

• 

PHY - Using Xilinx Virtex5 Rocket I/O –  Configured for USB3.0 –  5.0Gbps Signalling –  8b10b, SKP set, Training, & Rx Polarity Inversion

• 

Host and Device connected through coax cable to Lecroy CATC Analyzer –  Analyzer displays Superspeed USB 3.0 activity

• 

USB 3.0 Test Host in PC –  Receives data into Rocket I/O PHY –  Processes USB 3.0 packets, sends uncompressed data into Isoch buffers –  Application sofftware display video on screen

• 

Picture : http://www.engadget.com/2008/11/19/usb-3-0-demonstrations-dazzleuncompressed-1080p-transfer-prove 37

Demo – The setup - Two 8-lane PCIe cards connected through USB3.0 Cable & A/B Connectors – with SMA Conversion Adaptors. - Each PCIe card plugs in to a separate PC, one acts as test-Host and the other one as device

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Demo – The setup - Host PCIe FPGA, Device PCIe FPGA, USB3.0 cable, Ellisys & Lecroy USB3.0 Analyzers

Host PC

Device PC 40

Demo –Video 1080p @ 30fps

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USB3.0 Demonstration 2- Description •  Interoperability with 3rd party PHY •  MPEG Full HD Video buffers from the Device(Mass Storage) are sent to the host and the Host driver will display it on the PC screen •  USB 3.0 Device in PC –  1080p, 30 frames per second HD video –  Mimicing USB Mass Storage –  USB 3.0 Device controller send through TI PHY chip

•  USB 3.0 HOST in PC –  USB 3.0 HOST controller send through TI PHY chip

•  PHY – TI TUSB1310 –  Configured for USB3.0 –  5.0Gbps Signalling

•  Host and Device connected through real USB3.0 cable to Lecroy CATC Analyzer –  Analyzer displays Superspeed USB 3.0 activity

•  URL: http://focus.tij.co.jp/jp/pr/docs/preldetail.tsp? prelId=scj_09_041&contentId=55191 42

Future of USB 3.0

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USB3.0 SS vs SATA 6G USB3.0 SS

SATA 6G

Speed

5G bps

6G bps

Application



△ Storage only

Cable length

○ (3m)

△ (1m)

Isochronous





Set-to-set connection



? (eSATA) △(Cable)

Hot plug & unplug





Multi drop

○ (Hub)

△ (Port multiplier/option)

Cost





Bootable Device

△ (×Windows)



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USB3.0 Application other than Storage •  Good for NotePC •  External Video Graphic Adapter –  Multi screen for NotePC –  Maintenance for embedded system

•  USB SS -> PCI/PCIe converter –  Extending PCI/PCIe up to 3m –  Virtual Machine support

•  Ethernet to USB –  Extending USB 47

USB3.0 Application other than Storage •  External Video Graphic Adapter –  Multi screen for Note PCs –  External monitor for for embedded system •  Easy to expand, good for maintainance

–  DisplayLink provides a solution now •  It is too slow •  Not good for multimedia •  Not good for gaming •  Will be solved using USB3.0

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USB3.0 Application other than Storage •  USB SS -> PCI/PCIe converter –  PLX NET2280 •  Slow!!

–  Using SS of USB3.0 •  PCI and PCIe

–  Good for extending PCI/PCIe for Note PC and Factory Automation –  USB may be able similar capability to IOV of PCIe •  Virtual Machine( ex VMWare) supports like IOV via USB2 today 49

USB3.0 Application other than Storage –  Extending USB via ether net –  IOGear GUIP201 •  100G Ether and USB2.0 solution •  If using USB3.0 SS…

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