Table of Contents

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Structural Analysis

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SAR-1009-801 20768JMTW Revision 1.0

Published: September 28, 2010

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Structural Analysis Table of Contents 1

Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary

2

Device Overview 2.1 Downstream Product, Package, and Die Overview 2.2 Die Features

3

Process 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Transistors and Poly 3.6 High Voltage MOS Transistors 3.7 Isolation 3.8 Wells and Substrate

4

NAND Flash Cell Analysis 4.1 Overview 4.2 NAND Flash Plan-View Analysis 4.3 NAND Flash Cross-Sectional Analysis (Parallel to Bitline) 4.4 NAND Flash Cross-Sectional Analysis (Parallel to Wordline)

5

Materials Analysis 5.1 Overview 5.2 TEM-EDS and TEM-EELS Analyses of Dielectrics 5.3 TEM-EDS Analysis of Metallization and Contacts 5.4 TEM-EDS Analyses of Poly and Silicides

6

Critical Dimensions 6.1 Vertical Dimensions 6.2 Horizontal Dimensions

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Structural Analysis 7

References

8

Statement of Measurement Uncertainty and Scope Variation

About Chipworks

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Overview 1 Overview 1.1

List of Figures

2 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.1.14 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6

Device Overview Droid Xtreme Cell Phone Droid Xtreme Cell Phone – Main Board Package Photograph – Top Package Photograph – Bottom Package X-Ray – Side View Package X-Ray – Plan View Package End X-Ray Package Corner Plan-View X-Ray Package Flash Dice Bonding X-Ray Die Photograph – NAND Flash Die GWP2 Die Markings – NAND Flash Die GWP2 Die Photograph – NAND Flash Controller Die TMCL4 Die Markings – NAND Flash Controller Die TMCL4 Annotated GWP2 Die Photograph – Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Bond Pads Bond Pad

3 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5

Process General Device Structure Die Thickness Die Edge Die Seal Passivation ILD 2 ILD 1 ILD 1 – TEM PMD – TEM Minimum Pitch Metal 3 TEM Metal 3 Barrier and Adhesion Layers Minimum Pitch Metal 2 Minimum Pitch Metal 1 in the Periphery Minimum Pitch Metal 1 in the Array – TEM Array Metal 1 Edge – TEM Minimum Pitch Via 2s Minimum Pitch Peripheral Via 1s Minimum Pitch Array Via 1s – TEM Array Via 1s Parallel to the Bitlines – TEM Top of Via 1 – TEM

1-1

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Overview 3.4.6 3.4.7 3.4.8 3.4.9 3.4.10 3.4.11 3.4.12 3.4.13 3.4.14 3.5.1 3.5.2 3.5.3 3.5.4 3.6.1 3.6.2 3.7.1 3.7.2 3.7.3 3.7.4 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7

Minimum Pitch Contacts to Diffusion Bottom of Contacts to Diffusion in Periphery – TEM Bottom of Array Contacts to Diffusion – TEM Array Slot Contact to Diffusion – TEM Bottom of Array Slot Contact to Diffusion – TEM Contacts to Silicide – TEM Bottom of Contact to Silicide – TEM Interpoly Vias Interpoly Via – TEM Minimum Gate Length NMOS Transistor Minimum Gate Length PMOS Transistors Peripheral Transistors – TEM Logic Gate Oxide – TEM Peripheral High Voltage Transistor – TEM Thick Gate Oxide – TEM Poly over Isolation STI Edge – TEM Minimum Width Peripheral STI NAND Flash Array – Minimum Pitch STI (TEM) NAND Flash Array Embedded P-Well – SCM Embedded P-Well Detail – SCM Peripheral Wells – SCM Flash Array Embedded P-Well – SRP Shallow N-Well – SRP Lightly Doped P-Well Heavily Doped P-Well in the Periphery

4 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3.1 4.3.2 4.3.3 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6

NAND Flash Cell Analysis Metal 3 Metal 2 and Metal 1 Metal 1 to Substrate Transition Wordline and Bitline Contacts Wordline and Bitline Contact Detail Poly 1 Floating Gates and Bitline STI NAND Flash Array Overview – Parallel to Bitline Source Select Transistors and Contact Select Transistor and Flash Transistor – TEM NAND Flash Array Overview – Parallel to Wordline Wordline and Floating Gates – TEM Detail of Floating Gates – TEM Interpoly Dielectric – TEM Interpoly Dielectric Detail – TEM Tunnel Oxide – TEM

1-2

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Overview 5 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.4.1 5.4.2 5.4.3 5.4.4

Materials Analysis TEM-EDS Passivation 2 TEM-EDS Passivation 1 TEM-EDS ILD 2-2 TEM-EDS ILD 2-1 TEM-EDS ILD 1-3 TEM-EDS ILD 1-2 TEM-EDS ILD 1-1 TEM-EDS PMD 3 TEM-EDS PMD 2 TEM-EDS PMD 1 TEM-EDS CESL TEM-EDS Interpoly Dielectric Layers TEM-EELS Across the Interpoly Dielectric Layers TEM-EDS Metal 3 Body TEM-EDS Metal 3 Bottom TEM-EDS Metal 3 Upper Barrier Layer TEM-EDS Metal 3 Lower Barrier Layer TEM-EDS Metal 2 TEM-EDS Metal 2 Liner TEM-EDS Metal 1 TEM-EDS Metal 1 Liner TEM-EDS Top Polycide TEM-EDS Poly 2 Silicide TEM-EDS Interpoly Via Poly Fill TEM-EDS Contact Silicide

1-3

SanDisk/Toshiba SDIN4C2-8G 32 Gb MLC NAND Flash Toshiba 32 nm NAND Flash Process Overview 1.2

List of Tables

1 1.4.1 1.5.1 1.6.1

Overview Device Identification Device Summary Process Summary

2 2.1.1

Device Overview Package, Die, and Bond Pad Sizes

3 3.2.1 3.3.1 3.3.2 3.4.1 3.5.1 3.5.2 3.7.1 3.8.1

Process Measured Dielectric Thicknesses Metallization Measured Vertical Dimensions Metallization Measured Horizontal Dimensions Via and Contact Measured Dimensions Peripheral Transistor Horizontal Dimensions Transistor and Poly Vertical Dimensions STI Measured Dimensions Measured Well Depths and Die Thicknesses

4 4.1.1

NAND Flash Cell Analysis NAND Flash Cell Critical Dimensions

6 6.1.1 6.1.2 6.1.3 6.1.4 6.2.1 6.2.2 6.2.3 6.2.4

Critical Dimensions Dielectric Vertical Dimensions Metallization Vertical Dimensions Transistor and Poly Vertical Dimensions Well Depths and Die Thicknesses Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Peripheral Transistor Horizontal Dimensions STI Horizontal Dimensions

1-4

Manufacturer/Device Number DToshiba 32 nm NAND Flash Process About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company’s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world’s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation – earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches.

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