A core component of the MIPS datapath is the hardware that fetches an instruction from memory (and advances the PC by 4 bytes so that it refers to the next instruction). More specifically, the current value of the PC register is used to specify a location in the instruction memory, and the instruction stored at that location is read and passed on to other parts of the datapath. Simultaneously, an adder adds 4 to the current value of the PC (since MIPS instructions are exactly 4 bytes long). Then, since the Branch control line is not set by default, the multiplexor will pass through the new value, old PC + 4, and this value will be stored into the PC register on the next clock edge. Thus we have read the instruction at the current value of the PC and also updated the PC to refer to the next instruction. (Note: An adder works the same as a full ALU except that it can only perform addition, leading to a simpler circuit. In this case, one of the inputs also is always the constant value 4, a fact that can be used to simplify the circuit even further.)

R-type instructions take two registers as input and store their output in a third register. An example is add r1,r2,r3 which stores the sum r1 + r2 in register r3. Here the control line “RegDst” is set to 1 so that the destination register in the instruction (bits 15-11) will be passed through the multiplexor to the “Write Register” input of the register file. The source registers (bits 25-21 and 21-16 in the instruction) are passed to the two “Read Register” register inputs. The two values read from the source registers are passed as inputs to the ALU (since the “ALU_SRC” control line is NOT asserted), and the ALU performs the operation specified by the ALU control unit. The ALU control unit provides control signals to the ALU based on the value of the control line “ALU_OP”. Finally, since “MEM_TO_REG” is NOT asserted, the ALU’s result is passed through the mulitplexor to the “Write Data” input of the register file. In addition, since “REG_WRITE” is asserted, the register file will accept and store this input. The result value, therefore, is written into the given destination register.

Two registers are involved when storing a value in memory, one (bits 25-21 in the instruction) that holds the base address, and one (bits 20-16 in the instruction) that holds the value that we want to store. The offset field in the store instruction is sign extended to 32-bits, and passed as one of the two ALU inputs (due to the assertion of the “ALU_SRC” control line). The other ALU input is the base address read from the first register. The ALU, based on the setting of the “ALU_OP” control line, calculates the sum of the base address and the offset. This gives us the exact address where we want to store the value in memory. This exact address is simply connected to the “Address” input of the Data Memory, while the “Read Data 2” output of the register file is connected to the “Write Data” input of the Data Memory. This connection brings the value from the second register into the Data Memory unit.

The process of reading a value from memory is similar except that Bits 20-16 of the instruction now are used to identify the register into which we want to store the data. In addition, the MEM_TO_REG and WRITE_REG control lines are turned on so that the value read from memory will be stored in the desired register. This is a good place to mention that there still are things happening on many of the other lines. For example, Bits 20-16 still are passed to the “Read Register 2” input, and the “Read Data 2” output therefore will provide the value of the register that we really are using as a destination. This is okay, however, since the assertion of ALU_SRC means that this (old) value will not make it past the multiplexor to the main ALU. Similarly, the deassertion of WRITE_MEM means that this (old) value will not be stored into memory even though it does show up on the “Write Data” input of the Data Memory. The “Control” can be thought of as a conductor that is choosing multiplexor outputs and asserting or deasserting write signals depending on what we actually want to do.

The MIPS instruction beq r1,r2, will branch to the target address PC + 4 + offset * 4 if r1 is equal to r2. Note that PC + 4 is the address of the instruction to which we would go next if r1 is NOT equal to 2, and that the offset is stored as byte offset / 4 in the instruction. The latter works fine since instructions are all 4-bytes long and must appear at 4-byte boundaries in memory, and allows us to actually store 18 bits of byte offset (i.e., the 2 low-order zeroes are implied). The control unit asserts the “Branch” signal since we are executing a branch instruction, and the values of r1 and r2 are fetched from the register file and subtracted inside the ALU. If r1 is equal to r2 (as we assume in the diagram above), the ALU will assert the “zero” control line, and the AND gate will produce a 1, thus selecting the other input to the PC-update multiplexor. This other input is the result of adding the offset (shifted left by 2 bits to account for the 2 hidden bits) to the value of PC + 4. Of course, if r1 was NOT equal to r2, the AND gate would produce a 0 and the PC-update multiplexor would select the value PC + 4 (which is the instruction immediately after the branch).

BEQ