Thin Film Transistor Lab Guide

Thin Film Transistor Lab Guide Gate Electrode Layer: 1. Deposition ● Deposit a layer of Chromium 1000Å thick using the E – Beam Evaporator. ● Measure ...
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Thin Film Transistor Lab Guide Gate Electrode Layer: 1. Deposition ● Deposit a layer of Chromium 1000Å thick using the E – Beam Evaporator. ● Measure the sheet resistivity @ 10mA: ____________ ohms/square 2. Photolithography a. Coat/Bake ● Load the recipe “60 second primer” and center the wafer on the chuck. ● Cover the wafer uniformly with 80/20 primer and run recipe. ● Load recipe “1813 1 micron”, drop S1813 photo-resist on the center of the wafer until it spreads evenly into a 1.5 inch diameter circle. ● Run the recipe. ● Load the thermal process recipe “115 contact”. ● Once the spin process is complete, transfer the wafer to the hot plate and run the bake process. ● Measure the photoresist thickness: T=____________ angstroms o NOTE: Only use the halogen lamp on the spectrophotometer, the deuterium lamp will expose your photoresist. b. Exposure ● Attach mask “TFT Mask 1 - Gates” to the mask aligner. ● Look through microscope to check orientation of mask, text should appear right side up. ● Using the First Exposure setting with an exposure time of 1.5 seconds and a hard contact time of 2.0 seconds, expose the wafer to UV radiation. c. Development ● Load wafer into automated development bench. ● Run development recipe “1813 ONE MICRON”. ● Inspect wafer under microscope. 3. Etching ● Note: The etch time should be about 1minutes and 50 seconds. ● Etch away the Chromium using a bath of Chromium Etchant. ● Run wafer through SRD (Spin Rinse Dry) machine. 4. Stripping ● Strip the photoresist from wafer using “Quick Strip” method. ▪ Place wafer on spinner and flood with acetone. ▪ Start process “1813 1 micron”.



Once wafer starts spinning squirt IPA onto it through the holes in the spinner lid. ● Run wafer through SRD. 5. Descum in RIE ● Place wafer in RIE and run recipe “New Descum”. 6. Inspection ● This completes layer 1, Look at the structures under the microscope. The wafer should look like this image.

Active Layer: 1. Deposition ● Deposit 1000Å of Silicon Dioxide using the PECVD with the recipe “SiO2 Film 1000A”. ● Note: This recipe needs to run at 350C. Be sure to turn on the heater and allow it to reach temperature. ● Deposit 400Å of GIZO with the Sputter tool using recipe “GIZO 400 A". 2. Photolithography

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● Coat / Bake – Same process as in the gate step. ● Align and Expose ● The exposure settings should be Align and Expose with an exposure time of 1.5 seconds and a hard contact time of 2.0 seconds. ● Using the mask “TFT Mask 2 – Active”, use the microscope to find the alignment marks on the mask. ● Load the wafer and align the wafer to the mask, then expose to UV radiation. ● Development ● Same process as in the gate step. GIZO Etching ● Etch the GIZO layer using a bath of Aluminum Etchant. The etch time should be about 12 seconds. ● Run wafer through SRD. ● Inspect under microscope. Stripping ● Same process as in the gate step. Descum in RIE Inspection ● Layer 2 is now complete, inspect the wafer under the microscope and compare it to the following image.

Via Anti-Layer: Nothing is added in this step, instead we tunnel through the material added in the previous step. 1. Photolithography a. Coat / Bake – Same process as in the gate step. b. Align and Expose ● The exposure settings should be Align and Expose with an exposure time of 1.5 seconds and a hard contact time of 2.0 seconds. ● Use the mask “TFT - Mask 3 VIA”. ● Load the wafer and align the wafer to the mask, then expose to UV radiation. c. Development ● Same process as in the gate step. 2. Oxide Etching ● Etch the silicon oxide film in the RIE using the recipe “Oxide Via Etch”. 3. Stripping - Same process as in previous steps. 4. Inspection ● Inspect wafer under microscope and compare to the image below.

Source and Drain Layer: 1. Deposition ● Using the E-Beam Evaporator, deposit a 50Å thick layer of Chromium followed by a layer of gold 1000Å thick. 2. Photolithography a. Coat / Bake ● Prime wafer as done in previous steps. ● Load recipe “1805 half micron” on the spinner. ● Drop fresh SU1805 photoresist onto wafer, immediately close lid and run the recipe. ● Bake using same process as earlier steps. b. Align and Expose ● Use the mask “TFT - Mask 4 S/D Metal”. ● The exposure settings should be Align and Expose with an exposure time of 0.7 seconds. Use vacuum contact with a pre vac time of 4 seconds and a full vac time of 4 seconds. ● Load the wafer and align the wafer to the mask. ● Before exposure, use the check alignment function to see if the vacuum contact shifts the alignment. ● When alignment is achieved, expose to UV radiation. a. Development ● Same process as in the gate step. 3. Etching ● Etch the gold in a bath of gold etchant for about 20 seconds. ● Etch the chrome in a bath of chrome etchant for 5 to 6 seconds. 4. Stripping ● Same process as in the gate step. 5. Inspection ● This completes layer 3, Look at the structures under the microscope.

Reactivation: 1. O2 Annealing ● Anneal the wafer in O2 at 400 for 5 mins.

Testing: ● Electrically test the transistors using the Keithly source meter.