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TFT COLOR LCD MODULE Type: NL2432DR22-11B 8.9cm (3.5 Type) QVGA
SPECIFICATIONS （9th Edition, Issued on Jun. 12, 2002）
This document is preliminary. All information in this document is subject to change without prior notice.
Published by Color LCD Division Display Device Operations Unit NEC Electron Devices NEC Corporation
2002 All rights reserved. NEC Corporation
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No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors, which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are for use of “Standard” applications as specified below, and are not suitable for use of “Special” or “Specific” applications as specified below. NEC disclaims any responsibility or liability of any kind for any failure of equipment, personal injury or damage to property that may arise from the use of NEC devices for such “Special” applications. The devices listed in this document should not be used for such “Specific” applications. Application examples recommended by NEC Corporation. Standard:
Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).
Specific:
Military systems, aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, or any other equipment for which specifically high standard of quality or reliability is required.
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CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17.
DESCRIPTION ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.4 FEATURES ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.4 APPLICATIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.4 STRUCTURE AND FUNCTION ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.4 OUTLINE OF CHARACTERISTIC ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.5 BLOCK DIAGRAM ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.6 GENERAL SPECIFICATIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.8 ABSOLTE MAXIMUM RATINGS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.8 ELECTRICAL CHARACTERISTICS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.9 SUPPLY VOLTAGE SEQUENCE ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.10 INTERFACE PIN CONNECTIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.11 DISPLAY COLORS vs. DISPLAY POSITIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.13 INPUT SIGNAL TIMINGS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.14 OPTICAL CHARACTERISTICS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.16 RELIABILITY TESTS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.19 GENERAL CAUTIONS ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ P.20 OUTLINE DRAWING ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥P.21
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1. DESCRIPTION The NL2432DR22-11B is a color reflective active matrix TFT (Thin Film Transistor) color liquid crystal display (LCD) comprising amorphous silicon TFT attached to each display cell, driving circuits, a touch panel and LED front-light. The 8.9 cm (3.5 Type) diagonal display contains 240 × 320 pixels portrait and can display 262,144 colors simultaneously.
2. FEATURES • • • • • • •
Reflective type High contrast ratio and high brightness Front light and Touch panel attached Small footprint and light weight Driver interface (6-bit digital RGB signals) Recommended LCD controller (Part no.; S1L50282F23K100, NEC Corp.) Approved by UL1950 Third Edition and CSA-C22.2 No.950-95 (No.E170632)
3. APPLICATIONS • PDAs • Palm top terminals • Image viewers
4. STRUCTURES AND FUNCTION A color reflective TFT (thin film transistor) LCD module is comprised of a TFT liquid crystal panel structure with ICs for driving the TFT array. Sandwiching liquid crystal material in the narrow gap between a TFT array glass substrate and a color filter glass substrate creates the TFT panel structure. RGB (red, green, blue) color data and timing signals from a source system are input into column and gate drivers for active-matrix addressing the individual TFT cells. Acting as an Electro-optical switch, each TFT cell regulates light from the front-light. By regulating the amount of light reflection passing through the array of red, green, and blue dots, color images are created with clarity.
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5. OUTLINE OF CHARACTERISTICS (at room temperature) Display area
53.64 (H) x 71.52 (V) mm [Diagonal size 8.9 cm]
Drive system
a-Si TFT active matrix
Display colors
262,144 colors
Number of pixels
240 (H) x320 (V)
Pixel arrangement
RGB vertical stripe
Dot pitch
0.0745 (H) × 0.2235 (V) mm
Pixel pitch
0.2235 (H) × 0.2235 (V) mm
Module size
66.2 (Typ., H) × 91.0 (Typ., V) × 4.4 (Typ., D) mm
Weight
39.5 g (Typ.)
Contrast ratio
10:1 (Typ., with Front light and Touch panel )
Luminance
50 cd/m2 (Typ. IL=18mA)
Response time
32 ms (Typ., Ton + Toff)
Reflection ratio
40 % (Typ., with Front light and Touch panel)
Surface pencil hardness
3H (Min.)
Interface
Driver interface (6-bit RGB data, DCK, DE, POC, OEN)
Supply voltage
VCC 3.0 V (Typ., Logic) VDD 5.25 V (Typ., LCD driver) VGON 15.0 V (Typ., LCD driving) VGOFF -15.0 V (Typ., LCD driving)
Power consumption
LCD panel: 19 mW (Typ., Gamma and COM circuits in driver are included.) Front light: 255 mW (Typ., at IL=18mA)
9
9
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6. BLOCK DIAGRAM
FPC I/F COM circuit diagram
LCD panel + Driver + Front light + Touch panel
COM LCD panel Open GND
V0 to V4 GAM
Front light Touch panel
VCOM D00 to D05 D10 to D15 D20 to D25 INV CLK HSP STB POL AP
RAI 5 to 0 RAO5 to 0 GAI 5 to 0 GAO5 to 0 BAI 5 to 0 BAO5 to 0
Input
INV HCK HSP DLP PC HOE
DCK DE POC OEN
INVSE HDRSE PCI PCSE PANS DSE CKS HOEPW
H driver
VCK VSP VOE
VCK VSP VOE
Controller Note 1 V driver
Input
VCC VDD VGON VGOFF
V1 V2
YU XL YD XR
Note 1: Refer to the controller (part no.: S1L50282F23K100) specifications for input timings.
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FPC I/F Terminal No. 32 to 37 26 to 31 20 to 25 17 18 15 14 13 12 4 to 8
Symbol D00 to D05 D10 to D15 D20 to D25 CLK HSP AP STB POL INV V0 to V4
H driver
720 lines LCD panel V driver
9 10
GAM VCOM
40 44 42
VCK VSP VOE
43 41
VGON VGOFF
+15V -15V
16 39
VCC VDD
+3.0V +5.25V
2
COM
1,19,38,45
GND
320 lines H: 240 × 3 (R,G, B) V: 320
Reference design of COM circuit
VDD 100K COM
100K 50K
4.7μF/10V VCOM
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7. GENERAL SPECIFICATIONS Parameter Specification Module size 66.2 ± 0.2 (H) × 91.0 ± 0.2 (V) × 4.65 Max (D) 53.64 (H) × 71.52 (V) Display area [Diagonal display size: 8.9 cm (Type 3.52)] Number of pixels 240 (H) × 320 (V) Dot pitch 0.0745 (H) × 0.2235 (V) Pixel pitch 0.2235 (H) × 0.2235 (V) Pixel arrangement RGB (Red, Green, Blue) vertical stripe Display colors 262,144 Weight 42 (Max.)
8. ABSOLUTE MAXIMUM RATINGS Parameter Symbol
Supply voltage
pixel mm mm color g
Unit
Remarks
VCC
-0.3 to +4.0
V
Ta = 25 °C
VDD
-0.3 to +6.0
VGON
-0.3 to +44.0
V
Ta = 25 °C
VGOFF
VGON - 44.0 to +0.3 -0.3 to VCC+0.3
V
Logic signals
-0.3 to VDD+0.3
V
-
≤ 10
V
≤ 240
mW
Ta = 25 °C Above values are applied to V1 and V2. -
Top1
Relative humidity (RH) Note 1
-20 to +70 0 to +50 ≤ 95 ≤ 85
℃
Ta≤ 40°C
%
40°C 50°C
Storage altitude
≤ 13,600
m
-20°C ≤ Ta ≤ 70°C
Operating altitude
≤ 4,850
m
0°C ≤ Ta ≤ 50°C
Absolute humidity Note 1
9
mm
Rating
Logic input voltage VI Gamma control V0 to V4 voltage (Front light) VR Reverse voltage PD Power dissipation Storage temperature Tst Operating temperature
Unit mm
Note 1: No dew condensation Note 2: Ta = 50°C, RH = 85%
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9. ELECTRICAL CHARACTERISTICS (1) Logic/ LCD driving (Ta = 25°C) Parameter Symbol Min. Typ. Max. Unit Remarks Logic supply voltage VCC 2.6 3.0 3.6 V H driver supply voltage VDD 5.0 5.25 5.5 V V driver (+) supply voltage VGON 14.0 15.0 16.0 V VGOFF -14.0 -15.0 -16.0 V V driver (-) supply voltage Logic signal Logic input high voltage VIH 0.7×VCC VCC V Logic input low voltage VIL 0 0.3×VCC V GND Gamma control supply voltage V0 to V4 VDD-0.1 V +0.1 COM voltage input range COM VDD Vp-p COM center voltage Note COM/C 1.6 2.1 2.6 V At VDD=5.25 V VCC= 3.0 V VCC supply current ICC 0.2 1.0 mA Not include the controller VDD supply current IDD 3.3 8.0 mA VDD= 5.25 V VGON supply current IGON 0.04 0.1 mA VGON=15.0 V VGOFF supply current IGOFF 0.04 0.1 mA VGOFF= -15.0 V Note: The optimum value for COM/C is in the range of 1.6 to 2.6V. (2) Front light Parameter Forward current Forward voltage Total front light power
(Ta = 25°C) Symbol Min. Typ. Max. Unit Remarks Applied to V1 and V2 IL 18 20 mA (See diagram page 12) VL 5.9 7.1 7.9 V IL=18 mA PD 210 255 285 mW IL=18 mA
(3) Touch panel Electrical characteristics Parameter Symbol Input voltage Vtp Resistor between terminals (XL-XR) Rx Resistor between terminals (YU-YD) Ry Line linearity (X direction) Xlin Line linearity (Y direction) Ylin Insulation resistance Rins Capacitance Ctp Chattering Chat
Min. 3.3 200 200 10 -
Typ. 5 -
Mechanical characteristics Parameter Symbol Min. Typ. Operation starting force Ost 10 Surface hardness Hs 3 Input method: Finger or R0.8mm polyacetal stylus pen Input characteristics Parameter Point hitting life Line writing life
Max. 5.5 950 700 1.5 1.5 100 10
Max. 80 -
Unit Remarks V % % M At DC25V nF ms -
Unit Remarks g H Hardness of pencil
Symbol Min. Unit Remarks Lhp 1,000,000 times R0.8mm polyacetal stylus pen, 250g Lhr 1,000,000 times R3 silicon rubber, 300g Lwl 50,000 times R0.8mm polyacetal stylus pen, 250g , 35mm NEC Corporation
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10. SUPPLY VOLTAGE SEQUENCE
V
VGON
> 90%
VDD VCC Logic signals OEN
> 90%
0V
t ＞0
＞0
＞0
＞0 ＞0
> 90%
VGOFF
Remark 1: Supply voltage sequence must be kept according to the above timings. And when it is turned off, the sequence must be reversed. Remark 2: The “OEN” signal of the controller should be “H” after VGON. Remark 3: All signals should not be interrupted during the operation. Even if the signals recover, LCD module may not be operated correctly. In this case, reset the sequence again.
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11. INTERFACE PIN CONNECTIONS (1) Interface connector for signals and power CN1 Adaptable socket: FH12-45S-0.5SH (lower terminal type) or FH12A-45S-0.5SH (upper terminal type) Supplier: HIROSE ELECTRIC CO, LTD Pin No. Symbol Functions Pin No. Symbol Functions GND Ground D24 Blue data 1 24 COM Signal for common electrode D25 Blue data (MSB) 2 25 N.C. Non-connection D10 Green data (LSB) 3 26 V0 D11 Green data 4 27 V1 D12 Green data 5 28 Gamma control V2 D13 Green data 6 29 (Non–connection for internal gamma setting) V3 D14 Green data 7 30 V4 D15 Green data (MSB) 8 31 GAM Gamma selection switch D00 Red data (LSB) 9 32 VCOM Driver output signal D01 Red data 10 33 N.C. Non-connection D02 Red data 11 34 INV Data reversal signal D03 Red data 12 35 POL Polarity reversal signal D04 Red data 13 36 STB H driver latch signal D05 Red data (MSB) 14 37 AP H driver inhibition signal GND Ground 15 38 VCC Logic voltage VDD H driver voltage 16 39 HCK H driver shift clock VCK V driver shift clock 17 40 HSP H driver start pulse VGOFF V driver OFF voltage 18 41 GND Ground VOE V driver output enable (“L” output) 19 42 D20 Blue data (LSB) VGON V driver ON voltage 20 43 D21 Blue data VSP V driver start pulse 21 44 D22 Blue data GND Ground 22 45 D23 Blue data 23
Description of terminals Terminals Description This is the Common voltage. The voltage needs to be adjusted. COM The details are explained the above. Provide the gamma setting voltages. Maintain the following voltage relationships. V0 to V4 VSS V ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD In cases where the gamma voltages are supplied from outside, GAM needs to be set GAM “H”. Otherwise, GAM is “L” or “Open” for internal gamma setting. VCOM Output of VDD voltage at the falling edge of STB reversing the signal of POL. Invert input data signal. Synchronize with the shift clock. INV INV = L: Normal input INV = H: Invert input data This pin inverts the output polarity. The polarity inversion signal data is captured at the rising edge of STB. POL The gamma-resistor is switched in accordance with the positive/negative polarity. POL = H: Positive polarity POL = L: Negative polarity To be continued NEC Corporation
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Continued Terminals Description A timing signal that latches the contents of the data register. When an H level is read at the rising edge of CLK, the contents of the data register are latched and transferred to STB the D/A converter, and analog voltage corresponding to the display data is output. Also, because the internal operation via CLK continues even after the STB latch, do not stop CLK. The contents of the shift register are cleared at the rising edge of STB. This pin turns on/off the BIAS circuit and turns on the output SW and amplifier. When AP is H, the amplifier is set and the LCD is driving. The amplifier output and output SW are turned on at the rising edge of AP, starting the AP LCD drive. Note that the output SW is turned off at the rising edge of STB and the output becomes Hi-Z. This pin is the shift clock input of the column shift register. Display data is captured HCK into the data register at the rising edge. HSP Fetching of display data starts when H is read at the rising edge of CLK. This pin is the shift clock input of the gate shift register. The start pulse is captured at the VCK rising edge of clock and output the pulse at the falling edge. This pin controls the output of the gate drivers. Output can be controlled regardless of VOE VSP and VCK. VSP This pin synchronizes with the frame and the gate driver. (2) Interface connector for front light CN2 Adaptable plug: 04FLH-SM1-TB (Supplier: J.S.T. MFG CO., LTD.) Pin No. Symbol Functions 1 GND Ground (Left cathode) 2 V1 LED 1 Voltage (Left anode) 3 GND Ground (Right cathode) 4 V2 LED 2 Voltage (Right anode) (3) Interface connector for touch panel CN3 Adaptable plug: SFW4R-1STE1 (Supplier: FCI Japan) Pin No. Symbol Functions 1 XR Horizontal terminal (Right side) 2 YD Vertical terminal (Down side) 3 XL Horizontal terminal (Left side) 4 YU Vertical terminal (Up side) YU
V1, V2 GND
YU XL YD XR
XR
XL
YD NEC Corporation
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12. DISPLAY COLORS vs. DISPLAY POSITIONS (1) Display colors Data signal (0: Low level, 1: High level) R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Black 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blue 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Red 1 1 1 1 1 1 0 0 0 0 0 0 1 1 Magenta Basic 0 0 0 0 0 0 1 1 1 1 1 1 0 0 Green colors 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Cyan 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 White 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Black 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 dark : : : Red ↑ : : : grayscale ↓ 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 bright 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Red 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Black 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 dark : : : Green ↑ : : : grayscale ↓ 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 bright 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 Green 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Black 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dark : : : Blue ↑ : : : grayscale ↓ 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 bright 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Blue Remark 1: Colors are developed in combination with 6-bit signals (64 steps in grayscale) of each primary red, green, and blue color. This process can result in up to 262,144 (64×64×64) colors. Display colors
R5 0 0 1 1 0 0 1 1 0 0 0
R4 0 0 1 1 0 0 1 1 0 0 0
R3 0 0 1 1 0 0 1 1 0 0 0
R2 0 0 1 1 0 0 1 1 0 0 0
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(2) Display positions of input data
D (0, 0) R
G
D (1, 0) B
R
G
B
D( 0, 0 )
D( 1,0 )
•••
D(239,0 )
D( 0,1 )
D( 1, 1 )
•••
D(239,1 )
• • • • • •
• • • • • •
• • • • • •
• • • • • •
D( 0, 319 )
D( 1, 319 )
•••
D(239,319 )
13. INPUT SIGNAL TIMINGS (1) Input signal specifications for LCD controller (Ta=25℃､VCC=3.0V､VDD=5.25V) Timing characteristic Parameter Symbol Min. Typ. Max. Clock frequency PPHCK 5.4 7.2 Last data timing tLDT 2 STB frequency PPSTB 16.5 20.0 STB pulse width PWSTB 550 STB-HSP time tSTB-HSP 4 STB-AP time tSTB-AP 5 AP pulse width PWAP 15 VOE-AP time tVOE-AP 0 10 STB-POL time tSTB-POL 40 VCK-STB time tVCK-STB 1 3 VSP frequency PPVSP 50 65 Clock frequency PPVCK 16.5 20 Remark: All parameters should be kept within the specified range.
Unit MHz CLK kHz ns CLK μs μs μs μs μs Hz kHz
Remarks -
-
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Horizontal timing ch art PWSTB
tLDT
FLP (STB
PPHCK
FSCLK (HCK) FD2 :2 :23 3 (DATA
INVALID
240 #
2
INVALID
tSTB-HSP
FSSP (HSP)
tSTB-AP
PWM AP FMOD POL
PWAP
tSTB-POL
tVCK-STB
PWVOE
tVOE-AP
FLCLK (VCK,VOE)
H D r.-OU T
Hi- Z
V D r.-OU T
Hi- Z
VCOM-O UT Ve rtic al timing c hart FD2 :2 3 (DATA
Line
Line 2
Line 3
Line 320
INVALID
Line
Line 2
PPVCK
FLCLK (VCK,VOE)
PPVSP
FVSYNC (VSP)
V Dr.-OU T
INVALID
Line
Line 2
Line 3
Line 320
INVALID
Line
Po larity o f signal" POL" Frame N POL
Line
Line 2
Line 3
Line
Line 2
Line 3
VCOM-OUT Frame N+ POL VCOM-OUT
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14. OPTICAL CHARACTERISTICS < Front-light off > Parameter Contrast ratio Reflection ratio Chromaticity coordinates
Symbol CR RE W
< Front-light on > Parameter Contrast ratio Chromaticity coordinates Luminance
Symbol CR W Lu
Luminance uniformity
-
Condition White (x, y)
Note 1 Min. Typ. Max. Unit Remarks 7:1 10:1 Note 2,3 30 40 % Note 3 0.30, 0.31 Note 4 -
Note 1 Condition Min. Typ. Max. Unit Remarks 7:1 10:1 Note 2,5 White (x, y) 0.30, 0.31 Note 5 2 IL= 18mA 40 50 cd/m Note 5 Maximum luminance: 60 68 % Note 6 100%
9
9
< Reference data > Note 1 Parameter Symbol Condition Min. Typ. Max. Unit Remarks Response time Ton White to Black 90%→10% 15 30 (Module front surface ms Note 7 Toff Black to White 10%→ 90% 17 34 temperature=25℃) Note 1: Ta = 25 °C, VCC= 3.0V, Include front light and touch panel Note 2: The contrast ratio is calculated by using the following formula. Luminance with all pixels in "white" Contrast ratio (CR) = Luminance with all pixels in "black" Note 3: Contrast ratio and reflection ratio are measured as follows. Photo-detector Light
30° 10°
upper
lower
LCD or Reference (Standard diffused reflector)
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Note 4: White chromaticity coordinate is measured as follows. Photo-detector Optical diffusion treatment Light
LCD
Note 5: Contrast ratio, Chromaticity coordinates and Luminance are measured as follows.
1°
Photo-detector (TOPCON BM-5A)
50cm LCD MODULE
Note 6: Luminance uniformity is measured at the following 9 pints and is calculated by using the following formula.
Luminance uniformity (%) =
Minimum luminance Maximum luminance
x 100
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Note 7: Definitions of response time is as follows. Photo-detector output signal is measured when the luminance changes "white" to "black" or “black” to “white”.
White 100%
90%
Luminance
10%
Black 0%
Ton
Toff
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15. RELIABILITY TESTS Test item High temperature and humidity (Operation)
Condition
Judgments
1) 50 ± 2°C, RH = 85%, 240hours 2) Display data is black.
1) 0 ± 3°C…1 hour 55 ± 3°C…1 hour 2) 50cycles, 4 hours/cycle 3) Display data is black. 1) -20 ± 3°C…30 minutes Thermal shock 70 ± 3°C…30 minutes (Non operation) 2) 100cycles, 4 hour/cycle 3) Temperature transition time is within 5 minutes. No display malfunctions 1) 15 kPa Low pressure Note1 2) -20 ± 3°C…24 minutes (Non operation) 3) 70 ± 3°C…24 minutes 1) 53.3 kPa Low pressure 2) 0 ± 3°C…24 minutes (Operation) 3) 50 ± 3°C…24 minutes 1) 150pF, 150Ω, ±10kV ESD 2) 5 places on a panel surface (Operation) 3) 10 times each place at one-second intervals 1) 8 kinds of dust (by JIS-Z8901) Dust 2) 15 seconds stir (Operation) 3) 8 times repeat at 1 hour interval 1) 30 to 100Hz, 19.6m/s2 (2G) Vibration 2) 30 minutes/cycle (Operation) 3) X, Y, Z direction No display malfunctions 4) 1 time each direction Note1 No physical damages 1) 3920m/ s2 (400 G), 2.5ms Mechanical shock 2) X, Y, Z direction (Non operation) 3) 1 time each direction Note1: Display functions are checked under the same conditions as product inspection. Heat cycle (Operation)
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16. GENERAL CAUTIONS The following statements are very important, please be sure you understand the following information.
This symbol is a warning that you will get hurt if you make a mistake in operation.
(1) Un-packing caution Pick up the pouch only, when removing the module from a packing box. (2) Handling cautions a) As the electrostatic discharge may damage the LCD module, handle the LCD module with care avoiding electrostatic discharges. Peel the protection sheet from the touch panel surface as slowly as possible. b)
Since the LCD panel is made from fragile glass materials, impulse and pressure to the LCD module should be avoided.
c) As the surface of touch panel is easily scratched, use a soft dry cloth without chemicals for cleaning. d) Do not pull the interface connectors in or out while the LCD module is operating. e) Put the module rear side down on a flat horizontal plane. f) Handle FPC (Flexible Printed Circuit) and cables with care. g) When the module is operating, do not loose the logic signals. If any one or more of these signals were lost, the LCD panel would be damaged. h) Do not turn a front light cable to display side. i) Flexing or adding pressure to the module will result in a non-uniformity image. When the module is mounted to customer chassis, please evaluate the display condition carefully. (3) Atmosphere cautions a) Dew-drop atmosphere must be avoided. b) Do not store and/or operate the LCD module in a high-temperature and/or high-humidity atmosphere. Storage in the carrier tray and under the room temperature atmosphere is recommended. (4) LCD characteristics cautions Do not apply any fixed pattern data to the LCD module for a long time. It may cause image sticking. (5) Other cautions a) Do not disassemble and/or reassemble the LCD module. b) In case of returning the module for replacement and etc., please pack the LCD module properly to avoid any damages. NEC recommends to use the original shipping packages.
The liquid crystal display has the following specific characteristics. These are not defects or malfunctions. The ambient temperature may affect the optical characteristics of this module. Uneven brightness and/or small spots may be observed depending on different display patterns.
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17. OUTLINE DRAWING 66.2 ±0.2 (LCD
OUTLINE)
9 (TP OUTLINE)
53.64 (LCD
4.43 ±0.25
ACTIVE AREA)
31.75±0.25
2
RESPONCE AREA)
3.45 ±0.25
2 ±0.25
(TP VIEWING AREA)
54.64 (TP LCD ACTIVE AREA CENTER
±0.5
±0. 25
56.6
29.32
6.5
29.32 ±0.5
7. 74 ± 0.25
65.9 ±0.3
4.2
OUTLINE)
SERIAL:A2210036 PANEL:************* **.**.**/
E170632
R
C
US
MADE IN JAPAN
1
CN1
91
84 ± 0.3
(TP
± 0.2 ( L C D
OUTLINE)
± 0.25
44
38.76 ± 0 .5 ± 0 .5
38.76
AREA) VIEWING (TP
75
AREA) RESPONCE (TP
72.52
ACTIVE (LCD
45 4 CN3 1 CN2
1 CN2 A REA )
5
Ｂ
17.5 ± 0 .2
11.25
2.5
4
30
4.5 4.4
45.2
3.2
5.4
Ｂ’
16.5
4.5 4.4
(EXCLUDING F PC BE ND ING
47 21.5
CN3
71.52
CN1
5
23
AREA)
MODEL:NL2432DR22−11B
FPC(TP) FPC BENDING AREA
FPC(LED)
0.1
1.45
4.18
Remark ; The dimensions without tolerances are reference only.
3.2
A
FPC
DETAIL A
4.7
SECTION B-B'
NEC Corporation
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REVISION HISTORY The inside of latest specifications is revised to the clerical error and the major improvement of previous edition. Only a changed part such as functions, characteristic value and so on that may affect a design of customers, are described especially below. Edition
Document unmber
Prepared date
1st
DOD-N-0206
June 15, 2001
Revision contents New issue Signature of writer Approved by Checked by Prepared by H. Moriyama T. Kusanagi
DOD-N-0249
July 10, 2001
DOD-N-0275
July 26, 2001
Revision contents P4, 7 Weight: 45→52g typ. Power consumption: 28→26mW P5 BLOCK DIAGRAM is revised. GAM connected with GND P6 VDD voltage: VDD=-5.0 → VDD=+5.0 P8 γcontrol supply voltage: Min.;VDD+0.1 → GND+0.1 P8 Front light: 18.0mA → 50μA typ. 20.0mA → P8 Touch panel input voltage(Min) is added. P9 OEN signal is added P16 Touch Panel Characteristics is added. P19 Outline Drawing is revised. Signature of writer Approved by Checked by Prepared by H. Moriyama T. Kusanagi Revision contents P4 Weight 52 → 42g (Typ.) P7 Module size: 66.2 ± TBD(H) × 91.8 ± TBD (V) × 5.0 ± TBD (D) →66.2 ± 0.3(H) ×91.8 ± 0.3 (V) × 4.7 max.(D) P10 Adaptable socket: 04FH-SM1-TB → 04FLH-SM1-TB P11 Input signal timings are added. P17 Luminance: 15 → 25cd/m2 (Typ.) P22 Outline drawings are revising. Signature of writer Approved by Checked by Prepared by T. Yamaura T. Kusanagi
DOD-N-0286
Aug. 3, 2001
Revision contents P10 CN1 supplier: JAE → HIROSE ELECTRIC CO, LTD. P10 CN3 socket: SLW4R-5STE1 → SFW4R-1STE1 P22 Outline drawings are added. Signature of writer Approved by Checked by Prepared by T. Yamaura T. Kusanagi
DOD-N-0340
Oct. 10, 2001
Revision contents P4 ･Weight 42 → 39.5g (Typ.), ･Reflection ratio 17 → 40% ･Supply voltage VDD5.0 → 5.25V, ϒ control → LCD H-driver ･Power consumption 26 → 21mW P7 ･Module size: 66.2 ± 0.3 (H) ×91.8 ± 0.3 (V) × 4.7 max.(D) → 66.2 ± 0.2 (H) ×91.0 ± 0.2 (V) × 4.5 ± 0.2 (D) ･Weight 42 (Typ.) → 42g (Max.), (Front light) Reverse voltage and power dissipation are added ･Storage altitude: ≤ TBD → ≤ 13,600 ･Operating altitude: ≤ TBD → ≤ 4,850
edition
2nd edition
3rd edition
4th edition
5th edition
Revision contents and signature
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REVISION HISTORY Edition
5
th
Document unmber
DOD-N-0340
Oct. 10, 2001
DOD-N-0371
Oct. 18, 2001
DOD-N-0434
Jan. 11, 2002
DOD-N-0484
Mar. 4, 2002
edition
6th edition
7th edition
8th edition
Prepared date
Revision contents and signature
P8 ･H driver supply voltage: Min. 4.8 → 5.0V, Typ. 5.0 → 5.25V ･COM center voltage: Min. 1.3 → 1.6V, Typ. 1.8 → 2.1V ･Max. 2.3 → 2.6V, (V0-V4)/2=2.5 → 2.625V ･VCC supply current: Max. TBD → 1.0mA, ･VDD supply current: Typ. 5.2 → 3.7mA, Max. TBD → 8.0mA ･VDD =5.0V → 5.25V, VGON supply current: Max. TBD → 0.1mA ･VGOFF supply current: Max. TBD → 0.1mA ･(2)Front light and (3)Touch panel Parameters are revised. P10 γ control : (Non-connection) is added P11,14 INPUT SIGNAL TIMINGS: Some items are revised. P17 : Reflection ratio 17→ 40% P17 Chromaticity Coordinates: Typ. TBD → 0.30,0.31 Luminance Typ. 25 → 30cd/m2 Note3.: Measure condition of contrast ratio and reflection ratio are revised. P19 RELIABILITY TEST is added. P21 OUTLINE DRAWINGS are revised. Signature of writer Approved by Checked by Prepared by T. Yamaura T. Kusanagi Revision contents P.5 COM is added. P.8 Note 1. 1.3 → 1.6, 2.3 → 2.6 P.10 J.S.T. TRADING COMPANY LTD. → J.S.T. MFG CO., LFD. Signature of writer Approved by Checked by Prepared by T. Yamaura T. Kusanagi A. Kumano Revision contents P17 ･Contrast ratio: Min. TBD→(8:1) ･Reflection ratio: Min. TBD→30 ･Contrast ratio: Min. TBD→(8:1) ･Luminance: Min. TBD→24, Typ. 30→35 Response time: Ton Max. TBD→30, Toff Max. TBD→34 Signature of writer Approved by Checked by Prepared by H. Hada K. Kashimoto Revision contents P.8 8.Absolute humidity: Ta=50℃, RH=85% → ≤ 70 P.9 9.(1) V driver (-) supply voltage: Min. –16.0 → –14.0, Max. -14.0 → -16.0 VDD supply current: Typ. 3.7 → 3.3 (2)Total front light power is added. Mechanical characteristics are added. Input characteristics are added. P.11 11. Description of terminals is added. P.16 14. Luminance Min. 24 → 40, Typ. 35 → 50 Luminance uniformity is added. NEC Corporation
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REVISION HISTORY Edition
8th
Document unmber
DOD-N-0484
edition
Prepared date
Mar. 4, 2002
Revision contents and signature
P.17 Note5 is revised. P.18 Note7 is added. P.19 15. Low pressure and ESD is added. P.21 17. Nameplate label is added. Signature of writer Approved by M. Akiyoshi
9th edition
DOD-N-0589
Jun. 12, 2002
Checked by
Prepared by A. Kumano
P5 5 Module size (depth) 4.5mm(Typ.) → 4.4mm(Typ.) Dot pitch is added. P8 7 Module size (depth) 4.7mm(Max.) → 4.65mm(Max.) P16 14 Contrast Ratio at front light turning off 8:1(Min.) → 7:1(Min.) Contrast Ratio at front light turning on 8:1(Min.) → 7:1(Min.) P21 17 Outline is revised. Signature of writer Approved by M. Akiyoshi
Checked by S. Yoshikuni
Prepared by
A. Kumano
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NEC Corporation
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