System-Level Modeling and Design of Integrated MEMS
Tamal Mukherjee Department of Electrical and Computer Engineering Carnegie Mellon University
[email protected] http://www.ece.cmu.edu/~mems NSF Summer School on Computational Approaches for Simulation of MEMS, Friday, May 24
System Design Bottleneck 10000 1000
Gap
Design Complexity 100 (Million 10 transistors)
1 0.1
0.01 0.001 1960
100 10 1 0.1
Moore’s Law
1980
10000 1000 Design
Year
2000
Productivity (Million transistors per staff per year)
0.01 0.001 2020
Increasing gap between technology advancement and ability to design new systems [SIA] Design team sizes need to increase to eliminate gap c. Carnegie Mellon
1
MEMS Design Bottleneck ? 100
1
Design Complexity (# MEMS design 10 variables)
1 1960
Gap ?
1980
Year
2000
Design Productivity (Design variables 0.1 per staff per year)
0.01 2020
Same bottleneck, different scale How do we get design productivity to increase, so complexity can increase? c. Carnegie Mellon
Outline
MEMS Design Issues Process & Design Abstractions MEMS Circuit Level Modeling & Simulation Layout Generation Layout Verification Mesh Generation Synthesis Summary
c. Carnegie Mellon
2
Today’s MEMS Designers
Process flow
Materials characterization
1) Process design
c. Carnegie Mellon
Today’s MEMS Designers
Process flow
Materials characterization
Modeling of physical interactions
Layout-based design
Interface circuits
2) Component design
c. Carnegie Mellon
3
Bottom-Up Design
Macromodel Generation
Device design
System design c. Carnegie Mellon
Top-Down Design beam
fabrication requests op-amp resistor capacitor
■
Foundry
ApplicationSpecific Design
design rules, material parameters, device models
■
plate
w L L anchor w comb L w w N
Reusable, parametric models Macromodel bottleneck moved to library creation, and removed from design iteration c. Carnegie Mellon
4
MEMS Design Issues Layout Will it release ? Will it function ? Brownian noise Will it meet specifications ? Fn2 = 4kBT B ∆f Dynamic range e.g. Sensitivity (parasitics) Sensor resolution (noise) Design Interface circuits Electromechanical feedback systems Device matching Design for manufacturability, testability minimize sensitivity to variations account for device calibration c. Carnegie Mellon Î Requires hierarchical design methodology
Integrated MEMS Design
Application Driven ⇒ Low-volume custom MEMS
Design Methodology Characteristics Support wide variety of MEMS fab processes Supporting a wide class of MEMS designs Extensible to new MEMS design concepts Fits into the existing VLSI design flows Capable of evaluating integrated system designs
c. Carnegie Mellon
5
Outline
MEMS Design Issues Process & Design Abstractions MEMS Circuit Level Modeling & Simulation Layout Generation Layout Verification Mesh Generation Synthesis Summary
c. Carnegie Mellon
Process Abstractions: CMOS Micromachining
anchored electrodes
movable composite beam
~ 5 µm
circuits > 1.2 µm
etched pit
metal layers c. Carnegie Mellon
6
Process Abstractions: Polysilicon Micromachining anchored electrodes insulating plane movable polysilicon beam ~ 2-3 µm
> 2 µm c. Carnegie Mellon
Process Abstractions: Technology Capture
Decoupling of process complexity and design complexity through process abstraction
MEMS processing derived from VLSI Use VLSI process abstractions Layout technology file Model technology file Design rule file Layout (parasitic) extraction file
c. Carnegie Mellon
7
Process Abstractions: Layout Technology File
Same as VLSI Interface to foundry Layer definition GDS number Layer order Not required for simulation
(("Nwell" "drawing") (("Active" "drawing") ... (("Poly1" "drawing") (("P1Con" "drawing") (("Metal1" "drawing") (("Metal2" "drawing")
42 43
0 0
t) t)
46 47 49 51
0 0 0 0
t) t) t) t)
(("POLY0" "drawing") (("HOLE0" "drawing") (("POLY1" "drawing") (("ANCHOR1" "drawing") (("HOLE1" "drawing") (("POLY2" "drawing") (("HOLE2" "drawing") ...
13 41 45 43 44 49 46
0 0 0 0 0 0 0
t) t) t) t) t) t) t)
c. Carnegie Mellon
Process Abstractions: Model Technology File
Processdependent information Layer thicknesses Material properties Parameters common to all models in element library
`define `define `define `define `define `define `define
m1_resistivity m1_thickness m1_density spacer_gap E stress stress_gradient
0.07 0.7u 2700 20u 62G 300M 10M
`define `define `define `define `define `define `define
poly1_resistivity poly1_thickness poly1_density spacer_gap E stress stress_gradient
10 2u 2330 2u 165G 3M 0.1M c. Carnegie Mellon
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Process Abstractions: Design Rule Check
MEMS introduces Sacrificial etch to release structure Microstructure release of depends on Gap size Gap shape Gap spatial distribution
unreleased beam
unreleased plate
released plate c. Carnegie Mellon
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules A
CMOS-MEMS Example: A – Minimum and maximum structural width
c. Carnegie Mellon
9
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules
B
CMOS-MEMS Example:
A – Minimum and maximum structural width B – Minimum gap between structures
c. Carnegie Mellon
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules C
CMOS-MEMS Example:
A – Minimum and maximum structural width B – Minimum gap between structures C – Minimum structural metal extension
c. Carnegie Mellon
10
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules
D
CMOS-MEMS Example:
A – Minimum and maximum structural width B – Minimum gap between structures C – Minimum structural metal extension D – Minimum polysilicon spacing from edge
c. Carnegie Mellon
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules
E
CMOS-MEMS Example: A – Minimum and maximum structural width B – Minimum gap between structures C – Minimum structural metal extension D – Minimum polysilicon spacing from edge E – Minimum electronics spacing from edge c. Carnegie Mellon
11
Process Abstractions: MEMS-Specific Design Rules
MEMS release step adds new constraints on design rules
CMOS-MEMS Example:
F
A – Minimum and maximum structural width B – Minimum gap between structures C – Minimum structural metal extension D – Minimum polysilicon spacing from edge E – Minimum electronics spacing from edge F – Maximum beam length
c. Carnegie Mellon
Process Abstractions: MEMS DRC – “One Size Doesn’t Fit All” Minimum possible gap Function of adjacent structural width Etch rate depends on local neighborhood Structural design issues
Narrow gaps desired for actuation Wide structures desired for rigidity and wiring
Desire context-dependent DRC
c. Carnegie Mellon
12
Process Abstractions: Context Dependent DRC released released, if not a plate
undercut (µm)
20
curve for
15 other region 10 5
curve for plate region 0
0
5
10
15
20
inter-structure space (µm)
Etch rate different for plate and non-plate regions MEMS areas recognized by maximum etch criterion Released areas found by emulating etch phenomenon
B. Baidya et al., MSM 2001
c. Carnegie Mellon
Process Abstractions: Context Dependent DRC holes too small to release plate
w area released due to etchant coming from the sides
smaller gaps fail to release fingers
gaps having width same as the holes release the fingers
w
undercut dependent on gap c. Carnegie Mellon
13
Process Abstractions: Layout Parasitic Extraction Circuit Extraction
MEMS Extraction
•Recognizes layer overlaps and gaps •Capacitors, resistors and transistors
•Recognizes layer overlaps, gaps and geometrical features •Springs, plates, comb drives
c. Carnegie Mellon
Design Representations
3D Representations
Solid Model Mesh Original Design Entry Mode
c. Carnegie Mellon
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Design Representations
3D Representations
Solid Model Mesh Original Design Entry Mode
Layout
VLSI fabrication Preferred Design Entry Mode
c. Carnegie Mellon
Design Representations
Solid Model Mesh Original Design Entry Mode
Layout
V
3D Representations
VLSI fabrication Preferred Design Entry Mode
Behavioral Schematic
Fe M K
B
module resonator(vin); … parameter real K = 1 ; parameter real B = 1e-7 ; … analog begin Pos(Vtop)