STR-W6765 Quasi-Resonant Topology Primary Switching Regulators Features and Benefits

Description

▪ Quasi-resonant topology IC ⇒ Low EMI noise and soft switching ▪ Bottom-skip operation ⇒ Improved system efficiency over the entire output load by avoiding increase of switching frequency ▪ Standby burst mode operation ⇒ Lowers input power at very light output load condition ▪ Avalanche-guaranteed MOSFET ⇒ Improves systemlevel reliability and does not require VDSS derating ▪ 800 V / 1.8 Ω, 52 to 110 W (Universal/230 Vac input)

The STR-W6765 is a quasi-resonant topology IC designed for SMPS applications. It shows lower EMI noise characteristics than conventional PWM solutions, especially at greater than 2 MHz. It also provides a soft-switching operation to turn on the internal MOSFET at close to zero voltage (VDS bottom point) by use of the resonant characteristic of primary inductance and a resonant capacitor.

Continued on the next page…

Package: 6-pin TO-220

The package is a fully molded TO-220, which contains the controller chip (MIC) and MOSFET, enabling output power up to 52 W with universal input or 110 W with a 230 Vac input. The bottom-skip function skips the first bottom of VDS and turns on the MOSFET at the second bottom point, to minimize an increase of operational frequency at light output load, improving system-level efficiency over the entire load range. There are two standby functions available to reduce the input power under very light load conditions. The first is an auto-burst mode operation that is internally triggered by periodic sensing, and the other is a manual standby mode, which is executed by clamping the secondary output. In general applications, the manual standby mode reduces the input power further compared to the auto-burst mode. The soft-start function minimizes surge voltage and reduces power stress to the MOSFET and to the secondary rectifying Continued on the next page…

Typical Application +B

A

ErrAmp P

S1

GND

D

VCC

1

Standby ON/OFF

D

LowB

4

STR-W6735

S2

B

SI

Standby Out GND

Cont 6

FB 3

S/GND

ROCP

28103.30-6

7

OCP /BD

5

RX

SS /OLP

CX

A B

For ErrAmp, Sanken SE series device recommended For SI, Sanken linear regulator IC recommended

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765 Features and Benefits (continued) ▪ Various protections ⇒ Improved system-level reliability ▫ Pulse-by-pulse drain overcurrent limiting ▫ Overvoltage protection (bias winding voltage sensing), with latch ▫ Overload protection with latch ▫ Maximum on-time limit

Description (continued) diodes during the start-up sequence. Various protections such as overvoltage, overload, overcurrent, maximum on-time protections and avalanche-energy-guaranteed MOSFET secure good systemlevel reliability. Applications include the following: ▪ ▪ ▪ ▪

Set Top Box LCD PC monitor, LCD TV Printer, Scanner SMPS power supplies

Selection Guide Part Number

Package

Packing

STR-W6765

TO-220

Bulk, 100 pieces

Absolute Maximum Ratings at TA = 25°C Parameter Drain Current1 Maximum Switching Current2

Symbol IDpeak IDmax

Single Pulse Avalanche Energy3

EAS

Input Voltage for Controller (MIC) SS/OLP Terminal Voltage FB Terminal Inflow Current FB Terminal Voltage OCP/BD Terminal Voltage

VCC VSSOLP IFB VFB VOCPBD

MOSFET Power Dissipation4

PD1

Terminal Conditions 1 - 3 Single pulse 1 - 3 TA = –20°C to 125°C Single pulse, VDD = 99 V, L = 20 mH, 1-3 ILpeak = 5.8 A 4-3 5-3 6-3 6 - 3 IFB within the limits of IFB 7-3 With infinite heatsink 1-3 Without heatsink 4 - 3 VCC × ICC – Refer to TOP – – –

Rating 11.2 11.2

Unit A A

300

mJ

35 –0.5 to 6.0 10 –0.5 to 9.0 –1.5 to 5.0 28.7 1.3 0.8 –20 to 115 –20 to 115 –40 to 125 150

V V mA V V W W W °C °C °C °C

Controller (MIC) Power Dissipation PD2 Operating Internal Leadframe Temperature TF Operating Ambient Temperature TOP Storage Temperature Tstg Junction Temperature TJ 1Refer to figure 2 2I DMAX is the drain current determined by the drive voltage of the IC and the threshold voltage, Vth, of the MOSFET 3Refer to figure 3 4Refer to figure 5

All performance characteristics given are typical values for circuit or system baseline design only and are at the nominal operating voltage and an ambient temperature of +25°C, unless otherwise stated.

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

2

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765 4

VCC

+ -

Reg& Iconst

Start Stop Burst

OVP

R

Burst Control

Delay

Q

S/GND

OSC MaxON

+ Soft Start

D

BD

+ -

OCP/BD SS/OLP

Counter

Description Drain

3 6

OCP

+

Bottom Selector

OLP

Name

BSD

R

FB

+ FB +

S Q

S

1

1

S

R Q

Number

D

DRIVE Reg

Protection latch

7 5

Functions MOSFET drain

2

NC

Clipped

No connection

3

S/GND

Source/ground terminal

MOSFET source and ground

4

VCC

Power supply terminal

Input of power supply for control circuit

5

SS/OLP

Soft Start/Overload Protection terminal

Input to set delay for Overload Protection and Soft Start operation

6

FB

Feedback terminal

Input for Constant Voltage Control and Burst (intermittant)Mode oscillation cotnrol signals

7

OCP/BD

Overcurrent Protection/Bottom Detection

Input for overcurrent detection and bottom detection signals

Figure 1 – MOSFET Safe Operating Area Derating Curve

Figure 2 – MOSFET Safe Operating Area Drain Current versus Voltage at TA = 25°C, Single Pulse 100.0

60

0.

1

it

lim (on) nt S rr e o R D Cu ue t d

1.0

m

s

s

40

11.2 10.0 m

Drain Current, ID (A)

80

1

Safe Operating Area Temperature Derating Coefficient (%)

100

20 Refer to figure 1 for MOSFET SOA temperature derating coefficient 0

0

25

50

75

100

125

150

0.1

1

10

100

1000

Drain-to-Source Voltage, VDS (V)

Temperature, TF (°C)

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

3

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

Figure 3 – MOSFET Avalanche Energy Derating Curve

Figure 4 – Transient Thermal Resistance 10.000 Transient Thermal Resistance, RQJC (°C/W)

80

60

40

20

0

1.000

0.100

0.010

0.001 25

50

75

100

125

150

1μ

10μ

100μ

1m

10m

100m

Time, t (s)

Channel Junction Temperature, TJ (°C)

Figure 5 – MOSFET Power Dissipation versus Temperature 30

25 Power Dissipation, PD1 (W)

EAS Temperature Derating Coefficient (%)

100

With infinite heatsink PD1 = 28.7 W at TA ”ƒ&

20

15

10

5

0

Without heatsink PD1 = 1.3 W at TA ”ƒ& 0

20

40

60

80

100

120

140

160

Ambient Temperature, TA (°C)

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

4

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765 ELECTRICAL CHARACTERISTICS Characteristic

Symbol

Terminals

Min.

Typ.

Max.

Units

ELECTRICAL CHARACTERISTICS for Controller (MIC)1, valid at TA = 25°C, VCC = 20 V, unless otherwise specified Power Supply Start-up Operation Operation Start Voltage

VCC(ON)

4-3

16.3

18.2

19.9

V

Operation Stop Voltage

VCC(OFF)

4-3

8.8

9.7

10.6

V

Circuit Current In Operation

ICC(ON)

4-3

–

–

6

mA

Circuit Current In Non-Operation

ICC(OFF)

4-3

–

–

100

μA

Oscillation Frequency

fosc

1-3

19

22

25

kHz

Soft Start Operation Stop Voltage

VSSOLP(SS)

5-3

1.1

1.2

1.4

V

Soft Start Operation Charging Current

ISSOLP(SS)

5-3

–710

–550

–390

μA

Bottom-Skip Operation Threshold Voltage 1

VOCPBD(BS1)

7-3

–0.720

–0.665

–0.605

V

Bottom-Skip Operation Threshold Voltage 2

VOCPBD(BS2)

7-3

–0.485

–0.435

–0.385

V

Overcurrent Detection Threshold Voltage

VOCPBD(LIM)

7-3

–0.995

–0.940

–0.895

V

Normal Operation

IOCPBD

7-3

–250

–100

–40

μA

Quasi-Resonant Operation Threshold Voltage 1

VOCPBD(TH1)

7-3

0.28

0.40

0.52

V

Quasi-Resonant Operation Threshold Voltage 2

VOCPBD(TH2)

7-3

0.67

0.80

0.93

V

VFB(OFF)

6-3

1.32

1.45

1.58

V

IFB(ON)

6-3

600

1000

1400

μA

Standby Operation Start Voltage

VCC(S)

4-3

10.3

11.1

12.1

V

Standby Operation Start Voltage Interval

VCC(SK)

4-3

1.10

1.35

1.65

V

OCP/BDOCP/BD Terminal Outflow Current

FB Terminal Threshold Voltage FB Terminal Inflow Current (Normal Operation) Standby Operation

Standby Non-Operation Circuit Current

ICC(S)

4-3

–

20

56

μA

FB Terminal Inflow Current, Standby Operation

IFB(S)

6-3

–

4

14

μA

FB Terminal Threshold Voltage, Standby Operation

VFB(S)

6-3

0.55

1.10

1.50

V

Minimum On Time

tON(MIN)

1-3

0.40

0.82

1.25

μs

Maximum On Time

tON(MAX)

1-3

27.5

32.5

39.0

μs

Overload Protection Operation Threshold Voltage

VSSOLP(OLP)

5-3

4.0

4.9

5.8

V

Overload Protection Operation Charging Current

ISSOLP(OLP)

5-3

–16

–11

–6

μA

VCC(OVP)

4-3

25.5

27.7

29.9

V

ICC(H)

4-3

–

45

140

μA

VCC(La.OFF)

4-3

6.0

7.2

8.5

V

Protection Operation

Overvoltage Protection Operation Voltage Latch Circuit Holding

Current2

Latch Circuit Release Voltage2

ELECTRICAL CHARACTERISTICS for MOSFET, valid at TA = 25°C, unless otherwise specified Drain-to-Source Breakdown Voltage Drain Leakage Current

VDSS

1-3

800

–

–

V μA

IDSS

1-3

–

–

300

On Resistance

RDS(on)

1-3

–

–

1.8

Ω

Switching Time

tf

1-3

–

–

400

ns

–

–

1.55

°C/W

Thermal Resistance

RθJA

Junction to Internal Frame

1Current

polarity with respect to the IC: positive current indicates current sink at the terminal named, negative current indicates source at the terminal named. 2Latch circuit refers to operation during Overload Protection or Overvoltage Protection.

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

5

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

ELECTRICAL CHARACTERISTICS Test Conditions* Parameter Operation Start Voltage Operation Stop Voltage Circuit Current In Operation Circuit Current In Non-operation Oscillation Frequency Soft Start Operation Stop Voltage Soft Start Operation Charging Current Bottom-Skip Operation Threshold Voltage 1 Bottom-Skip Operation Threshold Voltage 2 Overcurrent Detection Threshold Voltage OCP/BDOCP/BD Terminal Outflow Current Quasi-Resonant Operation Threshold Voltage 1 Quasi-Resonant Operation Threshold Voltage 2 FB Terminal Threshold Voltage FB Terminal Inflow Current (Normal Operation) Standby Operation Start Voltage Standby Operation Start Voltage Interval Standby Non-Operation Circuit Current FB Terminal Inflow Current, Standby Operation FB Terminal Threshold Voltage Standby Operation Minimum On Time Maximum On Time

Test Conditions VCC voltage at which oscillation starts. VCC voltage at which oscillation stops. Inflow current flowing into power supply terminal in oscillation. Inflow current flowing into power supply terminal prior to oscillation. Oscillating frequency ( fosc= 1 / T ). SS/OLP terminal voltage at which ISS/OLP reach ≥–100 μA by raising the SS/OLP terminal voltage from 0 V gradually.

VCC (V)

Measurement Circuit

0→20 20→8.8 20 15 20

1

20

5

20

3

20

2

SS/OLP terminal charging current (SS/OLP terminal voltage = 0 V). Input 1 μs pulse width, as shown in waveform 1, to OCP/BD terminal twice after V1-3 rises. After that, offset the input waveform gradually from 0 V in the minus direction. Measurment of the offset voltage VOCPBD(BS1) is taken when the V1-3 start-to-fall point switches from twopulses-after to one-pulse-after. After measuring VOCPBD(BS1), as shown in waveform 2, offset the input waveform gradually. Measurment of the offset voltage VOCPBD(BS2) is taken when the V1-3 start-to-fall point switches from two-pulses-after to one-pulse-after. OCP/BD terminal voltage at which oscillation stops by lowering the OCP/BD terminal voltage from 0 V gradually. OCP/BD terminal outflow current (OCP/BD terminal voltage = –0.95 V). OCP/BD terminal voltage at which oscillation starts with setting the OCP/BD terminal voltage at 1 V, and then lowering the voltage gradually. OCP/BD terminal voltage at which oscillation stops by raising the OCP/BD terminal voltage from 0 V gradually. FB terminal voltage at which oscillation stops by raising the FB terminal voltage from 0 V gradually. FB terminal inflow current (FB terminal voltage = 1.6 V). VCC voltage at which ICC reaches ≥1 mA (FB terminal voltage = 1.6 V). Specified by VCC(SK) = VCC(S) – VCC(OFF).

20 20 0→15 –

Inflow current flowing into power supply terminals prior to oscillation (FB terminal voltage = 1.6 V).

10.2

FB terminal inflow current (FB terminal voltage = 1.6 V).

10.2

FB terminal voltage at which oscillation starts by raising the FB terminal voltage from 0 V gradually. Waveform between terminals 1 and 3 at low. Waveform between terminals 1 and 3 at low.

4

15 20 20

6 1

Continued on the next page…

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

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Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

ELECTRICAL CHARACTERISTICS Test Conditions*, continued Parameter

Test Conditions

VCC (V)

Overload Protection Operation Threshold Voltage Overload Protection Operation Charging Current Overvoltage Protection Operation Voltage

SS/OLP terminal voltage at which oscillation stops.

20

SS/OLP terminal charging current (SS/OLP terminal voltage = 2.5 V).

–

Latch Circuit Holding Current

Inflow current at VCC(OFF) – 0.3; after OVP operation.

Measurement Circuit 5

VCC voltage at which oscillation stops.

Latch Circuit Release Voltage VCC voltage at which ICC reaches 20 μA or lower by decreasing VCC after OVP operation. Drain-to-Source Breakdown Voltage IDSS = 300 μA Drain Leakage Current VDSS = 800 V Single Pulse Avalanche Energy – On-Resistance IDS = 1.4 A Switching Time – *Oscillating operation is specified with a rectangular waveform between terminals 1 and 3.

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

0→30 VCC(OFF) – 0.3 30→6 – – 30 20 20

1

7 8 9 1

7

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

Measurement Circuit 1

D

㧝

S/GND

VCC

SS/OLP

㧠

㧟

FB

㧡

㧢

OCP/BD

㧣

‫ޓ‬T

90㧑 50㧑

TON

V

100ǡ

10㧑

4.7kǡ

0.1ǴF

A

ICC tf

VCC

10V

Measurement Circuit 2

D

㧝

S/GND

㧟

SS/OLP

VCC

㧠

FB

㧡

㧢

OCP/BD

㧣

100ǡ

4.7kǡ

0.1ǴF

VCC 20V

10V

Measurement Circuit 3

D

㧝

S/GND

㧟

VCC

SS/OLP

㧠

FB

㧡

㧢

OCP/BD

㧣

100ǡ

4.7kǡ

0.1ǴF

VCC 10V

20V

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

8

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

Measurement Circuit 4 D

S/GND

㧝

SS/OLP

VCC

㧠

㧟

FB

㧡

OCP/BD

㧢

㧣

0.1ǴF

V

100ǡ

V 4.7kǡ

A

A

VCC

10V

Measurement Circuit 5 D

S/GND

㧝

SS/OLP

VCC

㧠

㧟

OCP/BD

FB

㧡

㧢

㧣

100ǡ

V A VCC 20V

10V

Measurement Circuit 6

D

㧝

S/GND

㧟

VCC

㧠

SS/OLP

FB

㧡

OCP/BD

㧢

㧣

5V OSC1 100ǡ 200㨪500nS

4.7kǡ

0.1ǴF

9V

OSC1 VCC

V1-3

10V

20V

TON㧔MIN㧕

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

9

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

Measurement Circuit 7 D

S/GND

㧝

SS/OLP

VCC

㧟

㧠

FB

㧡

OCP/BD

㧢

㧣

IDSS VDSS

MOSFET MOSFET measuring equipment

Measurement Circuit 8

D

S/ GND

㧝

㧟

30V

VCC

SS/OLP

VCC

㧠

FB

㧡

㧢

OCP/BD

㧣

VDS

0

Equation for calculation of avalanche engery, EAS; to be adjusted for ILPeak = 5.8 A

IL IL

‫ޓ‬

VD SPeak

VDS VDD 0

Avalanche energy tester

E AS

T1

VDS Peak 1 2 ˜ L ˜ ILPeak ˜ 2 VDS Peak  VDD

VCC

Measurement Circuit 9 D

S/ GND

㧝

㧟

VCC

㧠

SS/OLP

㧡

FB

㧢

OCP/BD

㧣

4.7kǡ VDS(ON) IDS 0.1ǴF RDS(ON)=VDS(ON)/IDS 20V

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

10

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

Waveform 1

VDS

VOCP/BD GND

VOCPBD(BS1)

Waveform 2

VDS

VOCP/BD GND

VOCPBD(BS2)

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

11

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

PACKAGE DIMENSIONS, TO-220

Ø3.2 ±0.2

2.6 ±0.1 Terminal dimension at case surface

(5.4)

1)

5.0 ±0.5

×R

+0.2

1.74 –0.1

(2

+0.2

1.34 –0.1

6×P1.27 ±0.15 = 7.62 ±0.15 Terminal dimensions at case surface

10.4 ±0.5

XXXXXXXX XXXXXXXX

2.8 MAX

Branding

16.9 ±0.3

2.8 ±0.2

7.9 ±0.2

Gate Burr

4.2 ±0.2

4 ±0.2

10.0 ±0.2

+0.2

0.45 –0.1

5.08 ±0.6 Terminal dimension at lead tips

1 2 3 4 5 6 7

Gate burr: 0.3 mm (max.) Terminal core material: Cu Terminal treatment: Ni plating and solder dip Heat sink material: Cu Heat sink treatment: Ni plating Leadform: 2003 Weight (approximate): 2.3 g Dimensions in millimeters

Drawing for reference only Branding codes (exact appearance at manufacturer discretion): 1st line, type: W6765 2nd line, lot: YMDD R Where: Y is the last digit of the year of manufacture M is the month (1 to 9, O, N, D) DD is the 2-digit date R is the manufacturer registration symbol

Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

12

Quasi-Resonant Topology Primary Switching Regulators

STR-W6765

PACKING SPECIFICATIONS Minimum packing option: Tube FM-205 E

4.8

+0.4 0

1.4

5.1 9 × R0.6

35.0

(15.4)

9.5–0.1

+0.3

8.9

Shipping Tube Dimensions: Wall thickness: 0.6±0.3 mm Wall warp: