SPI Flash Application Notes

AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes SPI Flash Application Notes SUBSTANCE 1. Introduce hardware and software prote...
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AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes

SPI Flash Application Notes SUBSTANCE 1.

Introduce hardware and software protection modes and their differences

2.

Important notes on deep power down mode

3.

Important notes on SPI FLASH under standby mode.

DESCRIPTION Hardware & Software Protection Mode SPI Flash protection mode includes software protection mode and hardware protection mode.

Hardware Protection Mode (HPM) requires SRWD set to 1 and WP# pin signal in low state.

In hardware

protection mode, the Write Status Register (WRSR) instruction is no longer accepted execution and the SRWD bit and Block Protect bits (BP0~BP3, varied according to FLASH size) are By using WP# going low to protect the BP0-BP2 bits and SRWD bit from data change.

Software Protection Mode (SPM), except hardware protection mode, all other settings (When SRWD bit=0 regardless WP# is low or high or when SRWD bit=1 and WP# is high) are software protection mode (please refer to the following table). In software protection mode, only memory is protected and the written-protected area must be defined in Status Register’s BP0 ~ BP3.

In software protection mode, the WREN instruction may set the WEL bit and change the values of SRWD, BP2, BP1, and BP0. The protected area, defined by BP2, BP1, and BP0, is at software protection mode (SPM).

 Generalplus Technology Inc.

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Jul. 06, 2016

AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes Note 1: SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operating along with Write Protection (WP#) pin for hardware protection mode. Note 2: BPx bits. The Block Protection (BP0, BP1, BP2 or BP3) bits, non-volatile bits, indicate the protected area (as defined in table 1) of the device against the program/erase instruction without hardware protection mode being set. Writing the Block Protection (BP2, BP1, and BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory against Page Program (PP), Sector Erase (SE), Block Erase (BE), and Chip Erase (CE) instructions (only if all Block Protection bits are set to 0, the CE instruction can be executed).

Table.1 Protected area size (may vary based on flash sizes); please refer to SPI Flash data sheet for more information.

Deep Power Down Mode The Deep Power Down (DP) instruction is to minimalize the device’s power consumption (to enter the Deep Power-Down Mode). During the Deep Power-Down Mode, the device is not in active and all Write/Program/Erase instructions are ignored.

Once the DP instruction is set, all instructions will be ignored except releasing from

Deep Power-Down Mode (RDP) and Read Electronic Signature (RES) instruction.

Suppose the master IC,

which is connecting with the SPI FLASH, establishes the DP instruction and SPI FLASH enters the Deep Power-Down mode.

Under these circumstances, if the master IC triggers a reset signal and because SPI FLASH

is under the Deep Power-Down Mode, the master IC’s initialization command to SPI FLASH will become void. To avoid such scenario, we recommend users issue SPI FLASH the F_SPI_GetID command (Get the FLASH ID via SPI interface) during master IC’s initialization to see whether SPI FLASH data can be read correctly.

If not,

the RDP instruction must be issued to wake SPI FLASH up from Deep Power-Down Mode.

 Generalplus Technology Inc.

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Jul. 06, 2016

AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes

Example 1: Make SPI FLASH enter Deep Power Down Mode, which minimalizes the power consumption of SPI FLASH.

Example 2: RDP instruction makes SPI FLASH release from Deep Power-Down Mode

 Generalplus Technology Inc.

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Jul. 06, 2016

AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes Example 3: During power on initialization, the master IC should issue the Read Flash ID instruction to assure whether or not FLASH is in Deep Power Down Mode. Standby Mode In standby mode, users must ensure that SPI interface is not under floating condition in order to make standby current stabilized.



Serial Peripheral Interface (SPI) allows the master IC to control many slave devices (see diagram below).

Technically, when CSB is high, SI and SO on the slave devices must be floating or high impedance to prevent bus fighting.

Master IC MISO MOSI SCK MCU

CSB1 CSB2 CSB3



SCK SI SO

SCK SI SO

SCK SI SO

SPI Device

SPI Device

SPI Device

CSB

CSB

CSB

When GPR25L’s SPI FLASH or GPR26L’s SPI ROM is in standby mode (CS pin = HIGH) or deep power

down mode (SPI ROM doesn’t have this mode), the SO pin will stay at high impedance condition, and SI pin will be in input floating condition.

In the figure next page, users must ensure if both MISO and MOSI pins on the

master IC are in non-floating condition (e.g. output mode or input pull low) before the system enters standby mode. If these two pins are under floating condition, there might be some current drain leakage occurred and furthermore, an increase of standby current will be yielded. Master IC

SPI Device

CSB

CSB

SCK

SCK

MISO

SO

MOSI

SI

GPxxxxx



GPR25Lxxx/ GPR26Lxxx

If the SPI interface is controlled by hardware or if there are some other factors making MISO or MOSI to

floating state, a 100K-Ohm pull-low resistor can be added to the floating pin (See R1 and R2 in the diagram below) to stabilize the standby current.

If the master IC uses GPIO as a SPI interface or if the system changes the

hardware SPI disable to GPIO mode and prevent MISO and MOSI from floating (i.e. output mode or input pull low) before entering standby mode, R1 and R2 are not needed. Adding R1 and R2 does not affect the connection

 Generalplus Technology Inc.

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AN0176 GPR25L/GPR26L Series Jul. 06, 2016 SPI FLASH Application Notes between SPI interfaces. Master IC

SPI Device

CSB

CSB

SCK

SCK

MISO

SO

MOSI

SI

GPxxxxx

GPR25Lxxx/ GPR26Lxxx

R1 R2 100K 100K

CONCLUSION 1.

Hardware and Software Protection Mode (a) Hardware Protection Mode must satisfy the following two conditions to enter hardware protection mode: WP# pin signal is low and SRWD sets to 1.

Either one is not met, the system will enter software

protection mode. (b) Hardware Protection Mode will protect all Memory areas and Status Registers.

Software Protection

Mode allows writing Status Register and the protected memory area is defined by the BP0 ~ BP3 of status register. (c) In Software Protection mode, if Status register’s BP0 ~ BP3 are all “0”, memory is not written-protected.

2.

Deep Power Down Mode (a). To avoid invalid command to SPI FLASH under Deep Power Down Mode while the master IC is being initialized, we recommend users issue SPI FLASH the F_SPI_GetID command (Get the FLASH ID via SPI interface) during master IC’s initialization to see whether SPI FLASH data can be read correctly. If not, the RDP instruction must be issued to wake SPI FLASH up from Deep Power-Down Mode.

3.

Standby Mode (a) When SPI FLASH is in standby mode or deep power down mode, its SI pin will be in input floating. Users must ensure if both MISO and MOSI pins on the master IC are in non-floating condition. Otherwise, there might be some current drain leakage occurred and furthermore, an increase of standby current will be yielded. (b) If the SPI interface is controlled by hardware or if there are some other factors making MISO or MOSI to floating state, a 100K-Ohm pull-low resistor can be added to the floating pin to stabilize the standby current.

 Generalplus Technology Inc.

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