Software Nir

Transactional

Memory Dan

Shavit*

MIT

Touitou

and

Tel-Aviv

Tel-Aviv

University

by

Abstract

University

constructing

classes

blockirag [7, 15, 14]. As we learn

from

chroni~ation signing

highly

isting of

a

literature,

is

flexibility

greatly

concurrent

hardware

Buildktg

inflexible

on

chronization

for

supporting

synchronization

can

of

be

Herlihy

provide

a general

Empirical

all

a k-word

evidence

chitectures the

concurrent

shows

that

lock-free

translation

and

outperforms

Herlihy’s

numbers

of processors.

software-transactional

always in

translation

based

the

and

to

a Load.

unlike

most

by

employing

operating

proposed

Barnes

style

protocols,

pol-

language

they

1

tency

Introduction

adding

are

able

using

protocol.

can

, and

or soon on the

for

to

level

a single

algorithms

the

of

word, imprac-

problem

on

machines

Herlihy

and

hardware

to

can

trans-

associative

to the

support

cache

a flexible

cache

consistency transactional

operations.

be written

Moss

solution:

a specialized changes

of provid-

existing

support.

synchronization

operation

executed

which

current

concurrent

primitives

minor

writing

chronization

[18]

operations operation

system

By

several

for

of the

an ingenious

memory.

making

helping”

icy.

most

to overcome

programming

and

Heap

Corn pare&Swap

support

[7] suggested

efficient

actional

of our

lists net-

Fetch&Complement

of

Rappoport’s

highly

on

counting

future.

ing

have

the

of

on two

compression

a three-word

of these near

simpro-

a Corn pare&Swap path

Linked/Store-Conditional

greatly

data-structures

combination

and

architectures

in the

[16]

for sufficiently

use

non-

flexibil-

concurrent

operation,

Unfortunately,

Bershad

of Barnes,

parallel

using

more.

operations

use

S pi ice

which

be developed

making

ar-

[2]

are

literature,

non-blocking

which

a special

that

the

non-blocking

the

[22]

implemented

tical

based

are

Pu

[5]

from

designing

Fetch&I nc, Israeli

translating

efficiency

“recursive

of

implementations

synchronization

of

Anderson’s

many a

STM

and uses

and be

the

task

Examples

ones

style

to the

is that

on a costly

works

outperforms

method key

approach

it is not

offer

multiprocessor

method

The

which

STM-transaction.

methods

large

methods,

our

for

the

words,

syn-

only

choosing

Massalin

software

use

lock-free

on simulated

the

we

using

method

compare&swap

collected

single

non-blocking,

We

to

grams.

programming

machines

implementations

on implementing

is

ex-

a

novel

in

plifies

level

Moss,

ity

de-

the

on

a

operation.

highly

object

of

transactional and

STM

existing

Load.Linked/Store.Conditional sequential

on

transactional

operations. on

best

(STM),

flexible

implemented

at

based

memory

syn-

task

operation

hardware

transactional

method

is

itional

the

choosing

the

Unfortunately,

and

methodology

soflwar-e

in

simplifies

programs.

Load_Linked/Store_Cond

word.

of

the

operations

of

As we learn

Any

syn-

as a transaction

an optimistic

algorithm

built

into

Unfortunately

though,

this

the

transactional

and

the

consisis block-

solution

ing. A major chines

obstacle widely

designing Given an

on the

highly the

increasingly

serious

tention

for

to

to

number gram

timing

highly and uses

they and

by

limit

anomalies

of

(possibly

modern

means

and

critical eliminating

make

critical

is

the

a multiprocessor sections

its

transactional

supports

flexible

face

clear

f0cu5

memory

pro-

altogether)

tions

which

This

class

Though

on

access

we cannot

and

processor

failures.

most

of in the

aim

known

the

memto todays in the

transactional

that

sequence

the

for

resiliency

a software

transactions,

a pre-determined

primitives

that

transactional

of applicability

of

static

includes

chronization

and

introduce

design

of synchroniza-

machines,

implement.ati0n9

support

a novel

software

in terms among

anomalies

that

(STM),

our

advantages

We

programming

software.

portability

approach,

implementation.

memory

performance,

of tirnhg

We

the

in

overall has

to adopt based

transactional

operations

machines,

The

proposes hardware

sofiware

ory

system

decrease

paper

not

same

con-

failures. to

im-

sections

increase

but

tion

for

of critical

processor

sections

is

multiprocessor

and

programming

delay

techniques

parallelism,

interconnect,

concurrent size

in

in

structures.

unpredictable

conventional

objects

since

memory

vulnerable key

problem

data

This

ma-

of programmers and

that

that

concurrent

unsuitable,

multiprocessor

difficulty

programs

realization

we argue

plementing

to making

is the

concurrent

growing

architectures,

are

way

acceptable

and

is,

transac-

of locations. proposed

syn-

literature.

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Author:

E-mail:

shanir@theory.

lcs. rnit .edu

operation

204

a nutshell environment,

operations

clusively lContact

in

In a non-faulty

fee. Ontario

STM

is usually

ownerships Op.

on the

If a transaction

the

way

based

to ensure

on locking

memory cannot

locations capture

the

atomicity

or acquiring accessed

exby an

an ownerships

it fails,

and releases

erwise, acquired.

To

deadlocks,

which

the

guarantee for

ownerships

continue

certain

process

which

This

other

same

location

plete

its

tional

is

to

only

help

eral

has

single

transactions

key

order

to

of

attempting

is the

cooperative

this

location in

free

if

ing

the

gives,

to

com-

one

release

we

using

cific

can

by

The

raon-

cooperative

other

One

can

use

method into

to

STM

for

to

[6, 26].

The

memory

to

tions.

non-blocking

Herlihy,

in

sequential

objects

cording done ory,

to

his

by first

switching

the the

help

into

it

to the

solution

Herlihy

for

large

current

updating.

Alemany

suggested the

new

data

structure,

to

whole

improve

price

of loosing

support

making

not

object, and

the

and

all that

portability,

standard

does

not

support

[4] and

with

as our and

drawbacks

em-

its

spe-

which

are

method:

a

recursive

causes

access

structure

processes

a disjoint

part

using

of

to

help

of the

data

ever,

in many

cases

since

have

to

will

have

to first

P‘s

operation

help

to

On

[20]

b, help

sys-

Q,

will

then

Q,

likely

other

hand,

and

fail.

for

again

P,

Moreover,

it,

when

also

the

P

and

location

after

b will

only HOW-

change

read

waiting

requesting

to

to

likely

help

P.

executes

the P

restart.

only

the

P

transaction,

a and

help

find

if

STM

release

have

most

P,

processes

as an

not have

on system

help

and

not

already

processes

some

coopera-

a

in

any

P has

ac-

redundantly

P. the

a will

the

the

pare&Swap

method

All

the

operation. will

P

a 2-word that

operation

own

P’s Compare&Swap

retry.

b, all

its

its

but

helped

Assume to

co-

fail

executes

b.

Q complete

11 after

of

nevertheless

which

on

level

percentage

b. According

continues

Q changed

will

P

are

a and

owns

helps

b and

transaction operations

they

locations

P first

acquires

quired

since

Q already

method,

Compare&Swap

the

a high

a process

on

process

case

con-

operating

assumptions

example

on

Compare&Swap

contention

for

k-word fail

“helped,”

k-word

then

ap-

LaMarca

general

tive

not

processes.

memory

a suitable

the

by

a set of strong

is

operations.

provide

of this

Ac-

of mem-

like

Felten

efficiency

’s

tentatively

atomic

and

the

at

version

does

of locking

tem

new

thus

by other Take

of

structure block

are

Compare&Swap

Herlihy

ones.

allocated

structures

proach

as

transformation

a data

’s method

data

loca-

guarantees

the

has

mostly

generate

other

of Load_ Linked/Store_Conditional

Unfortunately,

a

Com-

desired

concurrent

a new

on

to

k-word

sequel

updating

into

changes

pointer

the

non-blocking

methodology,

changes

the

a general

method

transactional

which

operative

succeed. in

offer

which

STM’S

and

of

transactional

of

implementation

to

to

copying

making

the

(referred first

approach

as an atomic

always

general

frequently

processes

operations

implementations

caching

2) on

[19]

streamlined

Compare&Swap

However,

translation

method

which

Unlike

concurrent

use

Figure

STM will

[15]

was the

the

collection

them (see

transaction

method),

object

on

any

performing transaction

The

highly

is straightforward:

implement

object,

some

based

approach to

a general

and

implemen-

and

.

major

is done

Barnes

structure.

Translation

sequential

ones

pare&Swap

that

provide

translating

non-blocking

shared

Lock-free

this

Rappoport

a clean k-word

two

based

and

needs

the lock-

by

call

“helping”

Sequential

STM

and

by Israeli

the

have

our

it helps

on specific

method,

both

approach

Though

are vague

achieving

a process

operation, chain.

paper

to

caching

process

cooperative

suggest,

the

by another own

executing

key

whenever

Prakash

implementation

overcome

redundant-helping.

1.2

in

of a non-blocking

results

update

method

its

a recent the

the The

Load-Linked/Store_Conditional

pirical

sev-

a location

which

details, using

in

locks.

dependency

and

implementation

need

among

complete the

the

behavior

locked

along

Shasha,

tation

transacone

to

involved

releasing

already

process

capture

the

and

recursively

the

Turek,

Moreover,

help

a location

to

out,

a location

policy

of [6, 26]

methodology,

coordination

to

helping

resilient

we must

feature

transaction.

overhead

a “reactive”

of

The

owner

the

non-blocking

even

to

locations

the

swapped

trying

the

eliminate

In order

a “helping”

owner

in

order.

key,

operation

by acquiring

delayed,

are

of their the

environment,

been

Oth-

ownerships

first

completes

by

the

the

is done

a faulty

which

help

avoid

must

increasing

achieved

is that

its

employing

it

transaction.

approach

one

transaction

transactions

own

effectively

in

every

acquired.

frees

transactions

in some

executes

crashed.

forcing

static

liveness

that

already

Op and

liveness,

needed

ensuring

make

or

the ownerships

it succeeds in executing

Finally, value

The

The

P.

will

if

to

processes

processes Q hasn’t

of b in its

2-word fail

own

Comacquire

waiting

for

waiting

for b will

changed

b, P will

cache.

behavior. To overcome in

[6],

the A

whole

limitations hk

object

similar

and

approach

Shasha,

and

“simulates”

vate

memory, the

in the

stores rest arts the

the

cache new

from

k-word

a location but

writing

process

uses

atomic

operation

memory

update.

values the

in the

beginning.

Read-Modify-write

disjoint

to the for

Barnes,

is done an

this

memory. Barnes

To make ceptable,

Turek,

its

which

the

checks

is the

case,

Otherwise, suggested

by locking

has

the

the

Results

techniques Parallel We

val-

when

(see

Section

found

blocking

process

method periments

order

205

the

cited

translation

to reduce

the

system

5) the

stable

above.

We

on

use

a simulated

accessing

translation and

the show

that

acone

(non-faulty).

We

comparison of

well

Alewife

machine, the

method

cooperative

the

methods overhead

the

of

translation

accepted

Proteus

[8, 9].

shared-memory in

stable

experimental conditions

Simulator

that

performance

is

first

under

Hardware

concurrency

to implement

needs

pay

distributed

value

operation

in ascending

sequential-to-non-blocking

performance

k-word the

the

to

private

if the

to the

Empirical

one

present

pri-

is done

non-blocking

are equivalent If

updating.

time

into

Our

by

in

first

1.3

copying

a process

updating the

Barnes,

avoids

proposed

According of

’s method, that

independently

execution

the

Write

the

concurrent

memory

Then,

Read-Modifyin

allows

i.e reading

ues contained read

method,

[26].

the

shared

memory.

of Iferiihy

caching

was

Prakash

first

from

the

introduced

object

[1] cache-coherent as

the

grows,

outperforms method.

in general

STM

potentiid the both

Unfortunately, and

other

for

STM

non-

Herlihg’s our

non-blocking

ex-

Dequeueo BeginTransaction DeletedItem G Read_transactional( Hesd) if DeletedItem Q Null ReturnedValue = Empty else Write-transactional( Hesd,DeletedItem+ if DeletedItem-+Next n Null Write-transactional( ’Ml, Null) ReturnedValue n DeletedItem+Value EndTransaction end Dequeue

k.word_C&S(Size,

DataSetlJ,OldH,

for

i=l

to

if

Size

do

Read_transactional

techniques

are

methods In ible

A Non

inferior

such

architecture

I:

to

summary,

similar

STM

shared

and

improved

section

objects,

for

i=l

to

Size

mentation

and

Finally,

in

and

ReturnedValue

for

design

which

ensures

the

lock-based a shared

package

software

transactional

standard

properties

in non-faulty

in

ones.

of the

our

concur-

faulty

The

our

A

begin

variant is

by

of the

a finite

transactional

sequence

the transactional

memory

of

local

and

memory,

of [16]. shared

A

a

- reads

a local

the

value

memory

of

machine

a shared

location

The

data

set of

a transaction

accessed

by the

structions.

Any

cessfully, other

– stores location.

in

of the

which

case For

of a doubly

returns A

dequeued

k-word

proposed

The

k-word

two

cessful

values

that

case,

memory turns A

item

and

New

the

1 may

transaction

as in the

stores

a C&S-Success

are

data set’s

transaction

Figure set,

the

checks

New value,

its

size.

equivalent

size

A suc-

a finite

implementation the

old. into

otherwise

In

try

the

the

set,

set

will

and

focus

on

supports

of the

in

the

in

Figure

known

literature.

Dequeue

that

could

2 is an procedure

in

(but

not

in

one

whole

cannot

and

with

system.

An

be swapped

implemented fail

forever,

if

out

transac-

order

However,

if pro(as when

used

only

can be made

since the

the

is non-blocking

in different

list).

if

implies

successfully

if it

implementation during

terminates

the

repeatedly

non-blocking,

swapped

same

terminate

hardware

linked

which

successfully

non-blocking

the

tolerant,

locations

their

is

will

theory

process

by a process

a process

The

two

if any

It

necessarily

times.

a doubly

Our

(1)

data

that

terminates

of attempts

transactions,

3

be

data

most

transaction

is swap

to write

updating

never

while

transaction)

assumption

of [16]

will

the

we

transaction

transaction

(not

number

many

tolerant

includes

of attempts.

process

after

static

paper

in

thus

a deterministic

the

operations

of some

dtierent

is repeatedly

whether

to

values

2 is

number

STM

tions

and

is wait-free

the

execution

some

cesses

(3)

memory

that

can

be stored

This

implementation

a possibly

under

transaction

and

as parameters

inputs

transaction,

executes

infinitely

successfully

value.

data

the

be performed

or an Empty

of the

to

~from

terminates

memory

transaction returns

a value

as parameters

and

atomically

gets

a transactional a class

of

a single

execution

for

swap-

process

which

of a transaction

successfully).

the it

re-

Implementation

of

Static-STM

CtYS-Fadure. sofiware which

changes action

the

in

visible

as in Figure

insuc-

form

1 is not.

a finite

that

locations

or complete

dequeuing

Compare&Swap

stored

are

transaction

gets

Old

k-word

the

ject

which

vectors

of shared fail,

trans-

order.

advance,

should

Compare&Swap

STM

after

the

which

synchronization

of a static

in Figure

register

Write-transactional

either

changes

Compare&Swap

a transaction and

its

list

the

of a local

set

and

may

example,

linked If

the

is the

among

transaction

transaction. of

transactions,

and

repeated

transaction

as a transaction. it

contents

Read-transactional

processes.

head

the

on

values

in

which

based

new

output

An

a shared

following

sequen-

real-time

a special

of the

which

repeatedly into

the

execute

order

their

is known

inputs

implementations

register.

Write.transactional

with is

set

the

the

example

into

satisfy

to

sequential

of as a procedure

static.

transaction

instructions:

Read-transactional

appear

The

data

set (2)

returns

sofiware

should

interleaving.

transaction

the

thought

performance

Memory

presenting

without

is consistent

static

which

proof.

function

We

transactions

i.e.,

actions

imple-

correctness

empirical

memory [13]:

Serializability:

runs

data

Transactional

Transaction

following

3 we describe

a sketch

tially,

evaluation.

2

2: A Static

bus

of flex-

of highly

resiliency

In Section

present

C&S-Success

EndTransaction

A tomicity: software

5 we

(DataSet~],New~])

=

k_word_C&S

end

for

a novel

provide

Section

Results

offers

STM,

Old~]

do

Wrke_transactional

non-resilient

[23].

performance

introduces

#

C& S-l%lure

Exitl’ransacti.m

Next )

in flavor.

coordination-operation

=

Transaction

standard

as queue-locks were

rent

Static

(DataSet~]])

ReturnedValue

Figure Figure

NewD)

BeginTransacti.m

transactional behaves

to its

addresses

is a thread

of primitive

operations

memory

like

a memory by means

of control to

that

memory.

(STM), that

is a shared supports

of transactions. applies Any

a finite

ob-

multiple A

implement

Memory[M],

trans-

of

206

a non-blocking a vector

transactional

sequence

implementation

We

memory,

termines

for

it.

process

Each

which

any

cell

static cent ains

TM the

Ownerships[M], in Memorg[lll],

keeps

in

the

shared

of

size

data a vector

which memory

M

stored

using in the

which

transaction a record

deowns with

StartTransaction(

input,DataSet

Initialize(Tranj

,input

Tranj

=

+ Stable

)

,DataSet

+

-.

Stable

=

return

tran,version) tran+stat.s)

version,’lkue)

False

Tranj +. Version++ if TTanj + Status =

rrm,versiOn,IsInitiatOr)

AcquireOwnerships( f;~ayi~~fl/l;h~j(

TransactiOn(Tranj,Tranj Tranj

‘hansaction(t

)

True

if

(version

#

tran-+version)

SC(tran+status, Success

(Success,

then

CalcOutput(Tranj

-+

OldValues,input))

if status

else

=

=

I?dure

Success

NewValues

return

O))

LL(tran+status) then

AgreeOldValues( return

then

(Success,

(status,failadd)

tran,version) =

CalcNewValues(tran+

UpdateMemory(tran,

version)

ReleaseOwnerships(

tran,version)

ReleaseOwnerships(

tran,version)

OldValues,tran+ NewValues)

else

Figure

if IsInitiator

3: St artTransaction

then

failtran=

Ownerships[failadd]

if failtran

=

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in

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a Figure

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Figure

19].

207

5: Ownerships

and

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ecuting

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cess saw it occupied

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property transaction

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ing location

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208

only

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5

An

Empirical

tion 5.1

Evaluation

of

Transla-

no

Doubly

Methodology

We

compared

methods ing

Colbrook

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without

and

[8].

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2048

contention

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software

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Dellarocas,

architecture

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MIT

[1].

of 6 bytes

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Brewer,

distributed-memory

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Weihl

of STIVI

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simulator

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had

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ples

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tial

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the

serve

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64

bits

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size

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for

evaluating structures.

data

structure

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bits

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of n processes

10000/n

times.

In this

change

the whole

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increments

variThe and

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benchmark state,

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counter

in

and have no built

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share

a process

tries

in par-

allocation

scenario

[10]:

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time

to atomically

acquire

a subset

size s of those resources. This is the typical of a well designed distributed data structure. of space we show only cesses atomically locations

increment

chosen

length

60.

highly

the benchmark

have

5000/n

uniformly

The

at random

benchmark

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times

queue

captures

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the

transaction

n.

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t ation

[11].

a variant In

consequently dequeues heap

this

of

used

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lier

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with

the

is probably

greatest the

this

built

directly

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a memory

we the

believe the theoretical

tations

of

[17]

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and

the 3 The

spurious

value

empty

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Load-Linked/Store-Conditional have

a random

s =

2

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behavior

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Proteus), while

access

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18]

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raeli

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[12]

2.

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will

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size

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ia rela-

size.

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to

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STM

processes

data

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value

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compare

says

STM

methods [23]

include

solution

(the

method.

backoff

manner).

Method

Compare&Swap

cooperative

and

based

All

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exclusive

Herlihy’s

to

described

based

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k-word

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imple-

non-blocking

[3] to reduce

contention.

leads us to conclude

differentiating

among

parallelism: do

not

process

at The

the

that

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performance

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parts

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price

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a time

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oj

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when

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Fortunately,

caching

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to

In both

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size

protocols

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and processes

memory

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coherence

cached

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copying

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structure.

number

in is at least

writing

and

parallelism

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concurrent

a jailing

the

cache

locking

potential

of the

and

failure

Both

exploit

software-transactional

methods

copy

However,

in

a boolean

MCS

methods

Potential

cesses

will

general

is that

stored on

transaction

the

methods:

and

could

of

benchmarks

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factors

the

its the

private

price

accessed

of

all ac-

of a

during

execution.

PowerPC Load_Linked

3.

operations. property

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Results

object

world then implemenor

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translation

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value

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memory

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than

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times. since

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size is n.

benchmark

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a heap

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simplification

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method

n processes

in

maximsl

in

a failing

Load-Linked/Store-Conditional allow

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64-bit Com pare&Swap Load&inked/Store.Conditional

Store-Conditional

from

less

proposed

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access

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value

queue

software

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parallelism

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to

above

structure

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5.2

k-word

on the

We

heap implemen-

each

couof ini-

enqueues/dequeues

as specialization

above.

two

implementations

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up-

of the

a queue

to the

ia equal

queue on a heap of size

benchmark

enqueues

is initially

2 Naturally

priority

index

limited

empty,

by

dequeues

5000/n

compared

2)

structure.

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and

enqueue/dequeue

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one

Queue

process

of

Every

array,

index

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ia not

list.

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item’s

aa

cells

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in each

if the

as in [24, 25]. Priority

the and

locations

to agree

methods

behavior For lack

which

of the

in

enqueues

benchmark

the

given

mentation

Allocation

tail

two

of processes,

Figure

not

data

are short,

allelism. Resource

of a queue

number

implemented

(given

Ber-

of parallelism,

Counting

data

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or using

data

small

of the

first

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updated

tively

a time

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tail/head

other.

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64-bit

scheme

benchmarks

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bits

a

the

each

we

[7].

synthetic

for

vary

amount

size n.

update

support

supports

as on the

methodology

four

methods

32

implemented

Load-Linked/Store_Conditional shad’s

not

in the

the

new

the

The

Instead

machines

by updating

size

The

of cells

the

the

architectures.

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contain

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of

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architecture

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head

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in

the

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n.

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dating

with

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represent

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concurrency

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machine Each

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current

for increases

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cycle/packet. The

potential

structure

Methods

number

of

is finite.

The

amount

of helping

ists

only

the

erative

209

in

methods.

by other

processes:

software-transactional In

the

cooperative

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the

implementation,

excoop-

12000,

~

1

1

8000

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1

10

20

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30

50

k-word ations

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and

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locations.

mance

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the

The

results

6.

and

the

vertical

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architecture, higher

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sors,

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the

number

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accessed

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linearly

word

updatea k-word on

the

given

in Fig-

of processors achieved.

to

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5.3

-------

------

30

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40

50

60

local

work

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performance

7,

the

STM

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causing

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Every

theoretical implemented

parison them

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and

than better

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than

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MIT

Alewife

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Workshop

processors, tended

Kluwer

version

publication,

Scalable

Academic

of

and

Machine:

Multiprocessor. on

this

Shared haa

In

ProceedMulti-

1991.

been

as MIT/LCS

E. W.

Blocking

Synchronization

cessors.

In

pression. Parallel

Primitives

Proceeding

for

of

Algorithms

and

An

submitted Memo

the

Asynchronous Jth

ACM

works.

for

[6] G.

T.E.

M.P.

pp.

Anderson. for

The shared

performance memory

List pagea

of

Performance

oj

Iesues

1 Ith

ACM

in

Non-

MultiproSymposium

Computation,

spin

multiprocessors.

Pages

on

1?25-134

and ACM,

N.

Shavit.

Vol.

Counting

41, No.

Net-

5 (September

Method

Structures on

for In

Parallel

Implementing

Proceedings

Lock-Free of the

Algorithms

and

5th

ACM

Architectures

1993.

Comon

199-208,

lock

Herlihy, of the

A

Data

[7] B,N

Bershad.

current Carnegie

ternatives

Systems,

1020-1048.

Barnes

Shared

1992. [3]

Distributed

on Shared-Memory

Proceedings

Journal

1994),

ex-

TM-454,

Symposium

Architectures,

and

1992.

Symposium

R. J. Anderson.

l?elten

of Distributed

[5] J. Aspnes,

1991.

[2]

60

A Large-

Memory

Publishers,

paper

appears

50

1990.

[4] J. Alemany,

August et al.

on Parallel

January

Principles

A. Agarwal

40

for their

comments.

References

[1]

1

30

Transaction

1(1):6-16,

and Maurice

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Benchmark

IEEE

Greg Barnes

x

Processors

Figure

helpful

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alIn

211

[6] E.A. E.

consideration

Technical

Mellon

University.

Brewer Weihl.

Practical

objects.

C.N. Proteus:

A.

lock-free

CMU-CS-91-

September

Dellarocas, A

for

Report,

183,

1991.

Colbrook,

High-Performance

con-

and

W.

Parallel-

~r-iiiza

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Queue

methodology

concurrent

data

gramming

Languages

November

1993.

for

implementing

ACM

objects. and

highly

Transactions

on

15(9):

Systems,

Pro-

745–77o,

t ation.

[16] M. [10]

K.

Chandy

Problem. guages [11]

T.H.

and InA

and

to

CM

The

Drinking

Transaction

on

6(4):632-646,

Systems,

Cormen,

duction

J. Misra.

C .E.

Leiserson

algorithms.

MIT

Programming October

and

R.L.

In

Lan-

20th

pages

1984.

Rivest.

Herlihy

and

Architectural

Philosopher

[17] IBM.

Intro-

Press.

Annual 289-5’00,

Power

[18] A. Israeli

DEC.

[13]

M.

Alpha

Herlihy

ness

system

and

condition

action pages

J.M. for

reference

manual.

Wing.

Linear&ability:

concurrent

on Programming 463-492,

July

objecte.

Languages

and

M.

Herlihy.

action pages

on Programming

124-149,

January

Languages

and

on

Notes

Verlag,

1-17.

pages

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Data

Structures.

Computer

Architecture,

1993.

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199.5’. Lecture

In

ACM

Trans-

Systems,

12(3),

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In A CM

Trans-

Systems,

13(1),

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Synchronization.

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Wait

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Springer

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Memory

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Proc.

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151-160. Performance Protocols.

Evaluation Proc.

of the 13th

of Lock-Free A CM

Sym-

Throughput

ratio of

STMf

Counter Doubly

linked

queue

queue

Table

posiwn

on

Principles

0.34 0.30 6.07 2.44 22.5 24.14 0.42 0.41

Bus Alewife Bus Alewife Bus Alewife BUS Alewife

Resource Allocation Priority

10 processors Herlihy’s Cooperative method method

other

1: Pure

implementation

of Distributed

throughput

Computing,

pages

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and M. Tuttle.

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213

0.74 0.45 58.9 12.9 85.61 59.8 2.8 1.1

1.98 1.92 1.44 1.75 1.09 1.12 1.26 1.27

ratio:

60 processors Herlihy’s Cooperative method method

STM

/ other

8.44 7.6 3.36 7.28 1.69 2.35 2.16 2.24

methods