Session 11 – Part 2 Computer Aided Engineering for Integrated Circuits
IC 752-E
Signal Integrity in Digital Systems Objective:
Basics signal integrity concepts
Outline:
1. Circuit attributes for signal integrity 2. Electrical systems 3. Interconnect modeling 4. Modeling criteria
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1. Circuits attributes for signal integrity LOGIC SWING, RISE AND FALL TIMES, CYCLE TIME V VH 01 . VLS
VLS
FGV • V •V IJ H 2 K L
H
Tc
01 . VLS
VL
t
tr
tf
1
Logic swing
VLS = VH − VL
Rise time - tr,
R|5volts . volts = S33 |T0.8volts
UVCMOS W BJT
Fall time – tf
tr = t f =
RS100 − 500 ps T80 − 200 ps
CMOS BJT
Cycle time – Tc
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Estimation of Highest Frequency of Interest Using Rise Time Fundamental frequency 1 Tc Taking 3-rd harmonic as highest frequency to be transmitted 3 f max = Tc A simplified relation the rise time and cycle time
νo =
Tc = 10tr
yields f max =
Example:
tr = 100 p sec
⇒
0.3 Tc . f max =
0.3 = 3 GHz 100 ⋅10−12
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Characterization of logic circuits (terminal properties) Static:
transfer curve (transfer characteristic) VDD=const
VIN
VOUT
VSS=const
The transfer curve is used to determine logic swing switching threshold noise tolerances noise margins noise immunities
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A prototypical transfer curve (steady state response) *-“UNITY GAIN” Points (slope = -1)
NML VOUT
NMH Switching Threshold Voltage
VT
NTL
NTH
VINL
NTH
L
VINH
NM H
- noise tolerance (sensitivity);
Noise immunity (NI):
NI H
L
=
NTH
L
VIN
- noise margin
L
VLS 5
Dynamic characterization Transient response: VIN and VOUT are transitioning between "high" and "low " levels VDD=const
VIN
VOUT
VSS=const
yielding: a) gate delay (internal delay) b) dynamic noise tolerance
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a) Definition of gate delay, t D , (aka internal delay) VIN
1 VINL + VLSIN 2 t
tD2
t D1 VOUT 1 L VOUT + VLSOUT 2
t
tD =
1 2
bt
D1
+ tD 2
g
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b) Dynamic noise tolerance (DNT) PA
Forbidden Area
NTL NM L
Area of safe operation PW
The DNT curves are generated using circuit simulation with perturbing pulses A[V]
PA PW
0
tr
PW-tr
t
added to the input signal. The DNT are determined via receiver characterization or circuit simulation.
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Dynamic characterization of logic circuits Dynamic noise tolerance
⇒
for receivers
Driving capability
⇒
for drivers
determined through study of driver-line interaction via circuit simulation characterization Driver power (current ) demand (needed for estimation of switching perturbations) - determined via circuit simulation characterization
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2. Electrical Systems 1. Signal distribution system Problems: signal delay signal distortion via coupling noise switching noise reflections losses (causing attenuation and dispersion) 2. Power and ground distribution system Problems: DC voltage drop switching noise 3. Externally coupled systems:
3. Interconnect Modeling Signal interconnections finite impedance low currents components
(40-70 Ω )
traces on-chip and bonds (WB, TAB, FC) conductors on chip carriers and connections (pins, SMT, balls) PWB conductors connectors Power and ground connections very low impedance ( mΩ, µΩ ) - lower than better higher currents ( mA, A ) components traces on-chip and bonds conducting plates in packages and boards
Coupling: capacitive inductive Technological trends - effects of scaling increased capacitive coupling increased importance of process variations decreased noise immunity decreased reliability (electromigration), yield (contamination effects)
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Qualitative discussion of interconnect behavior General comments on inductive effects Loop A
Loop B
I(t)
Magnetic field strength (and the flux) is proportional to loop current. A fraction of the magnetic flux from the loop A encompasses the loop B. Voltage induced in the loop B is proportional to the rate of change of flux in the loop A. Ground planes keep the loops small and local thus reducing inductive coupling. Inductive coupling reaches farther (encompasses more conductors) than capacitive coupling, which typically is more localized and decays rapidly with the distance.
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Effect of backplane Removed ground plane
Ground (backplane) included
G E (t )
G E (t )
G H (t )
G H (t )
The resistive losses in the substrate are approximated by
bg
tan δ =
1
ωε r ε o ρ
Depending on frequency and resistivity the substrate may behave as a conductor or a dielectric and may determine various signal propagation modes yielding various velocities of signal propagation.
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h
Results of approximate analysis Idealized structure
Graphical representation of results
Signal line ( ρ = 0 )
f [ MHz ]
x 106
Oxide ( ρ1 = ∞ )
b1
⊗ b2
Silicon ( ρ 2 - finite)
y
SkinEffect Mode
103
Slow-wave Mode
100
Ground plane ( ρ = 0 )
Quasi- TEM Mode
10−3
100
105
ρ 2 [ Ωcm ]
Example for: b1 = 1µm, b2 = 400µm (Grabinski, 1991).
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Capacitive coupling is important Example of prototypical results for fixed distance to the ground ( ≈ 2µm ) C [ pF / cm ]
5
Ct
CG 0
CG - capacitance to the ground, Ct - total capacitance
CC Conductor width [cm] 5
Cc - coupling capacitance (to the neighbor)
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Trends Increasing number of layers is needed due to chip complexity. Lines are longer and require higher aspect ratio to cope with space and attenuation restriction - consequently they exhibit more crosstalk. Processing variations are more important because lines are very tight and narrower. Hierarchical wiring is needed: RC models for lower levels, TL for higher levels. Skin effect might be important on higher level interconnects 2 δ = σ ≈ 2µm for copper at 1 GHz. Skin depth: ωρµ ;
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Example of effects caused by interconnect geometry scaling by a factor of 2 and a reduction of supply voltage from 2.5 [V] to 1.8 [V]. Geometry Base technology:
Scaled technology:
W = 0.9µm , S = 0.9µm , T = 0.9µm , kc = 0.53 W = 0.45µm , S = 0.45µm , T = 0.73µm , kc = 0.72 .
Typical circuit noise immunity: Base technology:
Scaled technology:
mb650 − 1500g mV r / 2.5 V mb650 − 1000g mV r / 18. V
b g yields b36 − 56g% of V
yields 24 − 60 % of VDD DD
.
Typical relative signal coupled noise Base technology:
Scaled technology:
mb500 − 700g mV r / 2.5 V mb700 − 800g mV r / 18. V
b g yields b38 − 45g% of V
yields 20 − 28 % of VDD DD
.
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4. Modeling Criteria for Signal Interconnections (based on single line analysis) Schematic of a line D
0
x
+ VA -
Basic relation used in derivation:
+ VB -
λ=v
2π
ω
Frequency domain criteria are based on comparison of line length to minimum signal wavelength as determined by the higher frequency signal to be transmitted through the interconnecting line.
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Simplified criteria tr ≥ 100 tD t 4 < r < 100 tD tr ≤ 4 tD
- ideal wire - lumped RC - transmission line
Alternative criteria (rule of thumb used by some designers): If
tr > 2.5t D
use lumped model
If
tr > 2.5t D
use transmission line model
A useful relation to estimate time of flight:
t D = D Ac = Dτ ; τ ≈ 333 . ε r ps / cm .
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Exercise Determine model required for the interconnect of geometry given below Dimensions are given in mils 1
εr1=1
0.4
2
εr2=9
(Al2O3)
Assume rise time tr = 100 ps and consider two cases: D = 60 mils a) interconnect on chip carrier where D = 25 cm . b) interconnect on a board where
