Sequential Circuits

z Sequential Circuits

z Circuits with Feedback

y

Simple circuits with feedback

y

Outputs = f(inputs, past inputs, past outputs)

y

Latches

y

Basis for building "memory" into logic circuits

y

Edge-triggered flip-flops

y

Door combination lock is an example of a sequential circuit

z Timing Methodologies

x

y

Cascading flip-flops for proper operation

y

Clock skew

x

x

Combination storage elements are also memory equal

reset

value C1

Metastability and synchronization

C2

C3 mux

multiplexer

z Basic Registers y

State is an "output" and an "input" to combinational logic

new

z Asynchronous Inputs y

State is memory

comb. logic

control

state

comparator

equal

open/closed

CS 150 - Spring 2001 - Sequential Logic - 1

CS 150 - Spring 2001 - Sequential Logic - 2

Circuits with Feedback

Simplest Circuits with Feedback

z How to control feedback?

z Two inverters form a static memory cell

y

clock

Shift registers

What stops values from cycling around endlessly

Will hold value as long as it has power applied

y

"1" X1

Z1

X2

"stored value"

Z2

switching

network

"0"

Xn

Zn

z How to get a new value into the memory cell? y

Selectively break feedback path

y

Load new value into cell

"data" CS 150 - Spring 2001 - Sequential Logic - 3

"stored value"

CS 150 - Spring 2001 - Sequential Logic - 4

Memory with Cross-coupled Gates

Timing Behavior

z Cross-coupled NOR gates y

"remember"

"load"

R

Q

Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R

Q'

S

Q

Q R S

S

Q'

z Cross-coupled NAND gates y

Reset

Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) S' Q

Q

S'

Hold

Set

Reset

Set

R S Q

R' R' CS 150 - Spring 2001 - Sequential Logic - 5

Q'

\Q

CS 150 - Spring 2001 - Sequential Logic - 6

100

Race

State Behavior of R-S latch

Theoretical R-S Latch Behavior

z Truth table of R-S latch behavior

S 0 0 1 1

R 0 1 0 1

Q Q' 01

Q hold 0 1 unstable

Q Q' 00

y

Q Q' 11

States: possible values Transitions: changes based on inputs

z Ambiguously returns to state 0-1 or 1-0

SR=00 SR=01

SR=10

SR=01

Q Q' 01

SR=00

SR=01

SR=10

Q Q' 10

SR=11 Q Q' SR=11 0 0 SR=11

S 0 0 0 0 1 1 1 1

SR=00 SR=10

SR=00

R

Q

S

Q'

R 0 0 1 1 0 0 1 1

Q(t) 0 1 0 1 0 1 0 1

CS 150 - Spring 2001 - Sequential Logic - 9

y

Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored

Set

SR=10

Q Q' 11

Q(t)

Q(t+ )

S R

Q(t+ ) 0 hold 1 0 reset 0 1 set 1 X not allowed X

S Q(t)

0

0

X

1

1

0

X

1

R characteristic equation Q(t+ ) = S + R Q(t)

CS 150 - Spring 2001 - Sequential Logic - 10

Gated R-S Latch z Control when R and S inputs matter

SR=10 SR=11 Q Q' SR=11 0 0 SR=11 SR=00 SR=00 SR=11

z Break feedback path

One of R or S usually changes first

Or non-deterministic transition

SR=01

SR=00 SR=10

R-S Latch Analysis

z Very difficult to observe R-S latch in the 1-1 state

A so-called "race condition"

Q Q' 10

CS 150 - Spring 2001 - Sequential Logic - 8

Observed R-S Latch Behavior

y

SR=01

SR=01

possible oscillation between states 00 and 11

CS 150 - Spring 2001 - Sequential Logic - 7

y

Q Q' 01

z State Diagram

y

y

SR=10

SR=00 SR=01

Q Q' 10

Clocks

R

R' enable' S'

S 100

S' R' enable' Q Q'

Reset

Q Q'

z Used to keep time y

Wait long enough for inputs (R' and S') to settle

y

Then allow to have effect on value stored

z Clocks are regular periodic signals y y

Period (time between ticks) Duty-cycle (time clock is high between ticks - expressed as % of period)

duty cycle (in this case, 50%)

period CS 150 - Spring 2001 - Sequential Logic - 11

CS 150 - Spring 2001 - Sequential Logic - 12

Clocks (contd)

Cascading Latches

z Controlling an R-S latch with a clock

z Connect output of one latch to input of another

y

Can't let R and S change while clock is active (allowing R and S to pass)

z How to stop changes from racing through chain?

y

Only have half of clock period for signal changes to propagate

y

Signals must be stable for the other half of clock period

y

Need to control flow of data from one latch to the next

y

Advance from one latch per clock period

y

Worry about logic between latches (arrows) that is too fast

R

R'

Q

clock' R

R

Q'

R

Q'

S

S

Q

S

Q

Q' S'

S

stable changing stable changing stable R'

and

S'

clock

clock

CS 150 - Spring 2001 - Sequential Logic - 13

CS 150 - Spring 2001 - Sequential Logic - 14

Master-Slave Structure

The 1s Catching Problem

z Break flow by alternating clocks (like an air-lock)

z In first R-S stage of master-slave FF

y

Use positive clock to latch inputs into one R-S latch

y

Use negative clock to change outputs with another R-S latch

y

y

z View pair as one basic unit y

master-slave flip-flop

y

twice as much logic

y

0-1-0 glitch on R or S while clock is high "caught" by master stage Leads to constraints on logic to be hazard-free master stage

1s

output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops

Set

R

Q'

S

S

Q

P'

R

Q'

S

Q

P

catch CLK

S

slave stage

master stage

Reset

slave stage

R

R P' R

R

Q'

S

S

Q

R

Q'

CLK

S

Q

P'

Master

P

P

Outputs

Q

CLK

Slave Outputs

Q'

CS 150 - Spring 2001 - Sequential Logic - 15

CS 150 - Spring 2001 - Sequential Logic - 16

D Flip-Flop

Edge-Triggered Flip-Flops

z Make S and R complements of each other y y

y

y

z More efficient solution: only 6 gates

Eliminates 1s catching problem

y

Can't just hold previous value (must have new value ready every clock period)

sensitive to inputs only near edge of clock signal (not while high) D

D holds D' when clock goes low

Value of D just before clock goes low is what is stored in flipflop

negative edge-triggered D flip-flop (D-FF)

0

4-5 gate delays

R

Can make R-S flip-flop by adding logic to make D = S + R' Q

Q must respect setup and hold time constraints to successfully

Clk=1 slave stage

master stage

capture input Q

P' R

Q'

S

Q

R

Q'

S

Q

S

Q'

0

D

Q

holds D when

P

clock goes low

D

CLK

D

CS 150 - Spring 2001 - Sequential Logic - 17

characteristic equation Q(t+1) = D

10 gates

CS 150 - Spring 2001 - Sequential Logic - 18

Edge-Triggered Flip-Flops (contd)

Edge-Triggered Flip-Flops (contd)

z Step-by-step analysis D

z Positive edge-triggered D

D

Inputs sampled on rising edge; outputs change after rising edge

y

D

z Negative edge-triggered flip-flops D

D

R

R

Q

Clk=0

100

Clk=0 S

Inputs sampled on falling edge; outputs change after falling edge

y

Q D CLK

S D

D

Qpos

positive edge-triggered FF

Qpos' Qneg

D

D

new D new D

D

negative edge-triggered FF

Qneg'

old D

when clock is low when clock goes high-to-low data is held data is latched CS 150 - Spring 2001 - Sequential Logic - 19

CS 150 - Spring 2001 - Sequential Logic - 20

Timing Methodologies

Timing Methodologies (contd)

z Rules for interconnecting components and clocks

z Definition of terms

Guarantee proper operation of system when strictly followed

y

z Approach depends on building blocks used for memory elements

y

y

y

y

hold time: minimum time after the clocking event until which the input must remain stable (Th)

Many custom integrated circuits focus on level-sensitive latches

(1) Correct inputs, with respect to time, are provided to the flipflops

y

setup time: minimum time before the clocking event by which the input must be stable (Tsu)

y

Found in programmable logic devices

z Basic rules for correct timing: y

change; can be rising or falling edge, or high or low level

Focus on systems with edge-triggered flip-flops x

clock: periodic event, causes state of memory element to

(2) No flip-flop changes state more than once per clocking event

data

Tsu Th

D Q

D Q

input clock

clock stable changing

there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

CS 150 - Spring 2001 - Sequential Logic - 21

data clock CS 150 - Spring 2001 - Sequential Logic - 22

Comparison of Latches and Flip-Flops Comparison of Latches and Flip-Flops

D

Q

CLK positive edge-triggered flip-flop

(contd)

Type

When inputs are sampled When output is valid

unclocked

always

propagation delay from input change

clock high

propagation delay from input change

(Tsu/Th around falling

or clock edge (whichever is later)

latch

D

level-sensitive CLK

latch

edge of clock) master-slave

Qedge

flip-flop D

G

Q

Qlatch

negative

CLK transparent (level-sensitive) latch

clock high

propagation delay from falling edge

(Tsu/Th around falling

of clock

edge of clock) clock hi-to-lo transition

propagation delay from falling edge

edge-triggered

(Tsu/Th around falling

of clock

flip-flop

edge of clock)

behavior is the same unless input changes while the clock is high CS 150 - Spring 2001 - Sequential Logic - 23

CS 150 - Spring 2001 - Sequential Logic - 24

Typical Timing Specifications

Cascading Edge-triggered Flip-Flops

z Positive edge-triggered D flip-flop

z Shift register

y

Setup and hold times

y

New value goes into first stage

y

Minimum clock width

y

While previous value of first stage goes into second stage

y

Propagation delays (low to high, high to low, max and typical)

y

Consider setup/hold/propagation delays (prop must be > hold)

D

Tsu

Th

20ns

5ns

CLK

Tsu

Th

20ns

5ns

IN

Tw 25ns

Q0

D Q

Q1

OUT

CLK

Tplh

100

Tphl

25ns

Q

D Q

13ns

40ns

IN

25ns

Q0 Q1 CLK

all measurements are made from the clocking event that is, the rising edge of the clock

CS 150 - Spring 2001 - Sequential Logic - 25

CS 150 - Spring 2001 - Sequential Logic - 26

Cascading Edge-triggered Flip-Flops (contd)

Clock Skew

z Why this works

z The problem

y

Propagation delays exceed hold times

y

Clock width constraint exceeds setup time

y

This guarantees following stage will latch current value

y

determined by all storage elements at the same time y

through logic

In

y

Tsu

4ns

This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays

before it changes to new value

Tsu

Correct behavior assumes next state of all storage elements

Effect of skew on cascaded flip-flops:

timing constraints

4ns

100

guarantee proper

Q0 Tp

Tp

3ns

3ns

operation of

In

cascaded components

CLK0

distribution of the clock

CLK Th

Th

2ns

2ns

CLK1 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CS 150 - Spring 2001 - Sequential Logic - 27

Summary of Latches and Flip-Flops z Development of D-FF Level-sensitive used in custom integrated circuits x

y y

can be made with 4 switches

Edge-triggered used in programmable logic devices Good choice for data storage register

z Historically J-K FF was popular but now never used y

Similar to R-S but with 1-1 being used to toggle output

CS 150 - Spring 2001 - Sequential Logic - 28

Metastability and Asynchronous inputs z Clocked synchronous circuits y

Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q

y

Not a good choice for PALs/PLAs as it requires 2 inputs

y

Can always be implemented using D-FF

z Preset and clear inputs are highly desirable on flip-flops y

Used at start-up or to reset system to a known state CS 150 - Spring 2001 - Sequential Logic - 29

Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock)

y

E.g., master/slave, edge-triggered

z Asynchronous circuits y

Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major

(complement state) y

version of CLK0

Q1 assumes infinitely fast

y

CLK1 is a delayed

Q0

Q1

concern) y

E.g., R-S latch

z Asynchronous inputs to synchronous circuits y

Inputs can change at any time, will not meet setup/hold times

y

Dangerous, synchronous inputs are greatly preferred

y

Cannot be avoided (e.g., reset signal, memory wait, user input) CS 150 - Spring 2001 - Sequential Logic - 30

Synchronization Failure

Dealing with Synchronization Failure

z Occurs when FF input changes close to clock edge

z Probability of failure can never be reduced to 0, but it

y

FF may enter a metastable state neither a logic 0 nor 1

y

May stay in this state an indefinite amount of time

y

Is not likely in practice but has some probability

can be reduced y

logic 1

y

y

logic 0

logic 0

logic 1

(1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)

asynchronous input

small, but non-zero probability

oscilloscope traces demonstrating

that the FF output will get stuck

synchronizer failure and eventual

D

Q

D

synchronized input

Q Clk

decay to steady state

in an in-between state

CS 150 - Spring 2001 - Sequential Logic - 31

synchronous system

CS 150 - Spring 2001 - Sequential Logic - 32

Handling Asynchronous Inputs

Handling Asynchronous Inputs (contd)

z Never allow asynchronous inputs to fan-out to more

z What can go wrong?

than one flip-flop y

y

Synchronize as soon as possible and then treat as synchronous signal

Async Input

Clocked Synchronous System D Q

Synchronizer Async Input D Q

Q0

In

In is asynchronous and

Q0

D Q

fans out to D0 and D1

Q0

one FF catches the

Clock

Clock D Q

Input changes too close to clock edge (violating setup time constraint)

Q1

Q1

D Q

inconsistent state may be reached!

Clock

Clock

signal, one does not

Q1

CLK

CS 150 - Spring 2001 - Sequential Logic - 33

CS 150 - Spring 2001 - Sequential Logic - 34

Flip-Flop Features

Registers

z Reset (set state to 0) R

z Collections of flip-flops with similar controls and logic

y

Synchronous: Dnew = R' Dold (when next clock edge arrives)

y

Asynchronous: doesn't wait for clock, quick but dangerous

z Preset or set (set state to 1) S (or sometimes P) y

Synchronous: Dnew = Dold + S (when next clock edge arrives)

y

Asynchronous: doesn't wait for clock, quick but dangerous

z Both reset and preset y

Dnew = R' Dold + S

(set-dominant)

y

Dnew = R' Dold + R'S

(reset-dominant)

y

Stored values somehow related (e.g., form binary value)

y

Share clock, reset, and set lines

y

Similar logic at each stage

z Examples y

Shift registers

y

Counters

OUT1

z Selective input capability (input enable/load) LD or EN y

Multiplexer at input: Dnew = LD' Q + LD Dold

y

Load may/may not override reset/set (usually R/S have priority)

z Complementary outputs Q and Q' CS 150 - Spring 2001 - Sequential Logic - 35

OUT2

OUT3

OUT4

"0" R S

R S

R S

R S

D Q

D Q

D Q

D Q

CLK IN1

IN2

IN3

CS 150 - Spring 2001 - Sequential Logic - 36

IN4

Shift Register

Universal Shift Register

z Holds samples of input

z Holds 4 values

y

Store last 4 input values in sequence

y

Serial or parallel inputs

y

4-bit shift register:

y

Serial or parallel outputs

y

Permits shift left or right

y

Shift in new values from left or right

OUT1

D Q

IN

OUT2

D Q

OUT3

D Q

OUT4

output clear sets the register contents and output to 0

D Q left_in left_out clear s0 s1

CLK

right_out right_in

s1 and s0 determine the shift function s0 0 0 1 1

clock

input

CS 150 - Spring 2001 - Sequential Logic - 37

s1 0 1 0 1

function hold state shift right shift left load new input

CS 150 - Spring 2001 - Sequential Logic - 38

Design of Universal Shift Register

Shift Register Application

z Consider one of the four flip-flops

z Parallel-to-serial conversion for serial transmission

y

New value at next clock cycle: parallel outputs

Nth cell to N-1th cell

to N+1th cell

Q D

CLK

parallel inputs

CLEAR

clear s0

s1

new value

1

0

0

0

0

output

0

0

1

output value of FF to left (shift right)

0

1

0

output value of FF to right (shift left)

0

1

1

input

0 1 2 3

s0 and s1 control mux serial transmission

Q[N-1] (left)

Input[N]

Q[N+1] (right)

CS 150 - Spring 2001 - Sequential Logic - 39

CS 150 - Spring 2001 - Sequential Logic - 40

Pattern Recognizer

Counters

z Combinational function of input samples

z Sequences through a fixed set of patterns

y

In this case, recognizing the pattern 1001 on the single input

y

In this case, 1000, 0100, 0010, 0001

signal

y

If one of the patterns is its initial state (by loading or set/reset)

OUT1

OUT IN

D Q

D Q

OUT2 D Q

OUT3

OUT4

D Q

CLK OUT1 IN

D Q

D Q

OUT2 D Q

OUT3 D Q

OUT4

z Mobius (or Johnson) counter y

CLK

In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 OUT1 IN

D Q

D Q

OUT2 D Q

CLK CS 150 - Spring 2001 - Sequential Logic - 41

CS 150 - Spring 2001 - Sequential Logic - 42

OUT3 D Q

OUT4

Binary Counter

Four-bit Binary Synchronous Up-Counter

z Logic between registers (not just multiplexer)

z Standard component with many applications

y

XOR decides when bit should be toggled

y

Always for low-order bit, only when first bit is true for second bit, and so on

OUT1

OUT2

OUT3

OUT4

y

Positive edge-triggered FFs w/ sync load and clear inputs

y

Parallel load data from D, C, B, A

y

Enable inputs: must be asserted to enable counting

y

RCO: ripple-carry out used for cascading counters x

high when counter is in its highest state 1111

x

implemented using an AND gate

EN D Q

D Q

D Q

(2) RCO goes high

D Q

CLK

(3) High order 4-bits are incremented

(1) Low order 4-bits = 1111

D C RCO B QD A QC LOAD QB QA CLK CLR

"1"

CS 150 - Spring 2001 - Sequential Logic - 43

CS 150 - Spring 2001 - Sequential Logic - 44

Offset Counters z Starting offset counters use of synchronous load y

e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . .

Sequential Logic Summary

"1" "0" "1" "1" "0"

z Ending offset counter comparator for ending value y

"0"

EN RCO QD D QC C QB B QA A LOAD CLK CLR

e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

z Combinations of the above (start and stop value)

y

Latch and flip-flop

y

R-S latch, R-S master/slave, D master/slave, edge-triggered D FF

z Timing methodologies y

Use of clocks

y

Cascaded FFs work because prop delays exceed hold times

y

Beware of clock skew

z Asynchronous inputs and their dangers "1" "0" "0" "0" "0"

CS 150 - Spring 2001 - Sequential Logic - 45

z Fundamental building block of circuits with state

EN RCO QD D QC C QB B QA A LOAD CLK CLR

y

Synchronizer failure: what it is and how to minimize its impact

z Basic registers y

Shift registers

y

Pattern detectors

y

Counters

CS 150 - Spring 2001 - Sequential Logic - 46