Sequential Logic

Sequential Circuits

 Sequential Circuits

 Circuits with Feedback

 Simple circuits with feedback

 Outputs = f(inputs, past inputs, past outputs)  Basis for building "memory" into logic circuits  Door combination lock is an example of a sequential circuit

 Latches  Edge-triggered flip-flops

 State is memory  State is an "output" and an "input" to combinational logic  Combination storage elements are also memory

 Timing Methodologies  Cascading flip-flops for proper operation  Clock skew

new

equal

reset

value

 Basic Registers

C1

C2

C3

multiplexer

 Shift registers  Counters

mux control

comb. logic state

comparator equal CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 1

clock

open/closed CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 2

Circuits with Feedback

Simplest Circuits with Feedback

 How to control feedback?

 Two inverters form a static memory cell  Will hold value as long as it has power applied

 What stops values from cycling around endlessly

"1" X1 X2 • • • Xn

Z1 Z2 • • • Zn

switching network

"stored value" "0"

 How to get a new value into the memory cell?  Selectively break feedback path  Load new value into cell "remember" "data"

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"load"

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Memory with Cross-coupled Gates

Timing Behavior

 Cross-coupled NOR gates  Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R

Q

S

Q'

Q

R S

 Cross-coupled NAND gates

"stored value"

Reset

 Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)

Hold

R

Q

S

Q'

Set

Reset

Set

100

R

S' R'

Q

S'

Q

S Q

R' CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 5

Q'

\Q CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 6

Race

State Behavior of R-S latch

Theoretical R-S Latch Behavior

 Truth table of R-S latch behavior

S 0 0 1 1

R 0 1 0 1

SR=10

Q Q' 0 1

Q hold 0 1 unstable

SR=00 SR=01

Q Q' 1 0

SR=01

 State Diagram

Q Q' 0 0

 States: possible values  Transitions: changes based on inputs

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 Ambiguously returns to state 0-1 or 1-0  A so-called "race condition"  Or non-deterministic transition SR=10 Q Q' 1 0

S 0 0 0 0 1 1 1 1

SR=00 SR=10

SR=10 SR=11

SR=11

Q Q' 0 0

SR=11

SR=00

SR=00

SR=10 Q Q' 1 1

 Break feedback path

 One of R or S usually changes first

SR=01

SR=11 SR=00 SR=11

R-S Latch Analysis

 Very difficult to observe R-S latch in the 1-1 state

SR=01

Q Q' 0 0

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Observed R-S Latch Behavior

Q Q' 0 1

SR=00 SR=10

SR=10

SR=11

possible oscillation between states 00 and 11

Q Q' 1 1

Q Q' 1 0

SR=11

SR=01

SR=00 SR=01

SR=01

Q Q' 0 1

R

Q

Q(t)

S

Q'

S R

R 0 0 1 1 0 0 1 1

Q(t) 0 1 0 1 0 1 0 1

Q(t+Δ) 0 hold 1 0 reset 0 1 set 1 X not allowed X

Q(t+Δ)

S

Q(t)

0

0

X

1

1

0

X

1

R characteristic equation Q(t+Δ) = S + R’ Q(t)

SR=00

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Gated R-S Latch

Clocks

 Control when R and S inputs matter

 Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored Set

R

R'

 Used to keep time Q

 Wait long enough for inputs (R' and S') to settle  Then allow to have effect on value stored

enable' Q'

S'

S

 Clocks are regular periodic signals  Period (time between ticks)

100

Reset

 Duty-cycle (time clock is high between ticks - expressed as % of period) duty cycle (in this case, 50%)

S' R' period

enable' Q Q' CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 11

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Clocks (cont’d)

Cascading Latches

 Controlling an R-S latch with a clock

 Connect output of one latch to input of another

 Can't let R and S change while clock is active (allowing R and S to pass)

 How to stop changes from racing through chain?  Need to control flow of data from one latch to the next

 Only have half of clock period for signal changes to propagate

 Advance from one latch per clock period

 Signals must be stable for the other half of clock period R

R'

 Worry about logic between latches (arrows) that is too fast

Q

clock' Q'

S'

S stable changing

stable changing

stable

R' and S'

R

R

Q'

R

Q'

S

S

Q

S

Q

clock

clock

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Master-Slave Structure

The 1s Catching Problem

 Break flow by alternating clocks (like an air-lock)

 In first R-S stage of master-slave FF

 Use positive clock to latch inputs into one R-S latch  Use negative clock to change outputs with another R-S latch

 0-1-0 glitch on R or S while clock is high "caught" by master stage  Leads to constraints on logic to be hazard-free

 View pair as one basic unit

master stage

 master-slave flip-flop  twice as much logic  output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage

Set

R

Q'

S

S

Q

P'

P

R

Q'

S

Q

CLK

R

Q'

S

S

Q

P' P

R

Q'

S

Q

CLK

Master Outputs Slave Outputs

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D Flip-Flop

Edge-Triggered Flip-Flops

 Make S and R complements of each other  Eliminates 1s catching problem  Can't just hold previous value (must have new value ready every clock period)  Value of D just before clock goes low is what is stored in flipflop  Can make R-S flip-flop by adding logic to make D = S + R' Q master stage

D

1s catch

S R CLK P P' Q Q'

slave stage

R

Reset

slave stage

R

slave stage

R

Q'

S

Q

P'

P

CLK

 sensitive to inputs only near edge of clock signal (not while high) D’

D

holds D' when clock goes low

Q'

Q'

S

Q

Q

negative edge-triggered D flip-flop (D-FF)

0 R

4-5 gate delays Q

Clk=1

R

10 gates CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 17

 More efficient solution: only 6 gates

must respect setup and hold time constraints to successfully capture input

Q’

S 0

holds D when clock goes low D

D’

characteristic equation Q(t+1) = D

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Edge-Triggered Flip-Flops (cont’d)

Edge-Triggered Flip-Flops (cont’d)

 Step-by-step analysis D’

 D = 0, Clk High D’

D

D’

1

0

R

Q

Clk=0

D’ 0

S D

D’

D0

0

D’

D

when clock is low data is held

when clock goes high-to-low data is latched

1

S D

new D new D ≠ old D

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Q

Hold state

Clk=1

S

D’

0

R

Q

Clk=0

Act as inverters

D

D’

R

D

D’

D

1

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Edge-Triggered Flip-Flops (cont’d)

Edge-Triggered Flip-Flops (cont’d)

 D = 1, Clk High

 D = 1, Clk LOW

11 →

0 D’

00 → 1D D’ 0 R

01 Act as inverters

D D’ 0

0

0→ 1

R

Q

Clk=1

Q

Clk=0 S D0

0 →0 1D

0 D’

1

S D0

1

D’

0

D

11 → 0

→

11 → 0

1 D’

0

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Edge-Triggered Flip-Flops (cont’d)  Positive edge-triggered  Inputs sampled on rising edge; outputs change after rising edge

 Negative edge-triggered flip-flops

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Negative Edge Trigger FF in Verilog module d_ff (q, q_bar, data, clk); input data, clk; output q, q_bar; reg q;

 Inputs sampled on falling edge; outputs change after falling edge

assign q_bar = ~q;

100 D CLK Qpos Qpos' Qneg Qneg'

positive edge-triggered FF negative edge-triggered FF

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always @(negedge clk) begin q hold) IN

D Q

Q0

D Q

Q1

OUT

CLK

Tphl 40ns 25ns

100 IN Q0 Q1

all measurements are made from the clocking event that is, the rising edge of the clock CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 29

CLK

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Cascading Edge-triggered Flip-Flops (cont’d)

Clock Skew

 Why this works

 The problem

 Propagation delays exceed hold times  Clock width constraint exceeds setup time  This guarantees following stage will latch current value before it changes to new value In

Tsu 4ns

Tsu 4ns

Q0

Tp 3ns

timing constraints guarantee proper operation of cascaded components

Tp 3ns

Q1

 Correct behavior assumes next state of all storage elements determined by all storage elements at the same time  Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay)  Effect of skew on cascaded flip-flops: 100

In

CLK1 is a delayed version of CLK0

Q0 Q1

assumes infinitely fast distribution of the clock

CLK Th 2ns

Th 2ns

CLK0 CLK1 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

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Summary of Latches and Flip-Flops

Flip-Flop Features

 Development of D-FF

 Reset (set state to 0): R

 Level-sensitive used in custom integrated circuits 

 Synchronous: D new = R' • D old (when next clock edge arrives)  Asynchronous: doesn't wait for clock, quick but dangerous

can be made with 4 switches

 Edge-triggered used in programmable logic devices  Good choice for data storage register

 Preset or set (set state to 10: S (or sometimes P)

 Synchronous: D new = Dold + S (when next clock edge arrives)  Asynchronous: doesn't wait for clock, quick but dangerous

 Historically J-K FF was popular but now never used  Similar to R-S but with 1-1 being used to toggle output (complement state)  Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q  Not a good choice for PLAs as it requires two inputs

 Both reset and preset

 Dnew = R' • D old + S (set-dominant)  Dnew = R' • D old + R'S (reset-dominant)

 Selective input capability (input enable/load): LD or EN

 Multiplexer at input: D new = LD' • Q + LD • D old  Load may/may not override reset/set (usually R/S have priority)

 Can always be implemented using D-FF

 Complementary outputs: Q and Q'

 Preset and clear inputs are highly desirable on flip-flops  Used at start-up or to reset system to a known state CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 33

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Registers

Shift Register

 Collections of flip-flops with similar controls and logic

 Holds samples of input

 Stored values somehow related (e.g., form binary value)  Share clock, reset, and set lines  Similar logic at each stage

 Store last 4 input values in sequence  4-bit shift register:

 Examples

OUT1

 Shift registers  Counters

OUT1

OUT2

OUT3

OUT4

"0" R S

R S

R S

R S

D Q

D Q

D Q

D Q

IN

D Q

D Q

OUT2

OUT3

D Q

CLK

CLK IN1

IN2

IN3

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IN4 CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 36

D Q

OUT4

Shift Register Verilog

Shift Register Verilog

module shift_reg (out4, out3, out2, out1, output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1;

in, clk);

always @(posedge clk) begin out4