Circuits with Feedback – Outputs = f(inputs, past inputs, past outputs) – Basis for building "memory" into logic circuits – Door combination lock is an example of a sequential circuit

• State is memory • State is an "output" and an "input" to combinational logic • Combination storage elements are also memory

Sequential Logic Review

value(4 bits) Ld1

Ld2

C1

new

Ld3

C2

mux control

C3

multiplexer

equal

comb. logic state

comparator

Material in this review is from Contemporary Logic Design by Randy Katz

equal

Digital combination lock state diagram

• •

S1 reset

closed

C1==value & new

not new i.e., no digits entered

S2 closed

C2!=value & new S3

C2==value & new

not new

closed

C3!=value & new

C3==value & new

2

Sensitive to inputs only near edge of clock signal (not while high)

States: 5 states – represent point in execution of machine – each state has outputs Transitions: 6 from state to state, 5 self transitions, 1 global – changes of state occur when clock says its ok – based on value of inputs ERR Inputs: reset, new, results of comparisons closed Output: open/closed C1!=value & new

open/closed

Edge-Triggered Flip-Flops •

•

clock

Reg: C1, C2, C3 need a clock to load value

1

•

reset

D’

D

holds D' when clock goes low

0 R

Q

Clk=1 OPEN

Q’

S

open

negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input

0 holds D when clock goes low

not new 3

D

D’

characteristic equation 4 Q(t+1) = D

1

Edge-Triggered Flip-Flops (cont’d) •

Edge-Triggered Flip-Flops (cont’d)

Step-by-step analysis D’

D’

D D’ R

D’

•

Positive edge-triggered – Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops – Inputs sampled on falling edge; outputs change after falling edge

Q

Clk=0 S

100 S

D

D

•

R

Q

Clk=0

D

D’

D CLK Qpos Qpos' Qneg Qneg'

D

new D new D ≠ old D

when clock goes high-to-low data is latched

D’ when clock is low data is held

positive edge-triggered FF negative edge-triggered FF

5

6

Timing Methodologies • •

•

Timing Methodologies (cont’d)

Rules for interconnecting components and clocks – Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements – Focus on systems with edge-triggered flip-flops • Found in programmable logic devices – Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: – (1) Correct inputs, with respect to time, are provided to the flipflops – (2) No flip-flop changes state more than once per clocking event

•

Definition of terms – clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level – setup time: minimum time before the clocking event by which the input must be stable (Tsu) – hold time: minimum time after the clocking event until which the input must remain stable (Th) Tsu Th

clock

7

data

D Q

D Q

input

there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

clock stable changing data clock

8

2

Comparison of Latches and Flip-Flops

Typical Timing Specifications •

D Q CLK

D

positive edge-triggered flip-flop

Positive edge-triggered D flip-flop – Setup and hold times – Minimum clock width – Propagation delays (low to high, high to low, max and typical)

CLK

D

Tsu Th 1.8ns 0.5ns

Tsu Th 1.8ns 0.5ns

Qedge Tw 3.3ns

CLK D Q G

Qlatch

CLK transparent (level-sensitive) latch

behavior is the same unless input changes while the clock is high

IN

D Q

•

OUT

Why this works – Propagation delays exceed hold times – Clock width constraint exceeds setup time – This guarantees following stage will latch current value before it changes to new value In

Tsu 4ns

Tsu 4ns

Q0

CLK

10

Cascading Edge-triggered Flip-Flops (cont’d)

Shift register – New value goes into first stage – While previous value of first stage goes into second stage – Consider setup/hold/propagation delays (prop must be > hold) Q0 Q1 D Q

Tphl 3.6ns 1.1ns

all measurements are made from the clocking event that is, the rising edge of the clock

9

Cascading Edge-triggered Flip-Flops •

Tplh 3.6ns 1.1ns

Q

data from 374 posedge triggered flip flop

Tp 3ns

100

Tp 3ns

timing constraints guarantee proper operation of cascaded components

Q1

IN

assumes infinitely fast distribution of the clock

Q0

CLK

Q1 CLK 11

Th 2ns

Th 2ns

12

3

Clock Skew •

Summary of Latches and Flip-Flops

The problem – Correct behavior assumes next state of all storage elements determined by all storage elements at the same time – This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic – Effect of skew on cascaded flip-flops:

•

Development of D-FF – Level-sensitive used in custom integrated circuit – Edge-triggered used in programmable logic devices – Good choice for data storage register Historically J-K FF was popular but now never used – Similar to R-S but with 1-1 being used to toggle output (complement state) – Good in old days of TTL/SSI (more complex input function: D = JQ' + K'Q – Not a good choice for PALs/PLAs as it requires 2 inputs – Can always be implemented using D-FF Preset and clear inputs are highly desirable on flip-flops – Used at start-up or to reset system to a known state

•

100 In Q0 Q1 CLK0 CLK1

CLK1 is a delayed version of CLK0 In our design we expect CLK1 and CLK0 arrive at the same time

original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

•

13

14

Dealing with Synchronization Failure •

Handling Asynchronous Inputs

Probability of failure can never be reduced to 0, but it can be reduced – (1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems – (2) use fastest possible logic technology in the synchronizer – (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)

•

Never allow asynchronous inputs to fan-out to more than one flip-flop – Synchronize as soon as possible and then treat as synchronous signal

Clocked Synchronous System Async Input

D Q

Synchronizer Q0

Async Input

D Q

D Q

Clock

Clock

asynchronous input

D

Q

D

D Q

synchronized input

Q

Q1

Clock

Clk 15

Q0

D Q

Q1

Clock 16

synchronous system

4

Registers

Handling Asynchronous Inputs (cont’d) • •

What can go wrong? – Input changes too close to clock edge (violating setup time constraint) • In

In is asynchronous and fans out to D0 and D1

Q0

one FF catches the signal, one does not

Q1

Collections of flip-flops with similar controls and logic – Stored values somehow related (e.g., form binary value) – Share clock, reset, and set lines – Similar logic at each stage Examples – Shift registers – Counters OUT1

OUT2

OUT3

OUT4

"0"

inconsistent state may be reached!

R S D Q

CLK

R S D Q

R S D Q

R S D Q

CLK 17

IN1

•

Holds samples of input – Store last 4 input values in sequence – 4-bit shift register:

OUT1 IN

D Q

D Q

OUT2 D Q

IN3

IN4

18

Universal Shift Register

Shift Register •

IN2

OUT3

Holds 4 values – Serial or parallel inputs – Serial or parallel outputs – Permits shift left or right – Load new input output

OUT4

D Q

left_in left_out clear s0 s1

CLK

right_out right_in clock

input 19

clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 0 0 1 1

s1 0 1 0 1

function hold state shift right shift left load new input 20

5

Design of Universal Shift Register •

Pattern Recognizer

Consider one of the four flip-flops – New value at next clock cycle:

• Nth cell to N-1th cell

Combinational function of input samples – In this case, recognizing the pattern 1001 on the single input signal

to N+1th cell

Q D

OUT

CLK OUT1

clear 1 0 0 0 0

s0 – 0 0 1 1

s1 – 0 1 0 1

CLEAR 0 1 2 3 s0 and s1 control mux

new value 0 output output value of FF to left (shift right) output value of FF to right (shift left) input

Q[N-1] (left)

Input[N]

D Q

IN

OUT2

D Q

OUT3

D Q

OUT4

D Q

CLK

Q[N+1] (right) 21

22

Counters •

Sequences through a fixed set of patterns – In this case, 1000, 0100, 0010, 0001 – If one of the patterns is its initial state (by loading or set/reset) OUT1

IN

D Q

D Q

OUT2

D Q

OUT3

Binary Counter • OUT4

D Q

Logic between registers (not just multiplexer) – XOR decides when bit should be toggled – Always for low-order bit, only when first bit is true for second bit, and so on

CLK

•

OUT1

Mobius (or Johnson) counter – In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 OUT1 IN

D Q

D Q

OUT2 D Q

OUT3

D Q

OUT4

OUT2 D Q

OUT3 D Q

OUT4 D Q

CLK

D Q

CLK "1" 23

24

6

State Machine Model

Offset Counters •

Starting offset counters – use of synchronous load – e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . .

•

Ending offset counter – comparator for ending value

"1"

EN

"0" "1" "1" "0"

D C B A LOAD CLK CLR

• •

RCO QD QC QB QA

Values stored in registers represent the state of the circuit Combinational logic computes: – Next state • Function of current state and inputs – Outputs • Function of current state and inputs (Mealy machine) • Function of current state only (Moore machine)

"0"

– e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

•

Combinations of the above (start and stop value)

"1"

EN

"0" "0" "0" "0"

D C B A LOAD CLK CLR

RCO QD QC QB QA

output logic

Inputs

Outputs

next state logic

25

Next State

26

Current State

Comparison of Mealy and Moore Machines State Machine Model (cont’d)

Inputs

• • • • •

•

output logic

Outputs

next state logic

Next State

States: S1, S2, ..., Sk Current State Inputs: I1, I2, ..., Im Outputs: O1, O2, ..., On Transition function: Fs(Si, Ij) Output function: Fo(Si) or Fo(Si, Ij)

•

inputs

Next State

inputs

State Clock 0

•

Mealy Machines tend to have less states – Different outputs on arcs (n^2) rather than states (n) Moore Machines are safer to use – Outputs change at clock edge (always one cycle later) – In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback Mealy Machines react faster to inputs – React in same cycle – don't need to wait for clock – In Moore machines, more logic may be necessary to decode state into outputs – more gate delays after

1

2

3

4

combinational logic for next state

reg

logic for outputs

outputs

logic for outputs combinational logic for next state

outputs

reg

5 27

state feedback

state feedback

28

7

Example: Vending Machine • • •

Example: Vending Machine (cont’d) •

Release item after 15 cents are deposited Single coin slot for dimes, nickels No change Reset

N Coin Sensor

D

Vending Machine FSM

Open

Release Mechanism

Clock 29

Example: Vending Machine (cont’d) •

present state 0¢

0¢ 5¢

N 5¢ N D

D 10¢

10¢ N+D 15¢ [open]

15¢

inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 – –

next state 0¢ 5¢ 10¢ – 5¢ 10¢ 15¢ – 10¢ 15¢ 15¢ – 15¢

Reset

S0 N

D

D

N

S4 [open]

S5 [open]

S1

S2 D S6 [open]

30

Example: Vending Machine (cont’d)

Minimize number of states - reuse states whenever possible Reset

Suitable Abstract Representation – Tabulate typical input sequences: • 3 nickels • nickel, dime • dime, nickel • two dimes – Draw state diagram: N • Inputs: N, D, reset S3 • Output: open chute – Assumptions: N • Assume N and D asserted S7 for one cycle [open] • Each state has a self loop for N = D = 0 (no coin)

• output open 0 0 0 – 0 0 0 – 0 0 0 – 1

Uniquely Encode States, binary encoding is selected present state inputs Q1 Q0 D N 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 – –

next D1 0 0 1 – 0 1 1 – 1 1 1 – 1

state D0 0 1 0 – 1 0 1 – 0 1 1 – 1

output open 0 0 0 – 0 0 0 – 0 0 0 – 1

symbolic state table 31

32

8

Example: Vending Machine (cont’d) •

Mapping to Logic

Q1

D1

0 1 1 1 D

X X X X 1 1 1 1 Q0

Q1

D0

0 0 1 1

Example: Vending Machine (cont’d)

1 0 1 1

N D

X X X X

•

Q1 Open 0 0 1 0

0 1 1 0

0 0 1 0

N D

0 1 1 1

N

X X X X

present state Q3 Q2 Q1 Q0 0 0 0 1

0 0 1 0

Q0

One-hot Encoding

Q0

0 0

1

0

D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

0 1

0

0

1 0

0

0

OPEN = Q1 Q0

inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 - -

next state D3 D2 D1 0 0 0 0 0 1 0 1 0 - - 0 0 1 0 1 0 1 0 0 - - 0 1 0 1 0 0 1 0 0 - - 1 0 0

output D0 open 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

D0 = Q0 D’ N’ D1 = Q0 N + Q1 D’ N’ D2 = Q0 D + Q1 N + Q2 D’ N’ D3 = Q1 D + Q2 D + Q2 N + Q3 OPEN = Q3

33

34

Vending Machine (cont’d) Equivalent Mealy and Moore State Diagrams

•

Moore machine Mealy machine outputs associated with transitions outputs associated with state N’ D’ + Reset

Reset

0¢ [0]

5¢ [0]

10¢ [0]

N’ D’

5¢

N’ D’/0

10¢

N’ D’/0

15¢

Reset’/1

N/0 N’ D’

D/1 N+D/1

N+D 15¢ [1]

N’ D’/0

N/0 D/0

N D

• •

0¢

N’ D’

N D

(N’ D’ + Reset)/0

Reset/0

•

OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) Implementation now looks like a synchronous Mealy machine – Common for programmable devices to have FF at end of logic

Reset’

35

36

9

Finite State Machine Optimization •

•

Algorithmic Approach to State Minimization

State Minimization – Fewer states require fewer state bits – Fewer bits require fewer logic equations Encodings: State, Inputs, Outputs – State encoding with fewer bits has fewer equations to implement • However, each may be more complex – State encoding with more bits (e.g., one-hot) has simpler equations • Complexity directly related to complexity of state diagram – Input/output encoding may or may not be under designer control

37

State Minimization Example

•

0/0 0/0 S3 0/0

S1

1/0

S0

1/0 S4 0/1

1/0

Input Sequence

Next State Present State X=0 X=1

X=0

Reset 0 1 00 01 10 11

S0 S1 S2 S3 S4 S5 S6

0 0 0 0 1 0 1

S2 S4 S6 S0 S0 S0 S0

Output X=1 0 0 0 0 0 0 0

0/0 S5 0/0

1/0

•

Input Sequence

Next State Present State X=0 X=1

X=0

Reset 0 1 00 01 10 11

S0 S1 S2 S3 S4 S5 S6

0 0 0 0 1 0 1

S1 S3 S5 S0 S0 S0 S0

( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 )

1/0 S2

•

Goal – identify and combine states that have equivalent behavior Equivalent States: – Same output – For all input combinations, states transition to same or equivalent states Algorithm Sketch – 1. Place all states in one set – 2. Initially partition set based on output behavior – 3. Successively partition resulting subsets based on next state transitions – 4. Repeat (3) until no further partitioning is required • states left in the same set are equivalent – Polynomial time procedure

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )

1/0 S6 0/1

38

Method of Successive Partitions

Sequence Detector for 010 or 110

S1 S3 S5 S0 S0 S0 S0

•

S2 S4 S6 S0 S0 S0 S0

Output X=1 0 0 0 0 0 0 0

S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6

( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) 1/0 39

40

10

Minimized FSM •

More Complex State Minimization

State minimized sequence detector for 010 or 110 Input Sequence Reset 0+1 X0 X1

Next State Present State X=0 X=1 S0 S1' S3' S4'

S1' S3' S0 S0

S1' S4' S0 S0

•

Multiple input example

Output X=0 X=1 0 0 0 1

inputs here

0 0 0 0

00

X/0

00

S4’ 0/1

10 01

1/0

S4 [1]

S3 [0] 11

10

10

1/0

S3’

01 11

present state S0 S1 S2 S3 S4 S5

11 00 01 01

11

S2 [1] 10

S1 [0]

01

10

X/0 0/0

00

S0 [1]

S0

S1’

10

00

11 01

S5 [0]

00 11

00 S0 S0 S1 S1 S0 S1

42

Minimized FSM

State Assignment Strategies

Implication Chart Method – Cross out incompatible states based on outputs – Then cross out more cells if indexed chart entries are already crossed out present state S0' S1 S2 S3'

S1

S2

S0-S1 S1-S3 S2-S2 S3-S4

S3

S4

S0-S0 S1-S1 S2-S2 S3-S5

S5 S0

S0-S1 S3-S0 S1-S4 S4-S5

S0-S1 S3-S4 S1-S0 S4-S5 S1

S1-S0 S3-S1 S2-S2 S4-S5

S2

output 1 0 1 0 1 0

symbolic state transition table

41

•

next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4 S0 S4 S5 S1 S2 S5 S4 S0 S5

00 S0' S0' S1 S1

next state 01 10 11 S1 S2 S3' S3' S1 S3' S3' S2 S0' S0' S0' S3'

•

output 1 0 1 0

•

Possible Strategies – Sequential – just number states as they appear in the state table – Random – pick random codes – One-hot – use as many state bits as there are states (bit=1 –> state) – Output – use outputs to help encode states – Heuristic – rules of thumb that seem to work in most cases No guarantee of optimality – another intractable problem

minimized state table (S0==S4) (S3==S5) S1-S1 S0-S4 S4-S0 S5-S5 S3

43

44

S4

11

Heuristics for State Assignment One-hot State Assignment • • •

•

•

Simple – Easy to encode, debug Small Logic Functions – Each state function requires only predecessor state bits as input Good for Programmable Devices – Lots of flip-flops readily available – Simple functions with small support (signals its dependent upon) Impractical for Large Machines – Too many states require too many flip-flops – Decompose FSMs into smaller pieces that can be one-hot encoded Many Slight Variations to One-hot – One-hot + all-0

•

– Group 1's in next state map I i i

•

Q a b

Q+ c c

O j k

a

b

i/j

c=i*a + i*b

i/k c

Adjacent codes to states that share a common ancestor state

– Group 1's in next state map I i k

•

Q a a

Q+ b c

O j l

i/j

b=i *a c=k*a

b

a

k/l c

Adjacent codes to states that have a common output behavior

– Group 1's in output map I i i

45

Output-Based Encoding •

Adjacent codes to states that share a common next state

Q a c

Q+ b d

O j j

j=i *a+ i *c b=i*a d=i*c

a

c i/j b

i/j

46

d

Current State Assignment Approaches

Reuse outputs as state bits - use outputs to help distinguish states – Why create new functions for state bits when output can serve as well – Fits in nicely with synchronous Mealy implementations

•

•

•

47

For tight encodings using close to the minimum number of state bits – Heuristic approaches are not even close to optimality – Used in custom chip design One-hot encoding – Easy for small state machines – Generates small equations with easy to estimate complexity – Common in FPGAs and other programmable logic Output-based encoding – Ad hoc - no tools – Most common approach taken by human designers – Yields very small circuits for most FSMs

48

12