The application of the electrical interface has been simulated using HSpice software. It demonstrated how the signal quality could be affected by the use of microstrip versus stripline traces and their associated advantages and disadvantages is discussed. Example XFI channels were assembled from the simulation results to demonstrate viability of the application.

Considerations for High Speed PCB Track Design in 10Gb/s Serial Data Transmission

Introduction This white paper describes the main considerations in the design of a PCB for the transmission of 10 Gb/s serial data. It has been written to aid the PCB designer to devise the layout for a host board for use with the Agilent 10 Gb/s HFCT-711XPD XFP LC differential serial transceiver and the electrical channel to the SerDes IC (XFI channel). Its focus is on the frequency-dependent attributes of the various components within the electrical channel. Additionally, the parametric issues of a pluggable connector are examined.

White Paper Steve Bowers and Dr Herbert Lage Applications Engineering Avago Technologies Fiber Optic Products Division

TheXFI XFIElectrical ElectricalChannel Channel The

Abstract A fundamental evaluation of a variety of approaches for designing a high-speed (10 Gb/s) serial differential electrical channel is examined. The application of the electrical interface has been simulated using HSpice software. It demonstrated how the signal quality could be affected by the use of microstrip versus stripline traces and their associated advantages and disadvantages is discussed. Example XFI channels were assembled from the simulation results to demonstrate viability of the application.

Introduction This white paper describes the main considerations in the design of a PCB for the transmission of 10 Gb/s serial data. It has been written to aid the PCB designer to devise the layout for a host board for use with the Avago 10 Gb/s HFCT-711XPD XFP LC differential serial transceiver and the electrical channel to the SerDes IC (XFI channel). Its focus is on the frequency-dependent attributes of the various components within the electrical channel. Additionally, the parametric issues of a pluggable connector are examined.

A block diagram of a typical electrical channel is Ashown block diagram of1.a This typical channel is shown in Figure is electrical a simplified electrical inchannel Figure 1. This is a simplified electrical channel within within an XFP application. The electrical an XFP application. The electrical characteristics characteristics of the data are assumed to be of XFIthe data are assumed to be XFI compliant, see the XFP compliant, see the XFP MSA (www.xfpmsa.org)MSA (www.xfpmsa.org) foron further details on an The XFI interface. for further details an XFI interface. The numbers in Table 1 relate to the position within the numbers in Table 1 relate to the position within channel: the channel: Table 1. XFI data channel details Number

Location

1-2

Channel from the IC pads to the IC I/O pins

2-3

10Gb/s data channel including vias

3-4

Channel through the pluggable connector

4-5

10Gb/s data channel including vias

5-6

Channel from the IC I/O pins to the IC pads

XFP Internal IC I/Os

XFP Internal IC I/Os

XFP pluggable connector

10 Gb/s data lines (tracks) 1

2

Figure 1. Block diagram of an electrical XFI channel

3

10 Gb/s data lines (tracks) 1

3

2 Serdes IC I/Os

10 Gb/s data lines (tracks)

Figure 1. Block diagram of an electrical XFI channel

2

4

XFP pluggable connector

5

6

the degrad channel, ie absolute ev measured d values for XFI channe

There are m integrity of 1. 2. 3. 4. 5. 6. 7. 8.

Tra Die The con Dis com Typ str Phy Da qua Tem

Here, we w analyze the digital data

Track Length Track dime properties increasing

The dielect dictates th transmissio Additional wave that t proportion constant er increases, the frequen effective er manufactu

Within the XFP MSA is an option to utilize eye opener ICs. This enables a reduction in the amount of jitter on the signal in both directions of the XFI channel. However, the interest here is in the degradation of signal quality due to the channel, ie. practical tests are necessary for an absolute evaluation of the channel. Where measured data is not yet available, the parametric values for components and parasitics within the XFI channel have been estimated. There are many factors affecting the signal integrity of high-speed data links: 1. Track dimensions 2. Dielectric material properties of the PCB 3. The physical design of the pluggable connector (effects of implementation) 4. Discontinuities between the track and component pads (reflections) 5. Type and length of track used, microstrip / strip line 6. Physical configuration of vias 7. Data pattern-dependency of the signal quality – jitter 8. Temperature dependency Here, we will examine each one in turn and analyze the associated effects on the transmitted digital data stream.

Track Length/Width and PCB Materials Track dimensions together with PCB material properties become more prohibitive with increasing frequency. The dielectric constant, er, of the PCB material dictates the effective capacitance around the transmission lines and is frequency dependent. Additionally, the velocity of an electromagnetic wave that travels through a dielectric is reduced proportionally to the square root of the dielectric constant er, ie. for a given EM wave, as er increases, the velocity decreases. Furthermore, as the frequency of the EM wave increases, the effective er of many dielectrics used for the manufacture of PCBs decreases. The group velocity of an electrical signal therefore depends on its frequency, an effect known as dispersion. However, this effect is usually small and will be ignored for the purposes of this study. The dielectric material of a PCB is generally composed of glass fiber and resin. The er is affected by the ratio of glass to resin used to make the laminate. The most common dielectric material used in high-speed data transmission is FR4. This material has a low er with a typical resin/ glass ratio of around 55%. At 5 GHz, er is about 4.2 [Ritchey 1999].

2

The losses of transmission lines are determined by the skin effect of the conductor and the absorption of electric energy by the dielectric. The skin effect confines the current flow to the surface of the conducting material, typically copper. Increasing the surface area, ie. by increasing the width of the transmission line, can mitigate the skin effect. The loss of electric energy in the dielectric is described by its loss tangent tan(d). In most digital applications up to about 1 GHz the dielectric loss is a small fraction of the loss due to the skin effect. However, since dielectric losses increase faster with frequency than skin-effect losses, they can become the dominating loss mechanism for very high data rate systems. When transmitting at frequencies of around 5 GHz or higher, the combination of trace dimension and PCB material is paramount in finding the right trade-off between low channel-loss, ie. low attenuation to maintain signal levels well above digital decision thresholds, and minimizing jitter or standing wave effects through the right amount of attenuation of unwanted reflections. For a shorter trace length at 5 GHz, the use of a lossy combination in order to introduce a small amount of additional attenuation may actually help to improve the overall XFI channel return loss.

Pluggable Connectors When using a pluggable connector, it is essential that the physical properties of the connector do not limit its use in the intended data channel. The electrical parasitics of the connector, eg. inductance, have to be included during the evaluation. The parasitic values are usually available from the manufacturer of the connector and enable the use of electrical simulation for Signal Integrity evaluation of the data channel.

PCB Layout Design and Microstrip versus Stripline Geometry A Time Domain Reflectometer can be used to evaluate discontinuities in the data track. It is critical to avoid reflections when transmitting data to ensure that only a clean signal with well defined edges and voltage levels is received. In the case of a short track length in an XFI channel transmitting at around 5 GHz, it maybe an advantage to use a PCB material that has a higher loss tangent tan (d) to help absorb reflections and hence improve signal quality1. Furthermore, the type of track used, stripline or microstrip, has both advantages and disadvantages for high-speed data transmission. See Table 2.

shorter trace length at 5 GHz, the use of a lossy combination in order to introduce a small amount of additional attenuation may actually help to improve the overall XFI channel return loss.

and optimizing signal integrity. Data Pattern-Dependency of the Signal Quality – Jitter The frequency content of the test pattern and the ‘typical’ live traffic will determine how the signal is

Table 2. Microstrip versus Stripline

Advantages

Disadvantages

Stripline

Buried track avoids surface EMI emission and improves EMI immunity.

Vias have to be used: 1) Can lead to reduced signal quality by causing reflections. 2) Can limit the track length due to narrow track width and increased dielectric losses.

Microstrip

Longer track lengths permitted; does not require vias so fewer impedance discontinuities that can impact Signal Integrity - more predictable.

Can lead to an EMI emission and immunity penalty for the channel both for the transmitting device and surrounding components - open-air emissions.

Note: 1. Reference: XFP Multisource Agreement Rev 1.0

3

The Use of Vias in High-Speed Data Transmission

Temperature dependency

The introduction of vias in to a high-speed electrical design can lead to multiple electrical reflections caused by impedance discontinuities in the data line. Additionally, the manufacturing process can be troublesome at frequencies >1 GHz to achieve the required signal quality. Other considerations are: simplifying electrical designs and optimizing signal integrity.

It is clear that materials used in the manufacture of PCBs can have differing coefficients of thermal expansion. However, the temperature range of a typical data application does not usually exceed the –40 to +85 °C limits. Over this temperature range the relative dimensional change of the PCB materials is less than 1%, and in the case of differential tracks, both tracks should be affected by the same amount. Such a small change in length of the traces should be insignificant in terms of the Signal Integrity of the XFI data channel. Similarly, for track width, the proportional change is of the same amount as the length change with temperature. Again, this is very minor with regards to the practical limits that apply to track width control in a typical manufacturing environment.

Data Pattern-Dependency of the Signal Quality – Jitter The frequency content of the test pattern and the ‘typical’ live traffic will determine how the signal is affected by the format of the data. The Synchronous Optical Network, SONET, data format typically has more content at lower frequencies than an Ethernet pattern, normalized to remove the bit rate difference. This is due to long strings of Ones and Zeroes that are allowed in the SONET format. Thus the range of frequencies that the PCB has to handle is relatively different for each of the network protocols. This can have a significant affect on the signal quality due to resonance effects and the overall frequency dependence of the data channel. It can therefore be important to check that a data channel not only works at the highest frequencies, but also does not cut off any low frequency content that could be present in SONET protocols for example. Note: The simulations within this document have utilized the PRBS 27-1 data stream. N.B. It is probable that a pattern with a lower frequency content, e.g. PRBS 223-1 would display worse results, however using this pattern would result in a much longer simulation time due to the required resolution of the waveforms, thus longer patterns were not used in the simulations.

3

Vias may experience stress caused by the expanding dielectric, due to differences in the thermal expansion coefficients of copper and FR4. This can threaten the mechanical integrity of the PCB and could lead to cracks in the vias for very thick PCBs, which may in turn manifest itself as intermittent failure [Ritchey 1999]. The most critical process step in that respect is soldering operations, which raise the temperature of the PCB to around +185°C. However, unless cracks occur during the manufacturing operations of the PCB temperature changes are not expected to affect the high-frequency properties of the XFI data channel. Hence temperature dependence will not be further discussed.

XFI Channel Simulation The XFI channel has been simulated to show how the various properties, discussed above, can influence the signal shape and quality. In this section, the XFI channel is separated into component models. The simulation tools used were Agilent Advance Design System v.2002 and Synopsis (formerly Avanti) HSpice v.2002.2.1. The schematic in Figure 2 demonstrates how the receiver section of a XFP module was modeled to enable the simulation of an XFI compliant channel. The significance of the various elements of this XFP receiver model will be discussed in some detail before we look at simulation results for a whole XFI data channel. Additional detail of the output buffer model of the XFP receiver is shown in Figure 3. As can be seen from the schematic a Current-Mode Logic (CML) buffer model has been devised in order to meet the I/O buffer specifications of the XFP MSA. The following table explains the various elements of the output buffer model shown in Figure 3:

1. Differential digital signal generator 2. 6th order Bessel filter to generate realistic analog edges and eye shapes1 3. Fine-tuning network to slow the final settling of the buffer, if required. The RC time constant used here is 4 ps. 4. Fast open-collector transistors with 50 ohm internal pull-up resistors – intrinsic switching speed approximately 10-15 ps. The current source in the “tail” determines the signal amplitude. 5. Capacitance of the die bond-pads and other parasitic capacitances. The capacitance used in this model is 0.1 pF. Note: 1. Reference: “The Art of Electronics” (Second Edition) by Paul Horowitz and Winfield Hill, Cambridge University Press, Chapter 5 “Active Filters and Oscillators”.

50 Ω Resistor

XFP

Module - lines (L ; 50 Ω ) mod Output Buffer Model

XFI Compliant Package Model

XFP - Tyco CONNECTOR

DC - blocks Figure 2. XFI channel model components

4

CML Buffer

V cc 6th order Bessel Filter 1

2

RC Eye shape fine adjustment 3

dc biasing

Pad Parasitic capacitance CML_Out +

+ 4

5 CML_Out -

+ RC time constant is 4ps

+

Figure 3. Schematic of the quantizer CML output buffer created for XFI simulation

XFP Model Components From the die pads the signal needs to pass through the IC package before it is launched onto the transmission lines inside the XFP module. Figure 4 shows the Scattering (S) parameters S11 and S12 of the preliminary quantizer IC package model that was used to account for packageinduced parasitics between the Silicon die and the quantizer SMT pin1. At this point it shall suffice to say that the package model is compliant with performance requirements of an XFI data channel. The preliminary model used here is based on an RLC-”ladder” approach that is explained in more detail later in this white paper when we will look at the influence of the receiver IC package on the Signal Integrity of a XFI channel link. A surface mounted dc-block allows the decoupling of the XFP module supply voltage from the voltages used by the Serializer/Deserializer (SerDes) IC on the host board. Figure 5 shows a schematic of the equivalent circuit for the parasitics of the 47 nF dc blocking capacitors that was used in the simulations. Note: 1. SMT: Surface Mount Technology

A Spice model of the pluggable connector, supplied by Tyco Electronics, was also inserted into the XFI channel model. The pins corresponding to the RD+/- signals were terminated with two 50 W resistors as depicted in Figure 2. 5

All other connector pins were grounded. A simulation was run where the XFP receiver model was stimulated with a 10 Gb/s PRBS (27-1) bit pattern. The differential waveforms were probed between pins RD+ and RD- of the XFP module connector (host side), the resultant eye-plot is displayed in Figure 6. Due to the complexity of the XFP connector model, simulation times tend to be long. A compact version of the model was therefore constructed in order to save processing time. The compact model is an equivalent single-line model that ignores the coupling between the pins and consequently cannot be used for connector-induced crosstalk analysis, however, it accurately describes the impedance discontinuity caused by the connector. The simulated Time-Domain Reflectometry (TDR) responses of the two connector models are shown in Figure 7. The agreement between the 2 models is satisfactory. This is also confirmed by XFI channel simulations where the resultant eye-plot together with the XFI compliant eye mask1 is shown in Figure 8. It can be seen that the eye-plot with the compact model is very comparable with the plot using the full connector model. All subsequent simulations used the compact connector model unless otherwise stated. Furthermore, the eye diagram in Figure 8 will serve as a reference for quantitative evaluations of eye closure as a function of XFI link design parameters.

The frequency content of the simulation pattern is shown in Figure 9. This is the Fourier transform of the PRBS (27-1) pattern emitted by the XFP receiver. It can be seen from this plot that frequencies above 20 GHz contribute little to the output signal produced by the receiver model. As mentioned earlier, for some data formats it can be as important to check the low frequency end of the spectrum, as it is to verify performance at the high frequency end. For the SONET data format, strings of consecutive ones and zeroes as long as 72 bits are allowed. The lowest frequency which then needs to pass the channel can be estimated according to f_low = BitRate/(2*N), where N is the maximum number of identical bits. Thus, for an OC-192 SONET data pattern, this equates to approximately 69

MHz. The low frequency cutoff of the XFI channel needs to be well below the 69 MHz in order for the link to be usable for SONET data formats. However, even for small values of the cutoff frequency, there is still an influence on Data-Dependent Jitter (DDJ) and eye-closure. The effect is most pronounced for long sequences of ones and zeroes. The R&D department of Avago has estimated the DDJ and the reduction of the inner eye height for the maximum allowed sequence of 72 identical bits. The results of these worst case calculations are depicted in Figure 10 as a function of cutoff frequency for a 10 Gb/s SONET data pattern. Note: 1. Reference: XFP Multisource Agreement, www.XFPMSA.org.

Figure 4. S11 and S21 plot of the quantizer IC package model. The model is based on an RLC “ladder” approach, which is explained in a later chapter of this white paper.

C C20 C=108 fF

L L14 L=0.6 nH R=

L L15 L=0.6 nH R=

Port P3 Num=3

Port P4 Num=4

C C23 C=47 nF

C C26 C=108 fF

Figure 5. Schematic of the parasitics for the dc blocking capacitors

6

C C25 C=108 fF

C C22 C C=11 fF C24 C=11 fF

Port P1 Num=1

Port P2 Num=2

C C21 C=47 nF

C C27 C=108 fF

r model

or, nserted

Figure 9. Frequency content of the 2 -1 PRBS bit stream emitted by the XFP receiver Figure 6. XFI channel simulation using the full connector model

A Spice model of the pluggable connector, supplied by Tyco Electronics, was also inserted into the XFI channel model. The pins corresponding to the RD+/- signals were terminated with two 50 W resistors as depicted in Figure 2. All other connector pins were grounded. A simulation was run where the XFP receiver model was stimulated with a 10 Gb/s PRBS (27-1) bit pattern. The differential waveforms were probed between pins RD+ and RD- of the XFP module connector (host side), the resultant eyeplot is displayed in Figure 6. Due to the complexity of the XFP connector model

Figure 6. XFI channel simulation full connector model simulation times tend tousing be the long.

A Spice model of the pluggable connector, supplied by Tyco Electronics, was also inserted into the XFI channel model. The pins corresponding to the RD+/- signals were terminated with two 50 W resistors as depicted in Figure 2. All other connector pins were grounded. A simulation was run where the XFP receiver model was stimulated with a 10 Gb/s PRBS (27-1) bit pattern. The differential waveforms were probed between pins RD+ and RD- of the XFP module connector (host side), the resultant eyeplot is displayed in Figure 6. Due to the complexity of the XFP connector model simulation times tend to be long. Figure 7. TDR simulations of the full Spice connector model and the compact model.

7

Figure Simulation plotend. using For compact high8. frequency theconnector SONETmodel data incorporating the XFI compliance eye mask strings of consecutive ones and zeroes as

format long as 72 bits are allowed. The lowest frequency which then needs to pass the channel can be estimated to f_lowof= the BitRate/(2*N), where N is the Aaccording compact version model was therefore maximum number bits. Thus, forThe an constructed in orderof toidentical save processing time. OC-192 model SONETisdata pattern, this equates model to compact an equivalent single-line approximately 69 MHz. The low frequency cutoff that ignores the coupling between the pins and of the XFI channel to for be well below the 69 consequently cannot needs be used connectorMHz in crosstalk order for analysis, the link to be usable SONET induced however, it for accurately data formats. However, discontinuity even for smallcaused values by of describes the impedance theconnector. cutoff frequency, there isTime-Domain still an influence on the The simulated Data-Dependent Jitter (DDJ) and eye-closure. The Reflectometry (TDR) responses of the two effect is most pronounced sequences connector models are shownfor in long Figure 7. The of ones and between zeroes. The department of Agilent agreement theR&D 2 models is satisfactory. hasisestimated the DDJ reduction of the This also confirmed byand XFIthe channel simulations innerthe eyeresultant height foreye-plot the maximum where togetherallowed with the XFI sequenceeye of 72 identical bits. in The results these 1 is shown compliant mask Figure 8. of It can worst case calculations are depicted in Figure 10 be seen that the eye-plot with the compact model Figure 8. Simulation plot using compact connector model 7-1 PRBS bit Figure 9.comparable Frequency content of eye the a function cutoff frequency forstream athe 10emitted Gb/s by the incorporating the XFI of compliance isas very with the2mask plot using full XFP receiver SONET data pattern. connector model. All subsequent simulations used the compact connector model high frequency end. For the unless SONETotherwise data format stated. Furthermore, the eye diagram in Figure ofversion consecutive andwas zeroes as long8as A strings compact of theones model therefore will serve as a reference for quantitative 72 bits arein allowed. lowest frequency constructed order toThe save processing time.which The evaluations oftoeye closure as a function XFI link then needs pass the channel can be of estimated compact model is an equivalent single-line model design parameters. according = BitRate/(2*N), N is the that ignores to thef_low coupling between the where pins and maximum number of identical bits. Thus, for anis consequently cannot beof used connectorThe frequency content the for simulation pattern OC-192 SONET data pattern, this equates to induced crosstalk analysis, however, it accurately shown in fFigure 9. This is the Fourier transform approximately 69 MHz. The low frequency cutoff describes the impedance discontinuity caused by of the PRBS (27-1) pattern emitted by the XFP of the XFI channel needs to be well below the 69 the connector. The simulated Time-Domain receiver. It can be seen from this plot that MHz in order for the link to be usable for SONET Reflectometry (TDR) responses of the two frequencies above 20 GHz contribute little to the data formats. However, for small values connector models are shown Figure 7.model. The of output signal produced byeven theinreceiver the cutoffbetween frequency, is still an influence on agreement the there 2 models is satisfactory. Jitter and The AsData-Dependent mentioned earlier, for some dataeye-closure. formats it can This is also confirmed by(DDJ) XFI channel simulations is most pronounced sequences of beeffect as important to check thefor lowlong frequency end of where the resultant eye-plot together with the XFI 1 is ones and zeroes. The department ofIt Agilent the spectrum, as is toR&D verify performance atcan the compliant eye mask shown in Figure 8. Figure 10. Effect of theitlow-frequency cut-off on DDJ and inner eye has estimated DDJ with and the of the beheight. seen that the the eye-plot thereduction compact model Note: eye height for thethe maximum allowed is very comparable with plot using the full 1 inner Reference: XFP Multisource Agreement, www.XFPMSA.org. 8sequence of 72 identical bits. The results of used these connector model. All subsequent simulations case connector calculations are depicted in Figure 10 theworst compact model unless otherwise as a function of cutoff forin a 10 Gb/s8 stated. Furthermore, the frequency eye diagram Figure SONET pattern. for quantitative will serve data as a reference evaluations of eye closure as a function of XFI link design parameters. The frequency content of the simulation pattern is shown in fFigure 9. This is the Fourier transform of the PRBS (27-1) pattern emitted by the XFP receiver. It can be seen from this plot that frequencies above 20 GHz contribute little to the output signal produced by the receiver model. As mentioned earlier, for some data formats it can be as important to check the low frequency end of the spectrum, as it is to verify performance at the Note: 1 Reference: XFP Multisource Agreement, www.XFPMSA.org.

Figure 8. Simulation plot using compact connector model Figure 7. TDR the simulations of the full incorporating XFI compliance eyeSpice mask connector model and the compact model.

7 7 A compact version of the model was therefore constructed in order to save processing time. The

Figure 10. Effect of the low-frequency cut-off on DDJ and inner eye height.

8

Eye Measure In the follow frequency a having deve simulations design spac the electric parameters taken from These11.are c Figure Simu Figure 8. Th parameters the measur Simulations w In a first an dimensions of a 10 Gbit lines. The c simulations signal is em (which acts travels thro interconnec resistor tha termination termination arrows in F

This simula arrangemen dependant real-world S finite, Figure 11.albei Simu die. Howeve parameters

Simulations In a first an dimensions of a 10 Gbit lines. The c simulations signal is em (which acts travels thro interconnec resistor tha termination termination arrows in F

This simula arrangemen dependant real-world S finite, albei die. Howeve

Eye Measurements In the following we will focus on the highfrequency aspects of XFI channel design. After Eye Measurements having developed a suitable base model, In the following we will focus on the highfrequency assimulations were carried out to map out the pects of XFI channel design. After having developed a design space. In order to quantify the impact on suitable base model, simulations were carried out to map the electrical eye from varying several of the out the design space. In order to quantify the impact on parameters described earlier, measurements were the electrical eye from varying several of the parameters taken from eye-plots of transient simulation runs. described earlier, measurements were taken from eyeThese are compared to the reference eye-plot in plots of transient simulation runs. These are compared to Figure 8. The eye-diagram in Figure 11 shows how the reference eye-plot in Figure 8. The eye-diagram in Figthe measurements were taken. ure 11 shows how the measurements were taken.

m emitted by the

ta format as long as cy which estimated ere N is the us, for an es to ncy cutoff ow the 69 or SONET values of fluence on losure. The uences of of Agilent on of the wed ts of these Figure 10 10 Gb/s

nd inner eye

Figure 11. Simulated electrical eye plot showing measurement parameters Figure 11. Simulated electrical eye plot showing measurement parameters

Simulations with Microstrip Tracks

Simulations with Microstrip Tracks InIna afirst analysis we will theateffect of trackofdimenfirst analysis we look will at look the effect track sions and dielectric loss on theloss propagation of a 10 Gbit/s dimensions and dielectric on the propagation signal on Gbit/s microstrip transmission lines. The configuration of a 10 signal on microstrip transmission adopted for the simulations isadopted shown infor Figure lines. The configuration the 12. The electrical signal is emitted byinthe XFP optical receiver (which simulations is shown Figure 12. The electrical acts as an transmitter), and travels through the signal is electrical emitted by the XFP optical receiver XFP connector the interconnect structure (which acts asand an along electrical transmitter), and on the host PCB to thethe resistor provides 100along W differentravels through XFP that connector and the tial termination.structure The signalon is probed terminainterconnect the hostacross PCB the to the tion resistor as indicated theWred arrows in Figure 12. resistor that providesby 100 differential termination. The signal is probed across the termination resistor as indicated by the red arrows in Figure 12.

This simulation setup is a somewhat “idealized” arrangement which neglects the frequency dependant characteristics of the IC package of a real-world SerDes or Eye Opener IC, and the finite, albeit small, input buffer capacitance of the die. However, this approach will allow us to analyze the influence of the trace parameters on the XFI data channel in an unambigiuous manner. In a later chapter we will replace the termination resistor with a more realistic electrical receiver model. For the board-level interconnect, loosely coupled microstrip traces were used with a differential impedance of 100 W. Three combinations of trackwidth and dielectric were simulated for 4, 8, and 12 inches track length each. The details of the configurations together with the results of the eye diagram analysis are listed in Table 3. Please note that for both epoxy laminates the same dielectric constant was employed to enable the use of identical trace geometries. The dielectric constant reduces with frequency and differs somewhat for the two laminates, the figure used here is at the higher end of the range of reported values. It can be seen from the plots below in Figure 13 that the expected eye closure and increased data dependent, i.e. deterministic jitter is evident due to the increase in track length. Both ‘0’ and ‘1’ transitions split into multiple traces and the central area is severely reduced. The central eye mask shown in Figure 13 is based on the “XFI ASIC/SerDes Receiver Input compliance mask”1 and is for relative comparison only. Please note that 12 inches track length is the maximum recommended in the XFP multi source agreement. The results listed in Table 3 are plotted in Figure 14 to illustrate the increased deterministic jitter and the reduced eye opening as a function of the chosen microstrip geometry and dielectric material. It is evident that simulation 1 produces the largest losses, which are attributed to the skin- resistance of the relatively narrow, only 5 mil wide track. Widening the tracks to 12 mil considerably reduces the skin effect induced losses as can be seen in the data for Simulation 2. For both of these simulations, a lossier (and therefore cheaper) laminate with a loss tangent of 0.025 was used. To increase eye margin further one can Traces on PCB Zdiff ~100 Ω

This simulation setup is a somewhat “idealized” arrangement which neglects the frequency dependant XFP characteristics of the IC package of a XFP - Tyco real-world SerDes or Eye Opener IC, and the Receiver finite, albeit small input buffer capacitance of the CONNECTOR Model die. However, this approach will allow us to analyze

Figure 12. Building blocks for XFI data link simulation. The red arrows indicate where the signal is probed.

8

Termination Resistor 100 Ω

impedance of 100 W. Three combinations of trackwidth and dielectric were simulated for 4, 8, and 12 in track length each. The details of the configurations together with the results of the eye diagram analysis are listed in Table 3. Please note use lower as per Simulation 3. However, the that for loss bothlaminates epoxy laminates the same dielectric improvement is small except for very long interconnect constant was employed to enable the use of lengths exceeding about 6 inches length. For traces shortidentical trace geometries. The dielectric constant erreduces than 6 inches standard, i.e. higher loss laminates should with frequency and differs somewhat for be sufficient to meet the channel requirements. the two laminates, theXFI figure used here is at the higher end of the range of reported values.

ASIC/SerDes Receiver Input compliance mask”1 and is for relative comparison only. Please note that 12 in track length is the maximum recommended in the XFP multi source agreement. The results listed in Table 3 are plotted in Figure 14 to illustrate the increased deterministic jitter and the reduced eye opening as a function of the chosen microstrip geometry and dielectric material. It is evident that simulation 1 produces the largest losses, which are attributed to the skin-

Figure 13. Comparison of eye plots from 4in (left) to 12in (right) track length for simulation 2. Note: Table 3. Simulation parameters and results for microstrip interconnects. 1

Reference: XFP Multi Source Agreement.

Simulation Configuration 9 XFP Reference Eye

Inner Eye Height [mV]

Deterministic Jitter [ps]

Inner Eye Width [ps]

Inner Area [ps*mV]

508.0

1.9

98.1

24917.4

Simulation 1 : N4000-6 (er=4.1, loss tangent 0.025, 2.8 mil thick), 5 mil wide microstrip, 100 mil track spacing, 0.5 oz copper 4 in track length

428.1

4.1

95.9

20527.4

8 in track length

337.3

7.8

92.3

15558.0

12 in track length

262.1

12.8

87.2

11427.6

Simulation 2 : N4000-6 (er=4.1, loss tangent 0.025, 6.6 mil thick), 12 mil wide microstrip, 100 mil track spacing, 1 oz copper 4 in track length

464.0

3.2

96.8

22457.6

8 in track length

401.6

5.1

94.9

19055.9

12 in track length

347.3

7.4

92.7

16088.7

Simulation 3 : N4000-13 (er=4.1, loss tangent 0.016, 6.6 mil thick), 12 mil wide microstrip, 100 mil track spacing, 1 oz copper 4 in track length

483.4

2.9

97.1

23469.1

8 in track length

426.6

4.3

95.7

20412.8

12 in track length

379.7

6.0

94.0

17845.9

resistance of the relatively narrow, only 5 mil wide track. Widening the tracks to 12 mil considerably reduces the skin effect induced losses as can be seen in the data for Simulation 2. For both of these simulations, a lossier (and therefore cheaper) laminate with a loss tangent of 0.025 was used. To increase eye margin further one can use lower loss 9 laminates as per Simulation 3. However, the improvement is small except for very long interconnect lengths exceeding about 6 in length.

Simulations with Stripline Tracks Stripline trace geometries are sandwiched between two reference planes, which can simultaneously act as Power and Ground planes. The various conductive layers are typically separated by about 6 mil thick dielectric layers. This implies that the stripline width needs to be fairly narrow, of the order of 5 mils, in order to meet 100 W differential impedance design targets. It is therefore assumed that skin-effect losses will

interconnect lengths exceeding about 6 in length. For traces shorter than 6 in standard, i.e. higher loss laminates should be sufficient to meet the XFI channel requirements.

It is therefore assumed that skin-effect losses will play a significant role, even though the whole surface of the striplines conducts current, in contrast to microstrip traces where most of the

Figure 14. Selected eye diagram parameters for microstrip interconnect XFI link configurations

10

Simulations with Stripline Tracks Stripline trace geometries are sandwiched between two reference planes, which can simultaneously act as Power and Ground planes. The various conductive layers are typically separated by about 6 mil thick dielectric layers. This implies that the stripline width needs to be fairly narrow, of the order of 5 mils, in order to meet 100 W differential impedance design targets. It is therefore assumed that skin-effect losses will play a significant role, even though the whole surface of the striplines conducts current, in contrast to microstrip traces where most of the current flows on the surface opposite to the reference plane [Hall 2000]. Wider tracks to reduce the skin-effect induced resistance at high frequencies would require thicker layers of dielectric material, however, this may not be feasible as the overall thickness of the stack up may exceed practical limits. Thicker boards may also require thicker vias, which can have adverse effects on routing density and lead to pronounced impedance discontinuities. Another disadvantage of striplines is the need to contact them with vias. The choice of via design can have a significant impact on signal integrity and the performance of the whole XFI channel. The XFI MSA offers some guidelines for the design of vias, differentiating between singleended and differential vias, as well as analyzing the effect of open-circuit stub length on the via return loss (S11).

10

The high-frequency properties of vias (e.g. described by S11, S21 parameters) depend on the geometric parameters of the via (drilled hole diameter, length of via, clearance diameter, etc.), as well as the stack-up configuration and the precise location of Ground and Power planes. In addition, back drilling can be used to reduce the stub-length of the via for improved high-frequency performance. However, a full investigation of the influence of these parameters on the XFI data channel is neither possible nor within the scope of this white paper. Thus, an equivalent circuit was developed for single-ended vias that produced a similar response to the S11 plot shown in the XFP MSA (Figure 60 in XFP MSA revision 1.0), allowing the appropriate simulation of the impedance discontinuity introduced by the via. The equivalent circuit of the employed via model is shown in Figure 15. Some manufacturing variability has been incorporated into the model by using slightly varying capacitance and inductance values. The resultant graph of the via’s return loss is depicted in Figure 16. Similar to the via simulation shown in Figure 60 of the XFP MSA (revision 1.0), the model produces a dominant resonance peak at around 17 GHz. The via model was subsequently inserted into the XFI data channel at either end of host board stripline interconnect. This allows the signal to flow from the XFP connector to the stripline and back from the stripline to the SMT termination resistor.

inductance values. The resultant graph of the via’s return loss is depicted in Figure 16. Similar to the via simulation shown in Figure 60 of the XFP MSA (revision 1.0), the model produces a dominant resonance peak at around 17 GHz current flows on the surface opposite to the R=0.50 0.70nH [Hall 2000]. 0.71nHWider tracks 0.72nHto reference plane reduce the skin-effect induced resistance at high frequencies would require thicker layers of 150fF 153fF 156fF 159fF dielectric material, however, this may not be feasible as the overall thickness of the stack up may exceed practical limits. Thicker boards may also require thicker vias, which can have adverse Figure 15. Via equivalent circuit. effects on routing density and lead to pronounced impedance discontinuities. 11 Two sets ofdisadvantage simulations were performed, oneneed using Another of striplines is the to a standard andvias. another for a lower dieleccontactlaminate them with The choice of vialoss design tric having tangents ofimpact 0.025 and 0.016, respectively. can haveloss a significant on signal integrity For both theof striplines were 5 mil wide and and thesimulations, performance the whole XFI channel. sandwiched between reference planes thatfor were mil The XFI MSA offers some guidelines the12.2 design apart. The differentiating tracks were weakly edge-coupled with 50 mil of vias, between single-ended and spacing. differential vias, as well as analyzing the effect of open-circuit stub length on the via return loss The simulation parameters and results are summarized in (S11). Table 4, two selected parameters are plotted in Figure 17. AsThe expected, due to theproperties relatively narrow the high-frequency of vias linewidth (e.g. skin effect induced losses lead to a pronounced reduction described by S11, S21 parameters) depend on the ingeometric eye opening caused, predominantly by a hole greatly reparameters of the via (drilled duced inner eye height. In fact, the XFP MSA only diameter, length of via, clearance diameter, recometc.), mends stripline up configuration to a maximum and of 6 inches as well as thelengths stack-up the for standard The use of a lowerand lossPower dielectric, however, preciseFR-4. location of Ground planes. In can lead to a noticeable improvement in eye opening. addition, back drilling can be used to reduce the This is attributed dielectric losses are prostub-length of to thethe viafact forthat improved high-frequency portionately larger for stripline than for microstrip performance. However, a full investigation ofgeomthe etries, since the electric field is fullyoncontained in the diinfluence of these parameters the XFI data electric in aisstripline channel neitherconfiguration. possible nor Lower withinloss thedielectrics scope of can therefore be used to exceed recommended stripline this white paper. Thus, an equivalent circuit was lengths to greater than 6 inches. A related discussion developed for single-ended vias that produced a of the relativeresponse importance of skin-effect dielectric similar to the S11 plot and shown in thelosses XFP can also be found in [Johnson 2002]. MSA (Figure 60 in XFP MSA revision 1.0), the noting appropriate simulation of the (inner It allowing is also worth that the inner eye opening impedance discontinuity introduced by the via. of eye height, Figure 17) is reduced even for “zero” inches trace due tocircuit the presence of the twovia vias. In the Thelength equivalent of the employed model particular case considered here the two vias lead to is shown in Figure 15. Some manufacturing a reduction of thehas eye opening by approximately 10%.model Careful variability been incorporated into the viabydesign or the use of differential vias can be employed using slightly varying capacitance and toinductance minimize this loss. The resultant graph of the via’s values. returneffect loss isofdepicted 16. Similar the Another using viasinisFigure an increased level oftodatavia simulation shown Figure 60lengths of the XFP MSA dependent jitter, DDJ. Forinshort trace the deter(revision 1.0), the model a dominant ministic jitter oscillates with produces trace length, as is shown resonance peak at around 17 GHz R=0.50

150fF

0.70nH

0.71nH

153fF

Figure 15. Via equivalent circuit.

11 11

0.72nH

156fF

159fF

This is attributed to the fact that dielectric losses are proportionately larger for stripline than for microstrip geometries, since the electric field is fully contained in the dielectric in a stripline configuration. Lower loss dielectrics can therefore be used to exceed recommended stripline lengths to greater than 6 in. A related discussion of the relative importance of skin-effect and dielectric losses can also be found in [Johnson 2002].

Figure 16. S11 return loss of via equivalent circuit

The via model was subsequently inserted into the XFIthe data channel at eitherinend of host board for lower loss dielectric Figure 18. This oscillatory stripline interconnect. This allows the signal behavior is attributed to resonance effects set uptoby the flow from the the stripline and reflections fromXFP theconnector impedancetodiscontinuities caused back from the stripline to the SMT termination by the two vias at each end of the stripline. The effect is resistor. large despite the use of a pseudorandom bit surprisingly sequence. Two sets of simulations were performed, one using a standard laminate and another a lower To further investigate this phenomenon, thefor propagation loss dielectric havingforloss tangentsconfiguration of 0.025 and5 was delay of the stripline simulation 0.016, respectively. For both the Figure determined (174.17 ps/in). This simulations, allows us to plot striplines were of 5 mil sandwiched 18 as a function the wide signaland round-trip time (twice the between reference that were 12.2 trace length) in units planes of the bit period (100 ps).mil Theapart. resultThegraph tracksis were edge-coupled mil 19 ing shownweakly in Figure 19. It is clearwith from 50 Figure spacing. that the maxima and minima are periodic with the bit period which confirms the original interpretation of the jitter The simulation parameters and results are magnitude oscillations as a resonance effect. summarized in Table 4, two selected parameters This effect caninlead to variability in system performance are plotted Figure 17. As expected, due to the for short interconnect Small of the dielecrelatively narrow lengths. linewidth thevariations skin effect induced tric constant of athe epoxy laminate between losses lead to pronounced reduction inmanufactureye ing runs will result predominantly in variations of the opening caused, by stripline’s a greatlypropagation delay.inner This in turn will cause differences in MSA the signal reduced eye height. In fact, the XFP round-trip time for interconnects with up theto same only recommends stripline lengths a nominal length. The of overall effectfor onstandard system performance will be maximum 6 inches FR-4. a variability of the total jitter that needs to be tolerated Thethe use of a lower dielectric, however, can by receiver. In theloss interest of consistent system perforlead to a noticeable improvement in eye opening. mance it will be best to user a lower grade laminate that This is attributed the fact dielectric losses atintroduces dielectrictolosses largethat enough to sufficiently are proportionately larger for stripline than for tenuate reflections. microstrip geometries, since the electric field is fully contained in the dielectric in a stripline configuration. Lower loss dielectrics can therefore be used to exceed recommended stripline lengths to greater than 6 in. A related discussion of the relative importance of skin-effect and dielectric losses can also be found in [Johnson 2002].

Simulation 4 : N4000-6 (er=4.1, loss 0.025, 12.2 mil separation between reference planes), 5 mil wide stripline, 50 mil track spacing, 0.5 oz copper 2 in track length

375.7

4 in track length

321.4

7.9

92.1

14800.5

6 in track length

264.0

10.4

89.6

11827.2

8 in track length

225.6

13.4

86.6

9768.5

Table 4. Simulation parameters and results for stripline interconnects.

Simulation 10Configuration in track length

Inner Eye Height 190.4 [mV]

12XFP in track lengthEye Reference

161.3

Deterministic Jitter 17.5 [ps] 21.7

Inner Eye Width 82.5 [ps] 78.3

Inner Area

7854.0 [ps*mV] 6314.9

Simulation Simulation5 4: :N4000-13 N4000-6 (er=4.1, (er=4.1, loss loss 0.016, 0.025, 12.2 12.2 mil mil separation separation between between reference reference planes), planes), 55 mil mil wide wide stripline, stripline, 50 50 mil mil track track spacing, spacing, 0.5 0.5 oz oz copper copper 2 2inintrack tracklength length

391.1 375.7

4 4inintrack tracklength length

345.0 321.4

7.1 7.9

92.9 92.1

16025.3 14800.5

6 6inintrack tracklength length

294.0 264.0

8.9 10.4

91.1 89.6

13391.7 11827.2

8 8inintrack tracklength length

259.6 225.6

10.6 13.4

89.4 86.6

11604.1 9768.5

1010inintrack tracklength length

227.9 190.4

13.6 17.5

86.4 82.5

9845.3 7854.0

1212inintrack tracklength length

200.3 161.3

16.4 21.7

83.6 78.3

8372.5 6314.9

5 : N4000-13 (er=4.1, lossthe 0.016,inner 12.2 mileye separation between reference planes), 5for mil wide mil dielectric track spacing, in 0.5 Figure oz copper It Simulation is also worth noting that opening as is shown the stripline, lower 50 loss (inner eye height, Figure 17) is reduced even for 18. This oscillatory behavior is attributed to 2 in track length 391.1 “zero” inches of trace length due to the presence of resonance effects set up by the reflections from 4 intwo trackvias. length In the particular 345.0 7.1 92.9 discontinuities caused 16025.3 by the two the case considered the impedance here the two vias lead to a reduction of the eye vias at each end of the stripline. The effect is 6 in track length 294.0 8.9 91.1 13391.7 opening by approximately 10%. Careful via design surprisingly large despite the use of a in track length 259.6 10.6 to 89.4 bit sequence. 11604.1 or8 the use of differential vias can be employed pseudorandom minimize this loss. 10 in track length 227.9 13.6 86.4 9845.3 To further investigate this phenomenon, the Another effect of using vias is an increased level of propagation delay of the stripline for simulation 12 in track length 200.3 16.4 83.6 8372.5 data-dependent jitter, DDJ. For short trace lengths configuration 5 was determined (174.17 ps/in). It isdeterministic also worth noting that the inner opening as isallows shownusfor loss in Figure the jitter oscillates with eye trace length, This to the plotlower Figure 18 dielectric as a function of the 18. This oscillatory is attributed to in (inner eye height, Figure 17) is reduced even for signal round-trip timebehavior (twice the trace length) “zero” inches of trace length due to the presence of resonance effects set up by the reflections from the impedance discontinuities caused by the two the two vias. In the particular case considered vias at each end of the stripline. The effect is here the two vias lead to a reduction of the eye surprisingly large despite the use of a opening by approximately 10%. Careful via design pseudorandom bit sequence. or the use of differential vias can be employed to minimize this loss. To further investigate this phenomenon, the Another effect of using vias is an increased level of propagation delay of the stripline for simulation data-dependent jitter, DDJ. For short trace lengths configuration 5 was determined (174.17 ps/in). the deterministic jitter oscillates with trace length, This allows us to plot Figure 18 as a function of the signal round-trip time (twice the trace length) in

Figure 17. Selected eye diagram parameters for stripline interconnect XFI link configurations

12

Figure 17. Selected eye diagram parameters for stripline interconnect XFI link configurations

12 12

that needs to be tolerated by the receiver. In the interest of consistent system performance it will be best to user a lower grade laminate that introduces dielectric losses large enough to sufficiently attenuate reflections. units of the bit period (100 ps). The resulting graph is shown in Figure 19. It is clear from Figure 19 that the maxima and minima are periodic with the bit period which confirms the original interpretation of the jitter magnitude oscillations as a resonance effect. This effect can lead to variability in system performance for short interconnect lengths. Small variations of the dielectric constant of the epoxy laminate between manufacturing runs will result in variations of the stripline’s propagation delay. This in turn will cause differences in the signal round-trip time forjitter interconnects with the Figure 18. Data dependent as a function of stripline tracesame length nominal length. The overall effect on system performance will be a variability of the total jitter that needs to be tolerated by the receiver. In the interest of consistent system performance it will be best to user a lower grade laminate that introduces dielectric losses large enough to sufficiently attenuate reflections.

Figure 19. Data dependent jitter plotted as a function of the signal round-trip in units of the bit period.

XFI Channel Simulations with a SerDes Receiver Figure 18. Data dependent jitter as a function of stripline trace length So 13 far the “receiver” circuit was an ideal 100 W termination resistor. In a real-world XFI channel this will in most cases be replaced by an Eye Opener or SerDes IC with the termination resistor implemented on the Silicon die as part of the differential input buffer. This greatly simplifies system designs, as no additional surface mounted components are required for a XFI channel. However, this also means that the frequency dependent characteristics of the IC package are between the end of the host-board transmission lines and the termination circuitry. This in turn can have an influence on the quality of the received signal.

To evaluate this effect a model for the IC package was created. An ideal package for a XFI channel component would be a 50 W impedance (z0, zdiff =100 W) transmission line that would just introduce a delay to the signal but no reflections. Modern Ball Grid Array (BGA) IC packFigure 19. Data jitterto plotted a function of theline signal ages may get dependent fairly close this astransmission limit, round-trip the in units of the bitstructure period. however, internal of the IC package (eg. package vias and bond wires) will introduce impedance discontinuities. To model this progressively, we will take as 1313

To evaluate this effect a model for the IC package was created. An ideal package for a XFI channel component would be a 50 W impedance (z0, zdiff =100 W) transmission line that would just introduce a delay to the signal but no reflections. Modern Ball aGrid (BGA) line IC packages may an example 50 WArray transmission with a delay td of 90 get close to this line limit, length XFI Channel Simulations a SerDesinterconnect Receiver ps.fairly This corresponds to transmission anwith IC package however, the“receiver” internal structure theideal IC package So far the circuit an 100 of approximately 10 mm (~0.4was in),ofdepending onWthe re(eg. package and bond wires) will introduce termination resistor. In a real-world XFI channel fractive indexvias of the package material. Instead of describimpedance To modelby this this willinterconnect indiscontinuities. most cases replaced an however, Eye ing the as abe transmission line, we progressively, we will example a 50 W Opener SerDes IC take withas theantermination resistor will breakorthe package interconnect down into a discrete transmission line acircuits. delaydie td of 90 ps. This implemented on with the Silicon part ofdiagram the number of identical RLC Inas a circuit this corresponds to ana “ladder” IC package interconnect length differential input buffer. This greatly simplifies would resemble of series resistors and inducofsystem approximately 10 no mm (~0.4 in),surface depending on Each designs, as additional mounted tors linking capacitors that are connected to ground. the index of the package material. components are required forofa the XFI“ladder” channel. RLCrefractive element constitutes a step as is shown Instead of describing the as athis “ladder” However, thisinalso means thatmore the frequency schematically Figure 20.interconnect The steps transmission line, however, we willICbreak the dependent characteristics package are has, the more it will resembleof athe transmission line. Fewer package down into to a discrete number between theother end of the host-board transmission steps oninterconnect the hand will lead increased losses and oflines identical RLC circuits. aS11 circuit diagram this of and the termination circuitry. Thisparameters in turn pronounced resonances inIn the and S21 would resemble a “ladder” of series resistors can have an influence on the quality of the and this IC package interconnect model. inductors received linking signal. capacitors that are connected to The resonances andelement the cutoff frequency of this package ground. Each RLC constitutes a step of model move to lower frequencies as the number of RLC To evaluate this effect a model for the IC package the “ladder” as is shown schematically in Figure circuits is reduced. This is illustrated in Figure 21. For was created. An ideal package for a XFI channel 20. The more steps this “ladder” has, the more it the chosen example of be 50 aW50 asymptotic impedance and a component would Wline. impedance (z0, zdiff will resemble a transmission Fewer steps on delay of 90 ps, the total inductance equates to 4.50 =100 W) transmission line that would just the other hand will lead to increased losses and nH, and the total capacitance tosignal 1.80S11 pF. These are distributed introduce aresonances delay to thein but no reflections. pronounced the and S21 equally between the different “steps” of the “ladder” Modern Ball Grid Array (BGA) IC packages may[Hall parameters of this IC package interconnect model. 2000]. get fairly close to this transmission line limit, R the internal L however, structure of the IC package The thick grey line in Figure 20 is the maximum allowed (eg. package vias and bond wires) will introduce channel loss in an XFI link as per the XFP MSA. The packimpedance discontinuities. To model this age model consisting of only 2 RLC circuits is clearly not progressively, we will takeC as an example a 50 W consistent with the performance requirements of an XFI transmission line with a delay td of 90 ps. This link. corresponds to an IC package interconnect length Theapproximately effect that a realistic model has on the of 10 mmpackage (~0.4 in), depending on XFI link budget wasindex investigated a microstrip transmission the refractive of the for package material. line link model. As an example simulation configuration 2 Instead of describing the interconnect as a Ltransmission = tdchosen * z0 / with N line, =inches. td /the z0 / N was a microstrip ofC8break however,length we will Figure 20. Constituting elementsdown of an RLC-”ladder” package model. package interconnect into a discrete number The signal was probed at the IC pins (point 5 in Figure 1, of identical RLC circuits. In a circuit diagram this point D in the XFP MSA revision 1.0). Two eye diagrams would resemble a “ladder” of series resistors and that resulted from these simulations are shown in Figure inductors linking capacitors that are connected to 22. The eye on the left serves as a reference and shows the ground. Each RLC element constitutes a step of signal without an IC package model probed at the end of the “ladder” as is shown schematically in Figure the microstrip lines. The eye diagram on the right shows 20. The more steps this “ladder” has, the more it the same signal after the insertion of an IC package model will resemble a transmission line. Fewer steps on consisting of 3 RLC circuits. It is evident that the level of the other hand will lead to increased losses and jitter has increased, and the maximum inner eye opening pronounced resonances in the S11 and S21 is reduced. parameters of this IC package interconnect model.

R

L C

L = td * z0 / N

C = td / z0 / N

Figure 20. Constituting elements of an RLC-”ladder” package model.

the left serves as a reference and shows the signal 4, 6, 8, and 12 identical RLC circuits. The results without an IC package model probed at the end of are shown graphically in Figure 23. the microstrip lines. The eye diagram on the right shows theto same signalFigure after the In order interpret 23 insertion one needsoftoan IC package model 3 RLC circuits. It is remember thatconsisting fewer RLCofsections in the package evident that thea level of package jitter haswith increased, model means poorer a lowerand cutoff the maximum innernumber eye opening is reduced. frequency. A high of sections means that the package model asymptotically approaches a 50 The jitter and the inner eye height have been Figure 21. Transmission characteristics (S21) of the SerDes/Eye W transmission line. It is therefore evident from Opener IC package model. The package is broken down into multiple derived as a figure of merit from simulations Figure 23 that a package with a lower bandwidth identical RLC sections. where the total inductance and capacitance of the (fewer RLC sections) leads to increased jitter and chosen package model was broken down into 2, 3, a reduced eye opening. For the evaluation of the The thick grey line in Figure 20 is the maximum 4, 6, 8, and 12 identical RLC circuits. The results allowed channel loss in an XFI link as per the XFP overall XFI channel link budget it is therefore are shown graphically in Figure 23. important to pay attention to the frequency MSA. The package model consisting of only 2 RLC of theFigure IC package the eye circuits is clearly not consistent with the Incharacteristics order to interpret 23 oneofneeds to opener or SerDesthat IC. The same of performance requirements of an XFI link. remember fewer RLCargument sections applies in the package coursemeans the other way round, SerDes acts model a poorer packagewhen withthe a lower cutoff The effect that a realistic package model has on as the transmitter of the electrical signal andthat the frequency. A high number of sections means the XFI link budget was investigated for a XFP transceiver as the receiver. In order the package modelmodule asymptotically approaches a 50 microstrip transmission line(S21) linkofmodel. As an Figure 21. Transmission characteristics the SerDes/Eye Figure 23. jitter Jitter and inner eyeisheight as function of the ICfrom package keep toline. a minimum the bandwidth of the Wto transmission It therefore evident Opener IC package model. Theconfiguration package is broken 2 down intochosen multiple characteristics. example simulation was XFP transceiver needs towith be optimized in a similar Figure 23 that a package a lower bandwidth identical sections. length of 8 in. with aRLC microstrip fashion in order to keep any parasitics as small as (fewer RLC sections) leads to increased jitter andis One counter-intuitive observation in Figure 23 possible. a reduced eye opening. For the evaluation of the The thick grey line in Figure 20 is the maximum the fact that the eye opening seems to increase channel link it is therefore allowed channel loss in an XFI link as per the XFP overall again XFI if the number of budget RLC sections is reduced to important to pay attention to the frequency MSA. The package model consisting of only 2 RLC two. However, one needs to remember that this characteristics ofdoes the IC of loss the eye opener circuits is clearly not consistent with the package model notpackage meet the orspecification SerDes IC. The same argument performance requirements of an XFI link. of the XFP MSA. It applies appearsofthat the course the other way round, when thedue SerDes acts inner height of the eye is increased to the The effect that a realistic package model has on asreflection the transmitter of the electrical signal and the of the high frequency portion of the 10 the XFI link budget was investigated for a XFP transceiver module as the receiver. In order Gbit/s data stream by the package parasitics. microstrip transmission line link model. As an toThus, keep from jitter the to apoint minimum the bandwidth thethe of view of the Siliconofdie example simulation configuration 2 was chosen XFP transceiver needs to be optimized in a similar IC package acts as a low-pass filter. The reflected with a microstrip length of 8 in. fashion in order to keep any parasitics as small high frequency components of the signal will as possible. therefore be missing at the die pads, consequently

of 50 W asymptotic impedance and a delay of 90 ps, the total inductance equates to 4.50 nH, and the total capacitance to 1.80 pF. These are distributed equally between the different “steps” of the “ladder” [Hall 2000].

· For XFI c large sep and the S interconn to provid signal int 4 will be recomme rules for diameter lengths.

· If the XF limits, it optimum Agilent w designers providing addition, teams wi simulatio the XFP

The overrid XFI data ch careful ana “Due diligen compliance dependent MSA. Furth reducing the edge-rate and inner eye-opening at be smaller t the input buffer where it is most relevant. Interactions Conclusions and Recommendations can still cau The simulation examples and results within this unexpected Figure 22. Simulation without IC package (left eye diagram) and with an IC package model consisting of 3 RLC circuits. The signal is probed at paper have shown how the design of the XFI this will hav point 5 (figure 1, point D in XFP MSA) of the XFI channel reference model. channel can adversely affect the Signal Integrity of simulations the link. Special attention was paid to the 14 the system influence on signal quality of the interconnect towards a s The jitter and the inner eye height have been derived as transceiver module asthe thequantizer/ receiver. Ineye order to keep jitter structure between opener requiremen a figure of merit from simulations where the total induc- to a minimum theXFP bandwidth the XFP needs circuits on the moduleofand the transceiver eye opener/ tance and capacitance of the chosen package model was to be optimized in ahost similar fashion in orderclear to keep SerDes IC on the board. It became thatany Acknowledgm broken down into 2, 3, 4, 6, 8, and 12 identical RLC circuits. parasitics as small as possible. We would li the design decisions will depend on a number of The results are shown graphically in Figure 23. trade-offs: One counter-intuitive observation in Figure 23 is the fact Turin Techn In order to interpret Figure 23 one needs to remember that that the eye opening seems to increase again if the num- and suppor • For XFI channels where the transceiver and fewer RLC sections in the package model means a poorer ber of RLC sections is reduced to two. However, one needs Special than SerDes IC are placed close to each other, Figure 22. Simulation withoutcutoff IC package (left eye diagram) with an IC package model consisting of 3package RLC very circuits. The signal probed at the package with a lower frequency. A highand number to remember that this model doesis not meet his invaluab point 5 (figure 1, point D in XFP MSA) of the XFI channel reference model. EMI from the traces will contribute little to the of sections means that the package model asymptoti- loss specification of the XFP MSA. It appears that the in- which jump overall EMI of the system. This allows the use of cally height of the eye is increased due to the reflection of 14 approaches a 50 W transmission line. It is therefore nermicrostrip traces with standard, relatively high evident from Figure 23 that a package with a lower band- the high frequency portion of the 10 Gbit/s data stream loss FR-4. Attention needs to be paid to width (fewer RLC sections) leads to increased jitter and by the package parasitics. Thus, from the point of view of resonance effects due to reflections from a reduced eye opening. For the evaluation of the overall the Silicon die the IC package acts as a low-pass filter. The impedance discontinuities. The skin-effect XFI channel link budget it is therefore important to pay reflected high frequency components of the signal will resistance of relatively narrow traces and the attention to the frequency characteristics of the IC pack- therefore be missing at the die pads, consequently reducdielectric losses of standard FR-4 should age of the eye opener or SerDes IC. The same argument ing the edge-rate and inner eye-opening at the input bufprovide the necessary attenuation for applies of course the other way round, when the SerDes fer where it is most relevant. immunity to these reflections. acts as the transmitter of the electrical signal and the XFP 14

15

Conclusions and Recommendations The simulation examples and results within this paper have shown how the design of the XFI channel can adversely affect the Signal Integrity of the link. Special attention was paid to the influence on signal quality of the interconnect structure between the quantizer/ eye opener circuits on the XFP module and the eye opener/ SerDes IC on the host board. It became clear that the design decisions will depend on a number of trade-offs: • For XFI channels where the transceiver and SerDes IC are placed very close to each other, EMI from the traces will contribute little to the overall EMI of the system. This allows the use of microstrip traces with standard, relatively high loss FR-4. Attention needs to be paid to resonance effects due to reflections from impedance discontinuities. The skin-effect resistance of relatively narrow traces and the dielectric losses of standard FR-4 should provide the necessary attenuation for immunity to these reflections. • For XFI channels where the design requires a large separation between the XFP transceiver and the SerDes or Eye Opener IC, stripline interconnects are the most likely configuration to provide the targeted EMI margin. For good signal integrity, however, the use of low loss FR- 4 will be necessary. Furthermore, it is recommended to employ high-speed design rules for vias like increased clearance diameters and back drilling to reduce via stub lengths. • If the XFI channel design falls between these limits, it is recommended to determine the optimum configuration through simulation. Avago will support the activities of system designers and signal integrity engineers by providing state-of-the art component models. In addition, Avago’s Application Engineering teams will provide design references and simulation support to facilitate the adoption of the XFP standard for next generation systems.

For product information and a complete list of distributors, please go to our web site:

The overriding theme in the successful design of a XFI data channel is perhaps the requirement for a careful analysis of each constituting link element. “Due diligence” of a XFI link design is to establish compliance of each element with the frequency dependent loss specifications outlined in the XFP MSA. Furthermore, the sum of all losses needs to be smaller than the overall link budget. Interactions between the various link elements can still cause the XFI channel to show unexpected behavior and fail the compliance tests, this will have to be verified by signal integrity simulations. However, following this methodology the system design should rapidly convergence towards a solution that will meet the requirements.

Acknowledgment We would like to thank our colleagues at Avago’s Turin Technology Centre for their expert advice and support during all stages of this work. Special thanks are due to Giampaolo Bendelli for his invaluable help at the beginning of this study, which jump-started this white paper.

References [Hall 2000] Stephen H. Hall, Garrett W. Hall, James A. Call, “High Speed Digital System Design”, John Wiley & Sons, Inc., ISBN 0-471-36090-2. [Johnson 2002] Howard Johnson, “Mixtures of skin-effect and dielectric loss”, EDM Magazine, September 19, 2002. [Ritchey 1999] Lee W. Ritchey, “A tutorial on PCB Materials”, www.speedingedge.com

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