Philips J. Res. 48 (1994) 9-35

R1287

REDUCED EQUIVALENT CIRCUIT MODEL FOR PCB by R.F. MILSOM,

K.J.SCOTT

and P.R. SIMONS

Philips Research Laboratories, Cross Oak Lane, RedhilI, Surrey RH1 5HA, UK Abstract The physicallayout of electronic equipment can have a major influence on its electromagnetic behaviour. Correct design of this layout, in particular that ofPCBs, is therefore vital for EMC considerations, and accurate simulation of this behaviour is therefore needed. An equivalent circuit model for arbitrary layout has been developed and is presented in a companion paper in this issue. This paper describes the theoretical basis of a method to compress this circuit to a managable size for circuit analysis packages. An example demonstrating a massive increase in numerical efficiency is presented. Both the generation of the equivalent circuit and its compression are built into the Philips PCB layout simulator FASTERIX. Keywords: circuit compression, electromagnetic compatibility, equivalent circuit, layout simulation, printed circuit board.

1. Introduetion The physicallayout of electronic equipment, and in particular PCB (printed circuit board) layout can be a major cause of EMC (electromagnetic compatibility) problems. Both common and differential mode coupling and many other unwanted effects can arise when layout is poorly designed. As part ofthe project "Development ofan EMC Workbench for Microelectronic Application" within JESSI (Joint European Sub-micron Silicon Initiative), Philips Research Laboratories in both the UK and the Netherlands are developing a CAD package FASTERIXI) to simulate EMC problems. With this package board designers will be able to treat EMC as central to the design process, with the conductors and dielectrics of the PCB, cables and packages modelled as additional discrete components. FASTERIX is the successor to FACET2,3) whichaddressed part of the problem. Both packages are based on the automatic generation of a lumped passive equivalent circuit model comprising a network of capacitors, inductors and resistors. The netlist so generated is loaded directly into the Philips circuit analysis package PSTAR so that physical layout and components are modelled simultaneously. The model described here concentrates on predicting internal interference effects appearing in one part of a piece of

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R.F. Mi/som, K.J. Scott and P.R. Simons equipment as a result of sources in another part of the same equipment. Simulation of radiation and irradiation are also features of FASTERIX') but are not considered here. Many published papers'r') and commercial packages'') treat PCB connections as transmission lines. These are efficient models for straight parallel tracks. FASTERIX contains a much more general lumped equivalent circuit model for completely arbitrary layout. Despite this generality, the package is orders of magnitude more efficient for this type of problem than a typical package based on FEM (finite element method)") and even substantially faster than a package based on BEM (boundary element method)"). Nevertheless, when FASTERIX is applied to typical problems, the equivalent circuit it generates is initially extremely large. As a first step in FASTERIX a geometry pre-processor subdivides conductors into quadrilateral elements. In the lumped model derived directly from these elements, referred to here as thefull circuit model, there is mutual inductance and capacitance between each pair of elements, so the number of components in the equivalent circuit is of the order of the square of the number of elements, potentially many tens of millions. This complexity is illustrated in fig. 1 which shows a PCB layout with conductors subdivided into a few thousand quadrilateral elements. Computer memory and CPU limitations therefore imply that, as it stands, this layout cannot realistically be simulated. The theoretical basis of a method to reduce greatly the number of components in the circuit, while retaining the validity ofthe model for EMC applications, is described here. This reduced equivalent circuit, which has now been incorporated into FASTERIX, is referred to as the compressed circuit model. FASTERIX derives its numerical efficiency from the fact that both the generation of the full circuit model and also its compression are once only computations, i.e. they do not have to be repeated for each time or frequency. This is possible because geometrical features of layout are generally much smaller than a wavelength of electromagnetic radiation at frequencies of interest in EMC. Time and frequency domain analysis are handled by the circuit simulator into which the compressed circuit model is loaded. Splitting the modelling into field and circuit analysis phases is orders of magnitude more efficient than applying field analysis at every time or frequency point. Despite this approximation, accuracy is maintained typically up to several GHz. 2. Field analysis

A piece of electronic equipment typically comprises one or more PCBs with discrete and integrated components, and also packages and cables attached.

10

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Reduced equivalent circuit model for PCB

Fig.I. Mesh generated by FASTERIX for PCB layout from CAD system,

The electromagnetic analysis described here is aimed primarily at PCB layout, but is sufficiently general to include most parts of equipment structure. The set ofPCBs, packages and cables will be referred to as the interconnection system. The conductors and insulators which make up this structure are assumed to contain only linear materials, which is a valid assumption for the intended applications. Now let the interconnection system be excited by some AC source of frequency f (angular frequency w = 27rf). All field and circuit variables are then complex and have harmonic dependence on time t. Consequently a common factor of exp(jwt) may be suppressed throughout the analysis . . In the quasi-static BEM used to determine the full circuit modeI9), the solutions for current density j(r) and charge density p(r) on the conductor surfaces

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R.F. Mi/som, K.J. Scott and P.R. Simons are expanded over basis function sets defined in the elements. The spatial variation of current and charge over the conductors is extremely rapid, particularly near edges, so a large number of elements (and therefore unknowns) is required to obtain an accurate field solution. In thefull circuit model there is a one-to-one correspondence between circuit nodes and geometrical elements, and similarly between series branches in the circuit and edges between elements. In the modification to the method described here the scalar potential n= jw

JJ L

77n(r) dr3

(m, n = 1, 2 .... M - 1)

(26)

This solution for Y'!;>nis seen to depend on the choice of surface enclosing super node m and is therefore non-unique. The ambiguity is due to obtaining an explicit solution for the divergence ofj!((r) rather than for the current itself. Nevertheless a unique solution can be postulated. Recalling that 77n(r) is the solution for charge density due to a scalar potential distribution 'ljJn(r) which takes the value 1 at rn and 0 at rm(m =I- n), it is proposed that eq. (26) be modified to Y,?rn = jw

JJJ

'ljJm(r)77n(r) dr3

(m, n = 1,2 ....M - 1)

(27)

where the volume integral is over the domain of all conductors. Superposition theory'") shows that eq. (27) gives the correct net divergent current over all conductors for any set of super node voltages. Additionally, eq. (27) is found to be symmetrical in m and n as required by the theorem of reciprocity'"), Application to real examples has demonstrated that eq. (27) is a valid assumption. The net current at a node is the sum of solenoidal and divergent contributions. Therefore, Y mn = Y~n

+ Y'!;>n

(28)

(m, n = 1, 2 .... M - 1)

4. Equivalent circuit model

The admittance matrix model described above can be used directly in some circuit analysis packages, for example the Philips simulator PSTAR. However .its use is limited to frequency domain analysis. For general non-linear time domain circuit analysis a lumped model of the interconnection system is required. This is derived here from the admittance matrix model. Firstly the lossless case is considered. Then a correction for ohmic loss is introduced. In the following section it is shown how the component values in the compressed circuit model can be derived from the full circuit model. 4.1. Loss-less

compressed

circuit model

Substituting eqs (22) and (27) into eq. (28) Y;nn = j~

20

JL

un(r) . nm(r) dr2

+ jw

JJJ

'ljJm(r)77n(r) dr3

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Reduced equivalent circuit model for PCB Equation

(29) may be written as

1 Ymn =:---L , +jwC~n JW mn

(m,n=

1,2 ....M--l)

(30)

where ,

1

Lmn = ffm un(r) . nm(r) dr2

(31)

and (32)

L~n and

c:

can clearly be identified as inductance and capacitance, so the admittance matrix model can be replaced by an equivalent circuit model, an example of which is shown in fig. 5 for the case of a layout with four super nodes. There is a parallel tuned circuit section comprising inductor L'mn and capacitor between every node pair m and n. The combination L~m, is connected between node m and the arbitrarily chosen ground node. Since Ymn is defined as the inwardly directed current at node m when node n is at 1 V and the other nodes at 0 V, it can be seen by comparing this circuit with eq. (30) that the values of the lumped components to be used in circuit analysis are given by

c:

a;

M-I

Cmm= LC~m

0~

_I

c.; = -C~n

(m =I- n)

M-I

Lmm= 1 /

LL' n=1

Lmn = -ii;

1

nm

(34)

(m =I- n)

In the special case where the node selected as ground corresponds to an ideal ground plane, whose presence has been allowed for in the Green's functions, the diagonal term Lmm is zero. One important property of this compressed circuit model is that it contains no mutual inductors, inductive coupling being fully accounted for by the selfinductances between all combinations of node pairs. This equivalence has a practical significanee in that some circuit simulators have limited capability for handling mutual inductances, and even those that allow mutual inductances appear to be more efficient when handling equivalent self-inductances.

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R.F. Mi/som, K.J. Scott and P.R. Simons

'"

2._---_.

N

U

C33

Cl3

Cl2

C22 o Ll2

........

j

u

o

Fig. 5. Equivalent circuit of four super node interconnection system -

excluding loss.

The most significant property, however, is the small number of circuit nodes compared with the number of geometrical elements. When this equivalent circuit, along with models for other components and sources, is used in a circuit simulation a numerically efficient simulation of layout effects results. As part of the circuit solution all node voltages and branch currents are obtained. Then using eqs (4) and (20) it follows that the field amplitude coefficients are given by (35)

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Reduced equivalëntcircuit

model for PCB

where Vn and Vg are the computed complex voltages at node n and at the chosen ground node respectively. The solutions for charge density and solenoidal current density are then given by M

p(r) =

L an7Jn(r)

(36)

n=1

and M

jS(r)

=

L anun(r)

(37)

n=1

Therefore the field solution follows directly from the solution of the circuit model. 4.2. Correction for loss

There are three important loss mechanisms in the interconnection system, all of which have been ignored in the analysis thus far: (1) resistive (ohmic) loss; (2) dielectric loss; (3) radiation loss. At frequencies of concern in most EMC problems, all these components of loss generally have only a small effect on current and charge distribution compared to the effect of inductive and capacitive coupling. Loss can therefore be treated as a perturbation of the loss-free behaviour of the interconnection system. The principal concern here is ohmic loss. The small dielectric loss can be modelled approximately, by post-multiplying all equivalent circuit capacitor values by a factor derived from the dielectric loss tangent. Radiation is of major importance in EMC simulation, but this is dealt with in a companion paper in this issue"). From the earlier analysis the solenoidal (divergence-free) current corresponding to a scalar potential distribution 'l/Jn(r) was given by j~(r)

= ;_un(r)

(38)

JW

The effect of introducing non-zero resistivity is to add a small correction to this current. Thus, including loss, j~(r) = ;_un(r) JW

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+ ~j~(r)

(39)

23

R.F. Mi/som, KJ. Scott and P.R. Simons Comparing with eq. (8) the corresponding perturbation ofthe vector potential is given by, (40) Now introduce the finite conductivity a of the conductors. The continuum equivalent of Ohm's law'") then modifies eq. (12) to give

+ .6.vn)

-'\l'ifJn - jw(vn

.s =Jn a

(in conductors)

(41)

and subtracting eq. (12) from eq. (41) •

A

-JWuVn

-s Jn =a

(42)

Now, substituting eq. (39) into eq. (42) and ignoring second order terms, to a good approximation (43) and combining eqs (40) and (43)

JJ' r

Je

GA(rlr').6.j~(r')

d3r' = un(r) w2a(r)

(44)

Since the vector potential un(r) is known from the loss-free analysis, eq. (44) is sufficient to determine the correction .6.j~(r). This is seen to have the form (45)

.6.j;(r) = ~Pn(r) where Pn(r) is the frequency-independent solution of

J J Ic

GA (rlr')Pn(r')dV

(46)

= ~(~;

Now, substituting eq. (45) into eq. (39) j;(r)

= ;_un(r) JW

+ ~Pn(r)

(47)

W

Comparing eq. (47) with eq. (31) it can be seen that the ohmic loss can be allowed for by modifying the inductances L~n to L'(mod) mn

24

=

1 - (l/jw)L:nn

fOfL~n

JmPn(r)'

...7 nm(r) d,.-

(m,n = 1,2 ....M ~ 1)

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-----------------~--~

-_

Reduced equivalent circuit modelfor PCB Since the second term in the denominator on the right-hand side is small compared with the first, eq. (48) can be approximated by L,(mod) = L' mn mn

{I + jwL:n R~m } n

(49)

where (50) Equation (49) indicates that, rather than modify the inductance, it is sufficient to add resistances Rmn in series with the Lmn where, taking proper account of the defined positive current direction, these are given by M-I

Rmm = L;m

L n=1

Rmn

=

-R~n

R'

,nm2 Lnm (m =1= n)

(51)

As with inductance, the diagonal resistance term Rmm is zero for the special case where the node selected as ground corresponds to an ideal ground plane. The modified form of the equivalent circuit in fig. Sis shown in fig. 6. 5. Derivation

of compressed model from full model

The derivation of the compressed circuit model described above is based entirely on field theory. However, it has not yet been shown in detail how the basis functions used are actually derived. One method of solving for these functions, and hence the component values in the compressed circuit model, uses the full circuit model as a starting point. This is not the most numerically efficient method of deriving the basis functions. However, since the full circuit model is currently available from FASTERIX, this provides the simplest method to test the circuit compression theory. More efficient methods are currently under investigation. The method is nevertheless equivalent to a field solution. The basic ingrediants of the full circuit model are now summarised. 5.1. Full circuit model (1) Each geometrical element corresponds to both

• a node of the equivalent circuit; • a capacitor plate. (2) Each edge between elements corresponds to both • a series branch of the equivalent circuit; • a series combination of resistor and inductor.

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R.F. Mi/som, KJ. Sealt and P.R. Simons

M

'".., M

'" U

o

R12

C33

C13

C12

C22

o L12

lilf----

R33

R13

....

.... ....

j

u

o

'" 0:

Fig. 6. Equivalent circuit of four super node interconnection system - including loss.

Let the complete set of conductors be subdivided into N elements (nodes) and T edges (series branches). Each edge s will have a defined positive direction, where the positively-directed unit vector normal to the edge is ns, and the elements on the negative and positive sides of the edge respectively have global indices p-; and p;. Let element n have Kn edges across which current can flow. Note that, although all elements are quadrilaterals, in some cases K; < 4. This arises if one or more edges of an element are open-circuit, i.e. not adjacent to another element.

26

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Reduced equivalent circuit model for PCB Now, a surface charge density basis function gn(r) is defined on each element

n such that, (52) where the integral is over the element n. The actual surface charge density p~s) (r) is then given by (53) where Qn is the net charge on the element. Surface current density basis functions hnk(r) are defined over the nth element and belonging to the kth edge of the element such that

1nk hnk(r) . nSnk(r) dr

=1

(54)

where the line integral is along the edge whose global index is Snk' The function hnk(r) is defined to be zero outside element n, and to make zero contribution to current crossing edges other than the kth. The surface current density just inside the element at the edge is given by,

js':2(r) = Is hnk(r)

(55)

where Is is the net current crossing the edge. The net surface current density in element n is then given by

x, J~s)(r)

=

'LJSnkhnk(r)

(56)

k=1

This is required

to be a solenoidal

field, i.e.

V' . .l"s) = 0

(57)

Note, however, that there is no requirement for the individual edge basis functions hnk(r) to be solenoidal, so long as eq. (57) is satisfied for each element. The precise form of hnk(r) is beyond the scope of this paper. Recalling that the two elements adjacent to edge S are numbered p; and pt, a total edge basis function Ws(r) with contributions from both elements can be defined for edge s. Thus

Ws(r)

=

hp;fl;(r)

+ hptp.t(r)

(58)

where /L; and /Lt are the local indices of the global edge S referred to the elements p; and pt respectively. The values of the components in the equivalent circuit are related to the basis functions as follows.

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R.F. Mi/som,

KJ. Scott and P.R. Sim ons

5.1.1. Inductance

The external mutual inductance L~~)(s, t = 1, 2 .... T) between edges sand t is given by L~~) =

Jh.

. At(r) d2r

Ws(r)

(59)

where At is the vector potential due to unit current across edge t. Therefore, using eqs (8), (54), (55), (58) and (59) it can be shown that L~~) =

J h. J h, Ws(r)

GA(rlr')Wt(r')d2r'd2r

(60)

where Os is the domain of the two elements p; and pi adjacent to edge s. Alternatively, L~~)=

J1; J1;+ J 1; J 1i + J1; J1;+ J1: J1i

GA (rlr')hp;-J-L;-(r') d2r' d2r

hp;J-L;(r)

2

2

2

2

2

2

hp;J-L;(r)

GA (;lr')hpiJ-Li(r')

d r' d r

hp;J-L:(r)

GA (rlr')hp;-J-L;-(r') d r' d r

hp:J-L:(r)

GA (rlr')hpiJ-Li(r')

d r' d r

(61)

5.1.2. Internal impedance

The internal impedance ZY) of edge s is defined as the impedance of the series combination of resistance R, and internal component of inductance L~? This is given by ZY) = s, + jwL~? =

Jh.

Z(surf) Ws(r)

2

. Ws(r)

(62)

d r

where Z(surf) is the complex surface impedance (complex form of surface resistivity2o)) of the conductor in domain Os. Assuming this is constant over each element, then substituting eq. (58) into eq. (62) Z(i) s

= R s +J·wL(i) ss = z(~urf) Ps.

/1 /1

+ z(~urf) P3 where

28

Zp(~urf) and Z(~rf) • P.

P;

hp,- J-L, -(r)

pi

. hp,- J-L, -(r) d2r (63) 2

hp+J-L+(r) . hp+J-L+(r) d tit

r

t

are the surface impedances of elements p; and pi;

Philip. Journal of Research

Vol. 48 Nos 1"'"2 1994

Reduced equivalent circuit model for PCB Since Z(surf) is a function of frequency as well as conductivity it follows that Z~i) is also frequency dependent. However, since the internal impedance of conductors is typically small compared to their external impedance at frequencies of interest in EMC, it is a good approximation to treat Z~i) as constant at its DC value. This is only necessary for time domain analysis and for the circuit compression. If Z~i) is the same for all elements then the frequency dependent correction for skin effect can be restored after compression, at least for frequency domain analysis. 5.1.3. Capacitance The voltage Vn on element n is defined as the weighted potentialover the element. Thus

J1s,

=

Vn

(r)