PSoC® 3 Sensored BLDC Motor Control

AN53595 Author: Isaac Sever Associated Project: Yes Associated Part Family: CY8C3xxx, CY8C5xxx Software Version: PSoC Creator 1.0 Associated Application Notes: AN42102

Application Note Abstract AN53595 details the implementation of Sensored BLDC motor control, using Hall Effect sensors, with closed loop speed ® control using the CY8C3866AXI-040 PSoC 3 device. Hardware over current protection and speed control in the BLDC application is also explained.

Introduction Brushless DC (BLDC) motors are now replacing traditional brushed DC motors due to higher reliability, efficiency, and lower noise. These are popular in almost every field such as consumer electronics, home appliances, and industrial controls. Development of high performance BLDC control systems requires higher accuracy. This is achieved by using closed loop control in a majority of BLDC control systems.

BLDC The advantages of BLDC motors over brushed DC motors are:

     

High efficiency More reliable and no arcing on commutation – No brushes to maintain Higher speed and power to size ratio Heat is generated in stator – Easy to remove

To implement this sequence, it is important to know the rotor position. This is done by using sensors, such as Hall Effect sensors (sensored control), or by sensing back EMF (sensorless control). Hall Effect sensors are embedded in the stator. When the rotor magnetic poles pass near the hall sensors, they supply a high or low signal, indicating that the north or south poles are passing nearby. The position of the rotor is derived from the exact combination of the three hall sensor signals. Sensored BLDC is introduced in this application note. Three position sensors provide the current position of the rotor. Position sensors toggle each at 180 electrical degrees of electrical rotation. A timing diagram of sensor output and the required motor driving voltage is shown in Figure 1. The optional use of pulse-width modulation (PWM) provides speed or torque control as shown on Phases A, B, and C in Figure 1. The duty cycle of the modulated output control signal (PWM) is varied to change the speed and torque of the motor. Figure 1. BLDC Sensor Output vs. Commutation Timing

Lower inertia – No commutator Higher acceleration rate

BLDC motors are more efficient than brushed DC motors. For the same input power, a BLDC motor converts more electrical power into mechanical power than a brushed motor because of the absence of friction due to brushes. In a brushed motor design, the brushes are used to change the poles of the electromagnet in order to keep the motor spinning. Due to this lack of brushes, there is nothing to mechanically handle the polarity changes. As a result, an electronic controller is required to continuously switch the phase of the winding which will keep the motor spinning. To do this, the stator windings are energized in a particular sequence as seen in Figure 1. BLDC motors have three phases. With this topology, to move the motor, two phases are driven during each commutation cycle. One phase is driven high (VMotor) and the other is driven low (GND). The remaining phase is left floating. With every commutation step, the motor will move 60 degrees. Upon completion of all cycles, the motor will have moved a complete 360 degrees.

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Hall-1

1

1

0

0

0

1

Hall-2

0

1

1

1

0

0

Hall-3

0

0

0

1

1

1

W

Wup

0

Wdown

V

U

Vup Vdown

Uup

0

0

0

0

Udown

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PSoC 3 Introduction The CY8C3866AXI device is in the PSoC 3 family. A block diagram of the device is shown in Figure 2 with the blocks used in the BLDC application highlighted. Figure 2. PSoC 3 (CY8C3866AXI) Block Diagram

Digital Subsystem The PSoC 3 digital subsystem provides unique configurability of functions and interconnects. The subsystem connects digital signals from any peripheral to any pin through the digital system interconnect (DSI). It also provides functional flexibility through an array of small, fast, low power universal digital blocks (UDBs) and small blocks targeted to specific fixed functions.

Fixed function timer blocks in PSoC 3 devices are of 16 bits and configurable to act as timers or PWM that play important roles in embedded systems. PSoC 3 provides up to four instances of the Timer block. If additional Timer blocks are required, they are configured in the UDBs. Timer blocks have various clock sources and are connected to the general-purpose input/output (GPIO) though the DSI.

UDBs

Configurable digital functional blocks are also available for other specific functions.



   

For optimal flexibility, each UDB contains several components:  ALU based 8-bit data path  Two fine grained PLDs  Control and Status Module  Clock and Reset Module A PSoC 3 device contains an array of up to 64 UDBs. Flexible routing through the UDB array. Portions of UDBs can be shared or chained to enable larger functions. Flexible implementation of multiple digital functions, including but not limited to timers, counters, PWM (with dead band generator), UART, I2C, SPI, and CRC generation/checking.

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Analog Subsystem The PSoC 3 analog subsystem provides the device, the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.2% error over temperature and voltage. The configurable analog subsystem includes analog muxes, comparators, analog mixers, opamps, voltage references, analog-to-digital converters (ADC), digital-to-analog converters (DAC), and digital filter blocks (DFB). All GPIO pins can route analog signals into and out of the device, using the internal analog bus. This feature enables the device to interface up to 62 discrete analog signals.

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The analog system on the CY8C3866AXI device contains:

  

Four continuous time/switched capacitor building blocks, which can be used to make programmable gain amplifiers (PGA), transimpedence amplifiers (TIA), mixers, and more. Four comparators with user configurable speed, accuracy, and hysteresis settings. Four dedicated opamps, which can be used as an analog buffer to drive external loads, analog filters, peak detector, a slow comparator, and so on.

 

Four DACs, configurable as current or voltage output, which are user configurable output range, direction, power, and speed. Delta-Sigma ADC with selectable resolution from 8 to 20 bits. These have user configurable input range, reference, sample rate, and operating mode.

BLDC Motor Control Based on PSoC 3 The block diagram of the BLDC motor control based on PSoC 3 is shown in Figure 3 and the PSoC Creator™ schematic is shown in Figure 4.

24 V Power Supply

Figure 3. Block Diagram of PSoC 3 BLDC Motor Controller

Inverter Module 6

Bus Current

3 Hall Sensors

I/O PWM Generator

I/O

PGA

3.3 V / 15 V Power Supply

I/O

DAC

I/O

Speed Command

BLDC Motor

ADC

State Machine (Speed Control)

PSoC3



Input control signals to the PSoC 3 are:

  

Speed command: Analog input pin that measures the voltage across a potentiometer to set the desired speed of rotation (one analog input pin). Motor current detection: Analog input pin to detect and cut off power device driver to protect motor when over current condition is detected (see following section) (one analog input pin). Hall Sensors: Three digital input pins connected to the outputs of the hall sensors from the motor. These sensor inputs provide the position of motor and are used to control the commutation by varying the PWM output signals to the power driver (three digital input pins).

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

Direction control: Digital input connected to a switch to control the motor rotation between clockwise and counter-clockwise (one digital input pin). Start/stop control: Digital input connected to a switch to start and stop rotation of the motor (one digital input pin).

Outputs from PSoC 3 are power device driver signals.

 

PWM signals to the high side of the power device driver (three digital output pins). PWM signals to the low side of the power device driver (three digital output pins).

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Figure 4. PSoC Creator Schematic for BLDC Sensored Motor Control

The three Hall Effect sensors are fed into a lookup table (LUT), which is created using the PLD capabilities of the UDB, and uses the data from the sensors to determine the motor position. The LUTs programmed logic will then pass the appropriate PWM signals to the GPIO at the proper time. The GPIO pins are connected to a external power driver module which will directly drive the BLDC motor by gating the high voltage supply. The LUT will also control the direction of the motor and control the starting and stopping of the motor based on what is read by the LUT from Com_Control_Reg. This digital logic will work together to produce the commutation sequence to turn the motor as seen in Figure 1. Speed control is accomplished by reading a potentiometer from an analog input pin with the DelSig ADC. Every time isr_termcount triggers, the firmware will check the ADC and see if any changes to the motor speed are required based on the voltage measured. The current speed of the

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motor is measured with TACH_timer, which is a 16 bit timer. Once a falling edge of Sensor 1 occurs, we know that the motor has made a complete revolution. This rising edge will trigger a capture on the timer and move the current timer value to a register which we can then read and determine the current motor speed. The calculated motor speed will then be fed into a control loop to compare the measured and expected motor speed. Based on this calculation, the duty cycle of the PWM may be adjusted to more accurately match the desired motor speed. This design also implements hardware based over current protection which is explained in greater detail in the next section. The comparator output of the over current detection system is tied directly to the PWM kill signal. When over current triggers, the PWM output is killed which will stop all control signals to the external driver module. This will occur regardless of the current CPU process or state.

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Over Current Protection This is implemented in hardware on the PSoC 3. The block diagram is shown in Figure 5. Figure 5. Over Current Protection Block Diagram for Three Phase Motor High Voltage Power Module Board and PSoC 3 Inverter Module

Vbus+

P

W

V

W V U

Comparator kills PWM output when current-detection input voltage is over the current limit threshold set by the DAC

BLDC Motor

U 3.3V

Nu

HALL 3 HALL 2 HALL 1

10k ohms

I/O

Nw

Nv

10k ohms

Level shift to mid PSoC3 supply ~ 1.65 V

Motor current is measured with a shunt resistor in the ground path of the power inverter module (R1 in Figure 5). This voltage is level shifted on the board and connected to an analog input pin on PSoC 3 (labeled CURRENT). This input voltage is fed into a PGA implemented with an analog continuous time block. The PGA multiplies the difference between the input voltage and reference voltage (a buffered voltage at half the analog supply, VDDA) and connects the output to a clocked comparator. The voltage level is compared to the current limit. The current

clk

PWM Generator

SC/CT

PGA

Current though 0.02 inverter (and motor) ohms shifts DC on R1 R1

CURRENT pin

Analog

Digital

DAC

UDB

Logic (LUT)

3H 2H 1H 3L 2L 1L

I/O

24 V Power Supply

3 Phase Motor High Voltage Power Module Board

PWM kill

Current Limit Threshold

PSoC3

limit value is set in a register and converted to an analog voltage with an 8 bit voltage DAC. The output of the comparator is connected to the PWM block and kills the PWM output when the current limit threshold is exceeded. This provides cycle-by-cycle current limiting to the BLDC motor. The implementation of the over current protection in PSoC Creator is shown in Figure 6.

Figure 6. PSoC Creator Schematic Implementation of Over Current Protection

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PSoC 3 resources used in the BLDC over current protection are:

    

Continuous time (SC/CT) block to implement the PGA. Analog comparator – This is a dedicated analog resource and does not use a SC/CT block. 8-bit PWM implemented in UDB (The same PWM used to control power device driver) – The output of the comparator triggers the kill input to the PWM when an over current condition is detected. Analog buffer, using one of the dedicated analog opamps. (This could be replaced with external resistor dividers and an analog input pin to reduce resource usage). VDAC8 – Built in 8-bit voltage DAC, this is used to set the current limit threshold for the comparator. (This could be replaced with external resistor dividers and an analog input pin to reduce resource usage).

To configure over current protection for a desired current limit, values must be selected for the resistor and the current limit threshold. The value of the over current detection shunt resistor is a tradeoff between headroom for the motor operation and robustness of the detection blocks. For a given current limit, enough change in voltage must be generated by the motor current to accurately detect the change with the comparator. However, increasing the resistor increases the ground voltage of the inverter and reduces the headroom to drive the motor. The current limit threshold and resistor value are related by the following equations, where gain is the gain of the PGA, Current is the desired limit, and vref is the level shifted reference voltage.

current limit threshold

R * Gain * Current

vref

Equation 1

R

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threshold vref Gain * Current

For the three phase motor high voltage power module board in this application and a 2 A over current protection limit, the shunt resistor R1 is selected to be 0.02 Ω and the PGA configured to a gain of 8. This gives a current threshold voltage of 0.02 Ω * 8 * 2 A = 320 mV + VREF = 320 mV + 1.65 V = 1.97 V. To generate this voltage, the current limit threshold DAC (VDAC8) output is set to a value of 82 in the firmware. The over current protection mechanism implemented in PSoC 3 hardware is an on-chip low cost solution.

PSoC 3 PI Closed Loop Speed Control The PI control algorithm is very useful in a continuous control system. There are two basic PI control algorithms: position mode and increment mode PI control algorithm. The following equation is a discrete expression of position mode of the PI algorithm. In the closed loop speed PI control system ek is speed error. k 1 k

K P * ek

KI *

ei

0

Equation 3

i 1

The disadvantages of the position mode PI algorithm are:

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When switching between closed loop and open loop, the system creates an impulse, which results in an unstable motor. Output of position mode PI control is related to all status in the past. The limited precision and memory of the speed calculations in the MCU creates unavoidable accuracy errors in the full position calculations.

The disadvantages can be solved by using the increment mode PI algorithm. The formula is shown in the following equation. k

k

k 1

K P * ( ek

ek 1 ) K I * ek Equation 4

Equation 2

The control increment is output, which is added to the current control input. This drives the PWM to adjust the speed of the motor. MCU implementation also becomes easier with the incremental speed control.

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Figure 7. PSoC 3 PI Closed Loop Speed Control Trigger Capture

Timer

Speed Calculation

Hall Sensor Position Feedback

Commutation

+ Speed command

PI

Power Inverter

PWM

BLDC

Firmware Architecture There is one main loop and one interrupt service routine, the Timer ISR. The Timer ISR generates an interrupt every 1 ms and triggers the speed control function. A flowchart of the firmware operation is shown in Figure 8. Figure 8. Firmware Flowchart

isr_termcount (every 1 mS)

ISR

N

Firmware Flow-Chart

Y Start

Call SpeedController()

Device Initialization

Hall Sensor 1 Falling Edge

N

Enable PWM Y Start Timers

Enable Interrupt

Update Display

Calculate Speed

Update Target Speed Read ADC (speed command)

Update iteration count

N

50 iterations? Y PI calculations

Update speed increment

Update PWM duty-cycle

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An interrupt generated by a timer every 1 ms, calls the speed control function. When the speed control function is called, it checks the tachometer timer to see if a falling edge of Hall sensor 1 is detected. The time stamp for the change in the sensor is compared to the previous time and the current speed of rotation of the motor is calculated. To add damping to the speed control for noise filtering, the speed variable (speed) is adjusted by only one step towards the measured speed. The ADC samples the speed setting voltage (on analog pin SPEEDSET). If the setting has changed, it steps the speed command by one value towards the new target for noise filtering. Every fifty iterations through the speed control loop (50 ms), the difference between the measured speed and the speed command is used to calculate the step adjustment to the PWM duty cycle using Equation 4. The step based adjustments to the PWM, measured speed,

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and speed setting dampen the instantaneous changes and produce smooth transitions in speed in response to changes in setting or rotation.

Summary Cypress BLDC motor control with PSoC 3 incorporates over current protection and closed loop speed control for an optimized solution. Over current protection, which is very important in BLDC control to avoid over current damage, is implemented with on-chip hardware. The PSoC 3 BLDC motor control solution has low total system cost and leaves significant PSoC 3 resources available for additional system functions.

References 1.

BLDC Closed-Loop Speed Control Based on CY8C24x33, Bill Jiang, Jeremy Huang and XiaoPing Weng, AN42102, Cypress.

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Appendix Schematic Figure 9. Three Phase Motor High Voltage Power Module Schematic (for use with CY8CKIT DVK1)

Demo Board Figure 10. Three Phase Motor High Voltage Power Module

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Figure 11. Three Phase Motor High Voltage Power Module and CY8CKIT DVK1

DVK Setup On the DVK connect:

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VR to P0_2 SW1 to P0_3 SW2 to P0_4 Figure 12. Project Pinout for Three Phase Motor High Voltage Power Module and CY8CKIT DVK1

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Document History ®

Document Title: PSoC 3 Sensored BLDC Motor Control – AN53595 Document Number: 001-53595 Revision

ECN

Orig. of Change

Submission Date

Description of Change

**

2712427

IQS

05/29/09

New application note

*A

2762558

IQS

09/11/09

Updated screenshots to Creator Beta 3.

*B

3009069

IQS

08/24/10

Updated screenshots to Creator Beta 5.

*C

3264782

RLRM

06/03/11

Updated screenshots to Creator 1.0 and added additional text to document.

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