## Programming Languages

Programming Languages Dr. Michael Petter Exercise Sheet 2 WS 2016/17 Assignment 2.1 MESI-Protocol. Take the example from slide 23 of the lecture and...
Author: Leon Gilmore
Programming Languages Dr. Michael Petter Exercise Sheet 2

WS 2016/17

Assignment 2.1 MESI-Protocol. Take the example from slide 23 of the lecture and start with the cache state, where CPU B exclusively has a and b in its cache. Assume the execution B.1 A.1 A.2 B.1 B.2. Draw a happened-before diagram without any store/invalidate buffers. Solution 2.1 a=1

cac he

I a b I

cac he

E0 a b E0

S1

M1

write back

write back

S1

read respon se invalidate a ck

B

b=1

A

S1

I S1

I

b==0

b==0

a==1

Assignment 2.2 Dekker. Draw a happened-before diagram for the Dekker algorithm describing an interaction of two threads for a case where one of the threads succeeds to enter the critical section. Assume the hardware to be sequentially consistent. In the beginning, all variables have a value of zero and are in shared state.

T1

S0

ck write ba

I

S1 M0 S0

M1

cac he

S0 f [0] S0 f [1] turn S0

S1

M1 I

S1 S1 M1

f[1]==1

invalidate invalida invalida te ack te invalidate ack

cac he

Solution 2.2 f[0]=1; T0 S0 f [0] f [1] S0 S0 turn

f[1]=1;

f[0]==1

turn!=1 f[1]=0; 1

Assignment 2.3 MESI-Protocol. Consider the following example program with Threads A and B executing a() and b(), respectively: struct G { int b=0; int a=0; }; void a(){ G.b=1; int rega=G.a; // * }

void b(){ G.a=1; int regb=G.b; // * }

1. Devise a configuration of the underlying machine model, such that a sequence of instructions, reaching the respective program points * lead to both the variables rega and regb containing the value 0. 2. Draw a happened-before diagram of a sequence of instructions that lead to this state.

cac he

B

M1 []

[ b=1 ]

I

M1 []

[ a=1 ]

G.a=1; Invalidate buffers;

I te ack invalidate

S0 G.b S0 G.a store [ ]

rega=G.a;

G.b=1;

invalida

S0 G.b [ ] store S0 G.a

cac he

A

invalidate invalida te ack

Solution 2.3 Store buffers;

regb=G.b;

2

rega=G.a; M1 [a]

invalidate invalida te ack

cac h

I

cac h

B

I M1

e

S0 G.b S0 G.a invalid [ ]

[]

ack invalidate

S0 G.b invalid [ ] S0 G.a

invalida te

G.b=1;

e

A

[]

[b] G.a=1;

regb=G.b;

Assignment 2.4 Dekker Implementation.