PROCESSOR

Introduction to PROCESSOR ORGANIZATION AND OPERATION

• The Central Processing Unit (CPU) of a computer is a general purpose processor with instruction set. • The primary function of a processor, such as the CPU of a computer is to execute sequences of instructions stored in main memory, which is external to the CPU • The CPU must first fetch an instruction from memory before it can be executed • The sequence of operations involved in processing an instruction constitutes an instruction cycle, which can be subdivided into two major phases: – the fetch cycle and – the execution cycle MICROPROCESSORS

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Begin

Processor operation Are there instructions awaiting execution?

No

• The instruction is obtained from main memory during the fetch cycle • The execution cycle includes decoding the instruction, fetching any required operands, and performing the operation specified by the instruction's opcode • The behavior of the CPU during an instruction cycle is defined by a sequence of microoperations, each of which typically involves a register transfer operation

Yes

Overview of CPU behavior

Fetch the next instruction

Fetch cycle

Execute the instruction

Execute cycle

No Are there interrupts requiring service?

Yes Transfer control to interrupt handling program MICROPROCESSORS

Program transfer 3

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Block diagram of a general purpose processor structure

Processor time units • State (CPU cycle time) – The time tCPU required for the shortest well-defined CPU microoperation (reciprocal of tCPU is the CPU clock rate). – A micro-operation typically involves a register transfer operation

Output Data

Control signals on system bus

Condition flags

• Machine cycle – Time interval for finish an intermediate operation, such as read/write memory, or read/write IO ports. – Fetch instruction = the first machine cycle of every instruction cycle. – Usually a machine cycle implies an external transfer of the processor.

Data Processing Unit (A L U and registers)

Control Unit

• Instruction cycle: – The sequence of operations involved in processing an instruction. – Instruction cycle include = fetch instruction + execution. – An instruction has many machine cycles.

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Input Data

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An simplified accumulator-oriented CPU

Synchronization of CPU with the rest of the computer subsystems

Control unit

Data Processing Unit

1.

Signals from system bus

Control signals internal to CPU

Internal control signals

ALU

Elementary level of the CLOCK signal applied to CPU

Control circuits

AC IR

2.

Control and synchronization signals for data transfer on the system buses (with memory and IO ports)

3.

Interrupt signals, for synchronization with external events.

DR

PC

AR

To main memory and I/O devices MICROPROCESSORS

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Start

Operation of the simple CPU AC← ←f(AC,RD)

CPU activated ?

Extensions to the simple accumulatorbased CPU

No

Yes AR←PC

Launch address

DR←M(AR)

Read memory

No

Yes Ctrl

No Add ? Yes

AR←DR(address)

AR←DR(address)

DR←AC

DR←M(AR)

M(AR)←DR

AC←AC+DR

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Jump ?

2. Execute Cycle

PC←DR(address)

fixed-point multiplication and division floating-point arithmetic

Special status and control registers – –

Status register (condition code or flag register) Control flags, or control registers

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4. Hardware support for implement and handle the data structure called stack memory.

–

3.

Operands Address information If the registers are multipurpose, the resulting machine is said to have the general register organization.

Extend the capabilities of the arithmetic-logic circuits • •

Yes

Extensions to the simple accumulatorbased CPU – –

Additional internal addressable registers for storing and manipulating: • • •

IR←DR (op-code) PC ← PC+1 Decode instruction

store AC?

ALU

1. Fetch Cycle

has a LIFO (last-in first-out) access discipline controlled by a memory address register in the CPU called a stack pointer SP SP always indicates the current "top" or entry address of the stack

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Typical CPU with general register organization Control Unit

Data processing Unit General purpose data / address registers

PC ALU Control circuits

IR

Data (buffer) register

SP

Address generation logic

AR

Status Register

5. Facilities can be provided for the simultaneous processing of two or more distinct instructions. – –

the ALU can be divided into k parts to permit up to k instructions to be executed at once (pipelining) the ALU can be replicated k times to permit up to k instructions to be executed at once MICROPROCESSORS

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System Bus Control

To main memory and IO devices MICROPROCESSORS

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External links of CPU (interfacing with external word) C

C

S

CPU

Din

• • • • • •

S

CPU I

I

A typical set of condition-code flags

Din

Dout

Sign (S) Zero (Z) Parity (P) OVerflow (V) Carry (C) Auxiliary Carry (AC)

Dout Bi-directional data bus

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Examples for setting condition flags

decimal 07+ 05 --12

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Examples for setting condition flags decimal 1208 -04

NBCD binary code 0000 0111+ 0000 0101 --------------S=0, Z=0, P=1, V=0, C=0, AC=0 0000 1100 + (>1001) 0110 Decimal correction --------------0001 0010

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NBCD binary code 0001 00101000 ---------------S=0, Z=0, P=1, V=0, C=0, AC=1 0000 1010 0110 Decimal correction --------------0000 0100

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Examples for setting condition flags decimal (signed) + 8+ - 128 ---- 120

Examples for setting condition flags decimal (signed) (unsigned)

binary (unsigned) 8+ 128 ---136

0000 1000 + 1000 0000 ------------1000 1000

- 72 + + 104 ---+ 32

S=1, Z=0, P=1, V=0, C=0, AC=0

184 104 ---288

binary

+

1011 1000 + 0110 1000 ------------0010 0000

S=0, Z=0, P=0, V=0, CY=1, AC=1

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OVERFLOW FLAG

OVERFLOW FLAG Input

x n −1 x n− 2 ...x 0 +

z i = xi ⊕ y i ⊕ ci

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Output

Notes

xn-1

yn-1

cn-1

zn-1

cn

V

y n −1 y n−2 ... y 0

0

0

0

0

0 01

0 0

0

z n −1 z n−2 ...z 0

0 1

1

0

1

0

1

0

0

0

1

1

0

1

0

1

0

0

1

0

0

1

0 1

0 10

1 11

0

1

1 00

1

1

1

1

1

1

0

0 ≤ i ≤ n − 1, c 0 = 0

c i +1 = xi y i + xi c i + y i c i

Add two positive numbers ⇒ positive

Add two negative numbers ⇒ negative

• For the sign bit sum we want the same equations z n −1 = x n −1 ⊕ y n −1 ⊕ c n −1 MICROPROCESSORS

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V = c n −1 ⊕ c n

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