Author: Michal Lucki Title: Principles of sequential logical circuits Compiled by: České vysoké učení technické v Praze Faculty of Electrical Engineering Contact address: Technicka 2, Prague 6, Czech Republic

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EXPLANATORY NOTES

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ANNOTATION The goal of this module is to introduce the principles of sequential logics. Selected aspects of more advanced logic circuits, such as Mealy or Moore machine, particular design steps, minimization algorithms are discussed in details.

OBJECTIVES After studying this module, a student should know the principles of operation of common sequential circuits, such as Mealy or Moore machines, devices with clocks, flip-flops etc. A student should be familiar with design steps and algorithms of minimization of states of a sequential device. The basic knowledge on combinational logics and Boolean algebra is assumed. Students should be able to solve tasks, to specify type of a machine and its states, to determine state diagrams, tables of transitions, to minimize number of states and encode output them. Those steps are necessary to practical implementations.

LITERATURE [1]

GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets, IEEE Press Understanding Science & Technology Series, Mar 16, 1998

[2]

STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, Mar 7, 2011, ISBN-10: 3642116817

[3]

HASSOUN, S., SASAO, T.: Logic Synthesis and Verification (The Springer International Series in Engineering and Computer Science), Kluver Academic Publisher, Nov. 1, 2001, ISBN-10: 0792376064

[4]

HACHTEL, G., SOMENZI, F.: Logic Synthesis and Verification Algorithms, Springer, Feb 10, 2006, ISBN-10: 0387310045

[5]

KOHAVI, Z., JHA, N.: Switching and Finite Automata Theory, Cambridge University Press, 2009, ISBN-10: 0521857481

[6]

HOLDSWORTH, B., WOODS, C.: Digital Logic Design, Fourth Edition, Dec. 17, 2002, Integra Software Services, UK Printed, ISBN-10: 0750645822

[7]

PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, Sep. 17, 2010, ISBN-10: 0262014335

[8]

Nelson, V., Nagle, H., Carroll, B., Irwin, D.: Digital Logic Circuit Analysis and Design, Mar 18, 1995, ISBN-10: 0134638948

Index 1 Introduction .......................................................................................................................... 6 1.1

Assumed knowledge (1/2) .......................................................................................... 6

1.2

Assumed knowledge (2/2) .......................................................................................... 8

1.3

Task: sequential logic device solved as a combinational circuit (1/2) ..................... 11

1.4

Task: sequential logic device solved as a combinational circuit (2/2) ..................... 13

2 Sequential logics ................................................................................................................. 14 2.1

General design stages of sequential logics ............................................................... 14

2.2

Sequential logic devices ........................................................................................... 15

2.3

Transformation of a Mealy machine into a Moore machine .................................... 17

2.4

Task: binary adder – specification of a state diagram and a table of transitions ...... 18

2.5

Task: specification of states and transitions of a binary comparator ....................... 20

2.6

Case study – sequential logics in a factory............................................................... 21

2.7

Case study – sequential controller for pumps .......................................................... 23

3 Optimization of finite state sequential machines............................................................. 25 3.1

Transformation of a transition table into a triangle table ......................................... 25

3.2

Verification of non-contradicting states in a triangle table ...................................... 27

3.3

Re-grouping of non-contradicting states .................................................................. 28

3.4

Minimization of transition table ............................................................................... 29

3.5

New alphabet ............................................................................................................ 30

3.6

Task: optimization of a synchronic counter (1/3) .................................................... 31

3.7

Task: optimization of a synchronic counter (2/3) .................................................... 33

3.8

Task: optimization of a synchronic counter (3/3) .................................................... 35

3.9

Encoding of a sample transition table of a Moore machine ..................................... 36

4 More advanced sequential devices .................................................................................... 38 4.1

D-type flip-flop......................................................................................................... 38

4.2

D-type flip-flop with asynchronous/synchronous clear ........................................... 39

4.3

JK and T flip-flops ................................................................................................... 40

4.4

Modulo-16 binary counter ........................................................................................ 41

4.5

Shift registers (SIPO) ............................................................................................... 43

4.6

Shift registers (SISO) ............................................................................................... 45

5 Final test .............................................................................................................................. 46

1 Introduction 1.1 Assumed knowledge (1/2) A student should be familiar with the fundamentals presented in the previous module entitled „Fundamentals of combinational logics“. Basic knowledge on Boolean algebra, binary codes, operation of logical gates, interpretation of truth tables, minimization of Karnaugh maps, and principles of operation of a simple latch or a multiplexor is assumed. For better comprehension, let us remind you some of the most necessary background information on combinational logics, which applies to sequential logics and more advanced digital devices.

Boolean algebra y = a & 0 → y = 0, y = a & 1

→ y = a, y = a | 0 → y = a, y = a | 1 → y = 1

4-position BCD particular bits of code words are originated by the conversion of decimal values, starting with the most significant bit at the left hand (23, 22, 21, 20 = 8, 4, 2, 1). 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111

4-position Gray code is a binary system, in which two successive code words differ in one bit. 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000. 3- or 2-position code words can be derived from the right-hand bits of a 4-position Gray code.

Truth table is a mathematical expression used to compute the functional values of logical functions. It contains a column for each input variable (for example a, b), and one or more final columns for all of the possible results of the logical operations. Each row contains one combination of input variables (0s and 1s), and the result of the operation – true (1) or false (0).

Sample truth table.

7

1.2 Assumed knowledge (2/2) Primitive gates AND – the output is true (1) if all the inputs are true. It operates as a logical multiplication. OR – the output is true (1) if at least one of the inputs (or more) is true. It operates as a logical sum. XOR – known as an exclusive OR. It results with 1 if one of the inputs is 1 and the other is 0. True output excludes the case when both inputs are true. NAND – the negation of an AND (AND in series with NOT). NOR – the negated OR. XNOR – The negation of XOR. Known as NXOR.

8

Primitive gates.

Karnaugh map is a form of representation of logical functions used for reduction of mathematical description of logical function and the minimization of number of logical gates in practical implementations. Karnaugh maps offer an overview on the logical states that could be dropped, because they are covered by some other expressions.

9

Sample 4-variable Karnaugh map.

10

1.3 Task: sequential logic device solved as a combinational circuit (1/2) Some tasks dealing with sequential logics can be solved as combinational logics. Let us consider a heater with two sensors of temperature. The first sensor indicates that temperature is above/below 15°C, the other one indicates temperature above/below 25°C. The heater is switched automatically on, if temperature falls below 15°C and it is switched off if temperature reaches 25°C. There is no manual switch and no flame indicator. Two variables are introduced, in the contrary to the previous task, variables are low-active, they activate actions at the value of logic 0: Solution: Input variables: T1 = 0, temp < 15°C OR 1, temp > 15°C T 2 = 0, temp < 25°COR 1, temp > 25°C

Output variable is: Y = 0, not heating, disabledby signal fromT 2 OR 1, heating, activated by signal fromT1

First sensor is OFF until the temperature of 15°C is reached. If temperature T is from the range (15, 25), first sensor is ON, if temperature is >25, both sensors are ON. Activation is by T1, deactivation is by T2. Table describing operation of a heater:

Truth table.

There are two possible outputs for the input combination “10”. The problem occurs because of a hysteresis. For temperature 15