Practical Digital Pre-Distortion Techniques for PA Linearization in 3GPP LTE Jinbiao Xu Agilent Technologies Master System Engineer
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Agenda
• • • •
Digital PreDistortion----Principle Crest Factor Reduction Digital PreDistortion Simulation Digital PreDistortion Hardware Verification
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Digital Pre-Distortion----- Principle Linear Response
Output Power
Saturation
Psat Pout -pd
Operating region with predistortion
Pout Operating region without predistortion
Input Power Output Phase Desired Output
Linear Output
θo-pd = k θout
Pi
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Pi-pd
Input Power
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Digital Pre-Distortion----- Principle The DPD-PA cascade attempts to combine two nonlinear systems into one linear result which allows the PA to operate closer to saturation. The objective of digital predistorter is to have y (t ) ≈ Cx(t ) , where C is a constant.
The most important step is to extract PA nonlinear behavior accurately and efficiently.
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Memory Polynomial Algorithm •
• •
As the signal (such as 3GPP LTE) bandwidth gets wider, power amplifiers begin to exhibit memory effects. Memoryless (LUT) pre-distortion can achieve only very limited linearization performance. Volterra series is a general nonlinear model with memory. It is unattractive for practical applications because of its large number of coefficients. Memory polynomial reduces Volterra’s model complexity. It is interpreted as a special case of a generalized Hammerstein model. Its equation is as follows: K
Q
z (n) = ∑∑ akq y (n − q ) y (n − q )
k −1
K is Nonlinearity order and Q is Memory order
k =1 q = 0
Memory Polynomial Structure
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Polynomial Structure
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Signal Training to derive the Memory Polynomial 1. Pre-distorter training: Nonlinear coefficients are extracted from the PA input and PA output waveforms (ie – on real physical behavior) 2. Copy of PA : The DPD model accurately captures the nonlinearity with memory effects Memory Polynomial Coefficients
aˆ = (U H U ) −1U H z
[
aˆ = aˆ10 ,L, aˆ K 0 ,L, aˆ1Q ,L, aˆ KQ
z = [z (0), z (1), K , z ( N − 1)]
T
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]
T
y (n − q) y (n − q ) u kq (n) = G G
k −1
[
u kq = u kq (0), u kq (1),L , u kq ( N − 1)
[
U = u10 ,L, uK 0 ,L, u1Q ,L, uKQ
]
T
]
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Crest Factor Reduction (CFR) Concepts • Spectrally efficient wideband RF signals may have PAPR >13dB. • CFR preconditions the signal to reduce signal peaks without significant signal distortion • CFR allows the PA to operate more efficiently – it is not a linearization technique • CFR supplements DPD and improves DPD effectiveness • Without CFR and DPD, a basestation PA must operate at significant back-off from saturated power to maintain linearity. The back-off reduces efficiency Benefits of CFR 1. PAs can operate closer to saturation, for improved efficiency (PAE). 2. Output signal still complies with spectral mask and EVM specifications
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Crest Factor Reduction (CFR) Concepts
If you can reduce the Peak-to-Average Ratio of the signal, then for a given amplitude Peak, you can raise the Average power (up & to the right, above) with no loss in signal quality. Thus, CFR enables higher PA efficiency by reducing the back-off, often by 6dB Copyright Agilent Technologies 2010 8
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Crest Factor Reduction for Multiple-Carrier Signals • • •
Multiple-Carrier Signals (such as GSM, WCDMA, WiMAX) already have high PAPR. In the future, they will also include multiple waveforms (ie - LTE with 3G WCDMA). Therefore CFR will increase in importance for Multi-Carrier PA (MCPA) linearization.
CFR algorithm for multiple carrier signals • • • •
PW (Peak Windowing)-CFR NS (Noise-Shaping) -CFR PI (Pulse Injection)-CFR PC (Peak Cancellation)-CFR
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CFR for 3GPP LTE DL OFDM Signal • Controls EVM and band limits in the frequency domain. • Constrains constellation errors, to avoid bit errors. • Constrains the degradation on individual sub-carriers. • Allows QPSK sub-carriers to be degraded more than 64 QAM subcarriers. • Does not degrade reference signals, P-SS and S-SS. • All control channels (PDCCH, PBCH, PCFICH and PHICH) adopts QPSK threshold.
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LTE CFR (Crest Factor Reduction) 0+0*j DC Value=0 [0+0* j]
ifft1 FFTSize=4096 [DFTSize] Size=4096 [DFTSize] Direction=Inverse FreqS equence=0-pos-neg
G2 Gain=1
A 0+0*j
G3 Gain=1
Qm
SC_St at us
DPD_LTE_CFR_Post Pr oc r fe
FFT
A3 BlockS izes=1;300;3495;300 [[1,Half_UsedCarriers,DFT_zeros,Half_UsedCarriers]] zeros Value=0 [0+0* j]
ifft2 FFTSize=4096 [DFTSize] Size=4096 [DFTSize] Direction=Inverse FreqS equence=0-pos-neg
out put
A
A2 BlockSizes=300;300 [[Half_UsedCarriers, Half_UsedCarriers]]
fft FFTSize=4096 [DFTSize] S ize=4096 [DFTSize] Direction=Forward FreqSequence=0-pos-neg
n i put
out put
DPD_ Rad iu s Cp il
DPD_RadiusClp i ClippingThreshold=16.5e-6 [ClippingThreshold]
FFT
FFT
n i put
D1 Bandwidth=BW 10 MHz [Bandwidth] OversamplingOption=Ratio 4 [OversamplingOption] CyclicPrefix=Normal [CyclicPrefix] UE1_MappingType=0;0;0;0;0;0;0;0;0;0 [UE 1_MappingType] OtherUEs_MappingType=0;0;0;0;0 [OtherUEs_MappingType] RS_EPRE=-25 [RS_EPRE] PCFICH_Rb=0 [PCFICH_Rb] PHICH_Ra=0 [PHICH_Ra] PHICH_Rb=0 [PHICH_Rb] P BCH_Ra=0 [PBCH_Ra] P BCH_Rb=0 [PBCH_Rb] PDCCH_Ra=0 [PDCCH_Ra] PDCCH_Rb=0 [PDCCH_Rb] PDSCH_PowerRatio=p_B/p_A = 1 [PDSCH_P owerRato i] UEs_Pa=0;0;0;0;0;0 [UEs_Pa] PSS_Ra=0 [PSS_Ra] SSS_Ra=0 [SSS_Ra] EVM_Threshold_QPSK=0.1 [EVM_Threshold_QPSK] EVM_Threshold_16QAM=0.1 [EVM_Threshold_16QA M] EVM_Threshold_64QAM=0.1 [EVM_Threshold_64QA M] OutOfBandAlgorithm=Armstrong algorithm
Simulation Results LTE Downlink 10MHz, Sampling Rate 61.44MHz, QPSK, EVM threshold 10%
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DPD Simulation Workspace Step 1 is to Generate Waveform for DPD
Step 3 is for DUT Model Extraction
Step 4 is for DPD Response
Compared with hardware verification tool, simulation tool does not include Step 2 and Step 5. Hardware verification toll will be introduced later.
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LTE DPD simulation for a memoryless nonlinear PA Fc
T
R5 File='Step3_DPD_Coefficients_Imag.txt Periodic=YES
Spe ctrum Ana ly z e r
Cx
Im
Env
Re S4 SampleRate=122.9e+6Hz [SamplingRate]
R6
AfterDPD Mode=TimeGate Start=0s SegmentTime=50µs
C3 Fc=2GHz
R4 File='Step3_DPD_Coefficients_Real.txt Periodic=YES
Fc
DPD_ Co ef
PA_ IN
Env
Cx
Spe ctrum Ana ly z e r
Cx
Env
DPD_ In p ut
D1 MemoryOrder=7 NonlinearOrder=9 NumOfInputSamples=61440 [NumOfInputSamples]
E1
Fc
T
PA_ OUT
DPD_PAModel
DPD_ Outp ut
DPD_PreDistorter
DPD_PAModel_1
S1 SampleRate=122.9e+6Hz [SamplingRate]
C2 Fc=2e+9Hz [FCarrier]
AfterDPD_PA Mode=TimeGate Start=0s SegmentTime=50µs
Pow10 Math G28 {Gain@Data Flow Models} Gain=0 [pPowers(1)]
M12 {Math@Data Flow Models} FunctionType=Pow10
G23 {Gain@Data Flow Models} Gain=-1.159 [pPars(1)]
Pow10 Math G26 {Gain@Data Flow Models} Gain=1 [pPowers(2)]
M16 {Math@Data Flow Models} FunctionType=Pow10
G22 {Gain@Data Flow Models} Gain=0.917 [pPars(2)]
Pow10 Math G27 {Gain@Data Flow Models} Gain=2 [pPowers(3)]
M15 {Math@Data Flow Models} FunctionType=Pow10
G21 {Gain@Data Flow Models} Gain=-1.746 [pPars(3)]
Pow10 Math G24 {Gain@Data Flow Models} Gain=4 [pPowers(4)]
Log10 Math L3 {Limit@Data Flow Models} K=1 Bottom=0 Top=0.86 [pXmaxVolt] LimiterType=linear
M17 {Math@Data Flow Models} FunctionType=Log10
M14 {Math@Data Flow Models} FunctionType=Pow10
G20 {Gain@Data Flow Models} Gain=0.992 [pPars(4)]
Pow10 Math G25 {Gain@Data Flow Models} Gain=6 [pPowers(5)]
M13 {Math@Data Flow Models} FunctionType=Pow10
G19 {Gain@Data Flow Models} Gain=-0.155 [pPars(5)]
A2 {Add@Data Flow Models}
PA_OUT {DATAPORT} Data Type=Complex Bus=NO
Phase Mag
EVM (dB)
P1 {PolarToC x@Data Flow Models} PA_IN {DATAPORT} Data Type=Complex Bus=NO
Phase
Log10 Math
Mag A3 {Add@Data Flow Models}
C2 {CxToPolar@Data Flow Models} L2 {Limit@Data Flow Models} K=1 Bottom=0 Top=0.788 [mXmaxVolt] LimiterType=linear
M2 {Math@Data Flow Models} FunctionType=Log10
Pow10 Math G18 {Gain@Data Flow Models} Gain=0 [mPowers(1)]
M3 {Math@Data Flow Models} FunctionType=Pow10
G1 {Gain@Data Flow Models} Gain=31.623 [mPars(1)]
A1 {Add@Data Flow Models}
M1 {Mpy@D ata Flow Models}
Pow10 Math 10e-201
G17 {Gain@Data Flow Models} Gain=1 [mPowers(2)]
M4 {Math@Data Flow Models} FunctionType=Pow10
G2 {Gain@Data Flow Models} Gain=-72.068 [mPars(2)]
C1 {Const@Data Flow Models} Value=1e-200
Pow10 Math G16 {Gain@Data Flow Models} Gain=2 [mPowers(3)]
M5 {Math@Data Flow Models} FunctionType=Pow10
G3 {Gain@Data Flow Models} Gain=254.726 [mPars(3)]
Pow10 Math G15 {Gain@Data Flow Models} Gain=4 [mPowers(4)]
M6 {Math@Data Flow Models} FunctionType=Pow10
G6 {Gain@Data Flow Models} Gain=-1107.963 [mPars(4)]
ACLR (dB)
Pow10 Math G14 {Gain@Data Flow Models} Gain=6 [mPowers(5)]
M7 {Math@Data Flow Models} FunctionType=Pow10
G5 {Gain@Data Flow Models} Gain=2956.358 [mPars(5)]
Pow10 Math G13 {Gain@Data Flow Models} Gain=8 [mPowers(6)]
M8 {Math@Data Flow Models} FunctionType=Pow10
G4 {Gain@Data Flow Models} Gain=-4462.485 [mPars(6)]
Pow10 Math G12 {Gain@Data Flow Models} Gain=10 [mPowers(7)]
M9 {Math@Data Flow Models} FunctionType=Pow10
G9 {Gain@Data Flow Models} Gain=3782.968 [mPars(7)]
Pow10 Math G11 {Gain@Data Flow Models} Gain=12 [mPowers(8)]
M10 {Math@Data Flow Models} FunctionType=Pow10
G8 {Gain@Data Flow Models} Gain=-1653.647 [mPars(8)]
Pow10 Math G10 {Gain@Data Flow Models} Gain=14 [mPowers(9)]
M11 {Math@Data Flow Models} FunctionType=Pow10
G7 {Gain@Data Flow Models} Gain=281.85 [mPars(9)]
G29 {Gain@Data Flow Models} Gain=1
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LTE DPD simulation for a nonlinear PA with memory R5 File='Step3_DPD_Coeffic ients _Imag.tx t Periodic =YES
Im Re R6
R4 Fc t File='Step3_DPD_Coeffic ients _Real.tx Periodic =YES Env
E1
Fc
Fc
Cx
DPD_O ut put
DPD_ Pre Di s to rter
Amplifier
Env
Env
Fc
T
DPD_Coef
Cx
Spec trum Analyzer
Cx
Cx
Env
DPD_I nput
D1 MemoryOrder=7 NonlinearOrder=9 NumOfInputSamples =61440 [NumOfInputSamples ]
C8 Fc =0.2e6Hz
Amplifier1 GainUnit=dB Gain=30 [GaindB] Nois eFigure=0 GCTy pe=none dBc1out=10dBm PdBmNoMem=-30 [PdBmNoMem] PdBmMax Mem=10 [PdBmMax Mem] MaxRis eTC=16.28e-9s [Max RiseTC] Max FallTC=16.28e-9s [Max FallTC]
E4
S1 SampleRate=122.9e+6Hz [SamplingRate]
vn i
input {DATAPORT} Data Ty pe=Env elope Signal Bus =NO
Mag Env
Amplifier
Cx
v out
R1 {Ris eFallTC@SV_VC_TC Models } PdBmNoMem=10 [PdBmNoMem] PdBmMax Mem=30 [PdBmMax Mem] Max Ris eTC=10e-6s [MaxRiseTC] Max FallTC=100e-6s [Max FallTC] RefR=50O [RefR]
c ontrol {DATAPORT} Data Ty pe=Floating Point (Real) Bus =NO
Mag Cx
C3 {Cx ToPolar@Data Flow Models}
E1 {Env ToCx @Data Flow Models }
Env
Phase
Phase
Fc A1 {Amplifier@Data Flow Models } Gain=1 NoiseFigure=0 [Nois eFigure]
RiseFallTC
AfterDPD_PA Mode=TimeGate Start=0s SegmentTime=50µs
C2 Fc =2e+9Hz [FCarrier]
Fc P1 {PolarToCx @Data Flow Models }
Amplifier output {DATAPORT} Data Ty pe=Env elope Signal Bus =NO A2 {Amplifier@Data Flow Models } GainUnit=v oltage [GainUnit] Gain=1 [Gain]
C1 {CxToEnv @Data Flow Models} Fc =0.2e6Hz
EVM (dB)
ACLR (dB)
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DPD Hardware Verification Flowchart Create DPD Stimulus
Capture DUT Response
DUT Model Extraction
DPD Response
Verify DPD Response
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DPD HW Flowchart consists of 5 steps: • Step 1 (Create DPD Stimulus) is to download waveform (LTE or User defined) into ESG/MXG. • Step 2 (Capture DUT Response) is to capture both waveforms before power amplifier and after power amplifier from PSA/MXA/PXA by using VSA89600 software. • Step 3 (DUT Model Extraction) is to extract PA nonlinear coefficients based on both captured PA input and PA output waveforms and then to verify DPD by using PA nonlinear coefficients. • Step 4 (DPD Response) is to download the waveform (LTE or User Defined) after predistorter (by using PA nonlinear coefficient from Step 3) into ESG/MXG, this real signal passes through the PA DUT, capture PA output waveform from PSA/MXA/PXA by using VSA89600 software. • Step 5 (Verify DPD Response) is to show the performance improvement after DPD. SystemVue DPD Jinbiao XU May 26, 2010
DPD Hardware Verification Workspace Structure
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DPD Hardware Verification Platform 1. PA input signal capture Signal source: LTE 10MHz
Agilent MXG/ESG
10MHz Reference
PSA/MXA/PXA
External Trigger
2. PA output signal capture MXG/ESG
PSA/MXA/PXA
10MHz Reference External Trigger
Attenuator
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DPD Hardware Verification – LTE (Step 1) Step 1: Create Stimulus
The CFR must be enable in LTE source. LTE paramters (such as bandwidth, Resource Block allocation and etc) can be set. The download waveform transmit power, length also can be set.
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DPD Hardware Verification – LTE (Step 2) Step 2: Capture DUT Response Firstly, connect the ESG directly with the PSA/PXA and click the “Capture Waveform” button in the “Capture PA Input” panel in the GUI. The captured signal is the input of the PA DUT. Then, connect the ESG with the DUT, and then connect the DUT with the PSA/PXA and click the “Capture Waveform” button in the “Capture PA Output” panel in the GUI. The captured signal is the output of the PA DUT. These I/Q files are stored for further usage.
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DPD Hardware Verification – LTE (Step 3) Step 3: DUT Model Extraction
DPD Verification AM-AM This step is to extract PA nonlinear coefficient from the PA input and PA output waveform and get the coefficients of the DPD model.
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DPD Hardware Verification – LTE (Step 4) Step 4: DUT Response
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This step is to apply the DPD model extracted in Step 3. The generated LTE downlink signal is firstly pre-distorted by the extracted model, and then downloaded into the ESG.
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DPD Hardware Verification – LTE (Step 5) Step 5: Verify DUT Response Spectrum EVM ACLR
This step is to verify the performances of the DPD (including spectrums of the DUT output signal w/ and w/o DPD, EVM and ACLR).
EVM (dB) ACLR (dB)
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Hardware Verification Results of Doherty PA
EVM (dB) ACLR (dB)
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References 1.
Lei Ding, Zhou G.T., Morgan D.R., Zhengxiang Ma, Kenney J.S., Jaehyeong Kim, Giardina C.R., “A robust digital baseband predistorter constructed using memory polynomials”, Communications, IEEE Transactions on, Jan. 2004, Volume: 52, Issue:1, page 159-165. 2. Lei Ding, “Digital Predistortion of Power Amplifiers for Wireless Applications”, PhD Thesis, March 2004. 3. Roland Sperlich, “Adaptive Power Amplifier Linearization by Digital Pre-Distortion with Narrowband Feedback using Genetic Algorithms”, PhD Thesis, 2005. 4. Helaoui, M. Boumaiza, S. Ghazel, A. Ghannouchi, F.M., “Power and efficiency enhancement of 3G multicarrier amplifiers using digital signal processing with experimental validation”, Microwave Theory and Techniques, IEEE Transactions on, June 2006, Volume: 54, Issue: 4, Part 1, page 1396-1404. 5. H. A.Suraweera, K. R. Panta, M. Feramez and J. Armstrong, “OFDM peak-to-average power reduction scheme with spectral masking,” Proc. Symp. on Communication Systems, Networks and Digital Signal Processing, pp.164-167, July 2004. 6. Zhao, Chunming; Baxley, Robert J.; Zhou, G. Tong; Boppana, Deepak; Kenney, J. Stevenson, “Constrained Clipping for Crest Factor Reduction in Multiple-user OFDM”, Radio and Wireless Symposium, 2007 IEEE Volume , Issue , 9-11 Jan. 2007 Page(s):341- 344. 7. Olli Vaananen, “Digital Modulators with Crest Factor Reduction Techniques”, PhD Thesis, 2006 8. Boumaiza, et a, “On the RF/DSP Design for Efficiency of OFDM Transmitters” , IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 7, July 2005, pp 2355-2361. 9. Boumaiza, Slim, “Advanced Memory Polynomial Linearization Techniques,” IMS2009 Workshop WMC (Boston, MA), June 2009. 10. Amplifier Pre-Distortion Linearization and Modeling Using X-Parameters, Agilent EEsof EDA
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