Performing Efficient Characterization and Verification Test of LPDDR3 Chris Loberg Tektronix
LPDDR3 Summit Santa Clara 2012
Agenda • •
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Introduction – LPDDR3 Verification Challenges Applying LPDDR3 Electrical Verification Techniques – Signal Integrity steps for evaluation of data bursts – Read & Write Burst Capture in a ranked PoP environment Performing JEDEC-Compliant Test Practices for LPDDR3 – How to consistently apply in a test environment – Pass/Fail Analysis & Reporting Accessing LPDDR3 Test Points with Good Signal Fidelity – Evaluation of available test point access options • Oscilloscope Interposers • Solder-down Probing Systems – Filter application Summary/Q&A
LPDDR3 Verification Challenges: Faster, Smaller, More output, Less power
LPDDR3 Key Features •
Speed and Capacity •
Bandwidth of 6.4 – 8.5 Gbps per die •
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x16, x32
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4, 8, 16, 32Gb Package Options
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Multiple channels, ranks – up to 346 balls
Battery Conservation •
Low Voltage (300mV – 1.2V MAX)
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Voltage Ramp and Device Initialization •
Temperature-compensated and partial array self refresh modes
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Deep power down mode which sacrifices all memory contents
Compact Packaging •
PoP and Discrete Packages
LPDDR3 Verification Challenges
Pushing the system power envelope LPDDR2: • 1.2 V • 533MHz
LPDDR3 Verification Challenges
Pushing the system power envelope LPDDR3: • 1.2 V • 800MHz
LPDDR3 Verification Challenges
Faster Clock Frequencies
LPDDR3 Verification Challenges
PHY Test Access
Signal Integrity
Bandwidth considerations for DDR Verification • LPDDR2/3 Depending on Error Tolerance Levels – 8GHz Debugging – 12.5GHz for Chipset/Controller & System Specification Reference Generation
DDR Eye Diagrams • Hexagon shaped area applied to DQ used as a keep-out zone to isolate only target rank of interest. • Use additional areas to target specific DQ patterns. Before
After
Signal Integrity
Characterizing LPDDR3 using Eye Diagrams • Tips for quick evaluation of DQ Signals
Signal Integrity
Read/Write Burst Identification
On a Trigger
Mark all Read/Write Events
Post Acquisition
Across entire recorded acquisition, apply a search algorithm to each acquired waveform, and mark reads/writes with visual delimiters
LPDDR3 Command Bus Capture & Display
Verification of Setup & Hold on Command Bus 1-16 Digital Channels – CS, CA1…CAn Timing & Placement 1-4 Analog Channels – Clock, DQ, DS Slew rate CS
DQ0
CA1
CA2
DQS0
CAn
CK
LPDDR3 Address Bus Capture & Display
Burst Detect on Command Bus Using command bus state, specific transactions can be isolated – Analysis of analog signals is then used for fine burst positioning to gate measurements
Search & Mark Capability for Cataloging Read/Write’s Suggest use of Digital Channels for Command/Address LPDDR JEDEC Measurements performed on ALL reads/writes JEDEC Tests + Debug Tools
JEDEC Test Verification of LPDDR
Verification Example
JEDEC Test Verification of LPDDR
System visibility in high ball count systems • Verification in multi-channel, multi-rank environments – Pinpoint source(s) of signal integrity concerns – Validation without re-probing using mux
34 ch 34 ch
Trigger Analog Out State 3 GHz Machine Analog CH 1 Mux
34 ch
CH 2
34 ch
4 ch CH 3
Analog In CH 1 CH 2 CH 3 CH 4
CH 4
LA
DSO
Signal Access & Probing
Keep--out Comparison of PoP & Embedded Keep Package-on-Package tends to have more clearance…
… compared to the embedded areas of a target
Signal Access & Probing
BGA Access Using Oscilloscope Interposers Unique, re-usable socket design allows for multiple chip exchanges
Signal paths and termination requirements are key and central to the designs
Modeling to predict analog performance
Oscilloscope filters to enable views with and without interposer circuit effects
Signal Access & Probing
LPDDR Interposer Support •
LPDDR2/3 increases the number of package types vs DDR2/3/4
