Page 2) 18 points. Page 3) 14 points. Page 4) 12 points. Page 5) 25 points. Page 6) 18 points. Page 7) 13 points. TOTAL out of 100

EEL3701 – Dr. Gugel Spring 2011 Exam II • • • Last Name_________________________________ First___________________ UF ID#_____________________________...
Author: Silas Watson
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EEL3701 – Dr. Gugel Spring 2011 Exam II • • •

Last Name_________________________________ First___________________ UF ID#__________________________________________

Open book and open notes, 90-minute examination to be done in pencil. No electronic devices are permitted or needed. All work and solutions are to be written on the exam where appropriate.

Point System (for instructor and TA use only)

Page 2)

18 points

_________________

Page 3)

14 points

_________________

Page 4)

12 points

_________________

Page 5)

25 points

_________________

Page 6)

18 points

_________________

Page 7)

13 points

_________________

TOTAL

_________________

out of 100

Grade Review Information: (NOTE: deadline of request for grade review is the day the exam is returned.) ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________ ________________________________________________________________________________________

1. Given the following ASM Diagram answer the questions that follow. States: S2:0 Inputs: W.L Outputs: A.H, B.L 1A. Draw a functional block diagram on the lower right to implement the design. Assume D Flip-flops are used and label your present states Qn…Q0 as needed. (6 pt.)

S0

S1 A

0

1

W

     B

S2 A,B

1B. Fill out the next state logic table for the design. Assume S3 will never be entered after power-up.

(12 pt.) W

Page 2

Q1

Q0

Q1+

Q0+

A

B

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1C. Show the logic equation and required circuit for D0.H (least significant state flip-flop input). Assume only NOR gates are available to implement the circuit and the logic equation should be in MSOP form. (7 pt.)

1D. Show the logic equation and required circuit for B.L (low true output). Assume only NOR gates are available to implement the circuit and the logic equation should be in MSOP form. (7 pt.)

Page 3

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1E. Instead of using a CPLD, assume that the design will be implemented in a 16K x 8 EPROM. All un-used address lines should be tied high. Show the EPROM connections below (left) and the memory contents (right). Recall that several of the input & output signals are low true. (4 pt., 8 pt.)

ADDR (Hex)

DATA (Hex) | | | | | | | | | | | | | | | | | |

2. Given the following ALU, answer the questions that follow.

8

IN7:0

S3 -­‐OE_M -­‐LD_A -­‐OE_A CLK -­‐LD_B CLK

REGA -­‐LD       D7:0 -­‐OE

8

REGB -­‐LD       D7:0 Q7:0

8

S2 S1 S0

8

8 IN1

ALU

Page 4

IN2

OUT7:0 D7:0

CLK

MUX

REGC

Q7:0

MUX  Select S3  =  0,  IN7:0  =>  *Mux  Out S3  =  1,  REGC  Q7:0  =>  *Mux  Out *When  –OE_M  =  1,  else  if  –OE_M  =  0      then  Mux  Out  =  Hi  Z  (tri-­‐state). REG  A/B  Signals -­‐LD_A/B  =  load  data  from  D7:0 -­‐OE_A            =  output  data  onto  D7:0

ALU  Function

S2  S1  S0 0      0      0        OUT  =  IN1 0      0      1        OUT  =  IN2 0      1      0        OUT  =  IN1  PLUS  IN2 0      1      1        OUT  =  Complement  (IN1) 1      0      0        OUT  =  IN1  multiplied  by  2 1      0      1        OUT  =  IN1  divided  by  2 1      1      0        OUT  =  IN1  PLUS  1 1      1      1        OUT  =  IN1  MINUS  1

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2A. Assuming that four DIP switches will be used to simulate an instruction register (IR3:0), draw the components inside the new controller block in the CPU that will be used to generate all the register and mux input signals shown on the previous page. Assume that the controller will be implemented in a 1K x 16 EPROM and that there are 29 states in the Controller ASM Diagram. (7 pt.)

2B. Given the following instructions below, create an ASM Diagram for the Controller block. In the ASM Diagram states, show only the ALU & Register signals that are true for a particular state. The IR3:0 bits will be switched by hand during the first state in the ASM and therefore are inputs to your controller. (3, 9, 6 pt.) IR3:0 = 0; In7:0 => RegA

Page 5

IR3:0 = 1; Average (RegA, RegB) => Reg A

IR3:0 = 2; RegA + 1 => RegA

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2C. Show how the components & design required to create the Least Significant Bit of RegA. (6 pt.)

3A. You are given a CPU with A15:0, D15:0, R/-W and –DS (data strobe). The reset vector is at 9FFF Hex. i.e. After reset, this is where the address of the first instruction is fetched from memory. Implement in the system an 8K block of EPROM and 16K block of SRAM with the following available devices: 8K x 8 EPROMs and 32K x 16 SRAMs. Place the SRAM block in the highest 16K of memory and the EPROM block where it is needed for the reset vector. Draw the EPROM and SRAM blocks below and label all connections. (12 pt.)

Page 6

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3B. Show the memory ranges for each block of memory (EPROM and SRAM) and the required decode circuitry for each memory device. Make sure your signals in the decode circuit match those shown on your memory devices on the previous page. (8 pt.)

3C. What data and address must be programmed in the EPROM to facilitate the RESET Vector? i.e. At what location in the EPROM and what data value needs to be programmed such that the CPU will fetch the lowest address of the EPROM (1st instruction in ROM) after Reset. (5 pt.) EPROM Address (device is not plugged in the board) _____________ Hex Data _______________ Hex

Page 7

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