Journal of Sensor Science and Technology Vol. 24, No. 1 (2015) pp. 10-14 http://dx.doi.org/10.5369/JSST.2015.24.1.10 pISSN 1225-5475/eISSN 2093-7563

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors Chung Mo Yang, Hee Yeoun Kim, and Jae Hong Park+

Abstract This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and SF6 should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and SF6 were set at 115 W, 3500 W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, C4F8 content of 400 sccm, and a gas exchange interval of SF6/C4F8 = 2 s/3 s. Keywords: MEMS sensor, Deep reactive-ion-etching, Etching profile

1. INTRODUCTION

etch-related property changes owing to sample patterns, and loading effects result in nonuniformity of the etch rate and the

Reactive ion etching (RIE) uses planar inductively coupled

etching profile within the wafer and sidewall damage during the

plasma (ICP) as its source. ICP has attracted significant attention

etching process. In particular, the etch rate and etch profile vary

as a material for through-silicon via (TSV) technology, which is a

significantly with the plasma exposure area (open area).

high-performance technique used for 3D packaging applications

Nonuniform etch rates prevent the mass production of MEMS-

and 3D microelectromechanical sensors (MEMS) structures.

based inkjet heat [2] or the microfluidic flow paths of recently

Compared to other techniques, RIE can produce high-density

highlighted Bio-MEMS owing to the high production costs

uniform plasma over large areas and under low pressure using

associated with the use of specially produced wafers, such as

ICP, and its etching speed has continuously improved owing to

silicon on insulator (SOI), because Si wafers cannot be used for

upgrades in the equipment technology industry. RIE technology

the aforementioned reason. Moreover, the etching-profile-related

can achieve a high aspect ratio [1] through frequent passivation

sidewall damage can lead to the formation of microbubbles in the

and etching induced by plasma formation controls. However, the

flow path, resulting ultimately in its blockage and failure. Sidewall damage occurs during etching and is different from the scallop that inevitably results from the Bosch method. In previous studies

National Nano Fab Center, 335 Gwahangro Yuseong-gu, Daejeon 305-701 Korea + Corresponding author: [email protected] (Received : Dec. 30, 2014, Revised : Jan. 15, 2015, Accepted : Jan. 19, 2015)

[3], experiments were conducted with small sample-type parts. However, studies have not been conducted with 4- and 6-in wafers. The aim of this study, therefore, was to analyze and

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(http://creativecommons.org/ licenses/bync/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

subsequently reduce/eliminate the etch rate nonuniformity and sidewall damage tendencies that occur under large-area etching conditions (open area > 20%) for mass production applications.

10

J. Sensor Sci. & Tech. Vol. 24, No. 1, 2015

I 11 I

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

Therefore, this study aimed to optimize the etching profile, an important factor in the DRIE process, which is a key processing step in the production of various MEMS structures. An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters. An optimal process condition of the DRIE device must be achieved in order to solve the aforementioned problems. In this

Fig. 1. SEM image of sidewall under (a) low-frequency (LF) and (b) high-frequency (HF) conditions.

regard, Lee et al. [4] reported that they could reduce the sidewall damage by performing hydrogen annealing. However, this method involves annealing the entire structure, and hence, it results in

are simultaneously taken into consideration. In this investigation,

targeted as well as undesired changes. This problem can be

the unit of the etch rate is µm/min, and the etch rate indicates the

overcome by selecting processing conditions that minimize

etched depth per etching time of the material. Further, uniformity

sidewall damage during DRIE etching [5-9]. As such, this study

means the deviation of the etched thickness in the same etching

is aimed at determining the optimal processing parameters for

time and through the entire wafer; the unit of uniformity is %.

minimizing the damage to the etched sidewall under a low-

Therefore, the LF method was used to perform large-area

frequency (LF) condition of 380 kHz (RF generator) using a

etching (open area > 20%) in this study. Etch rates increase, in

MACS Pegasus (Sumitomo Precision Products Co. Ltd, Japan).

general, with increasing coil power; however, this phenomenon is canceled out in the case of large-area etching. An optimal etching profile for etching a large Si wafer area (open area > 20%) was

2. EXPERIMENTAL SETUP

determined by controlling various DRIE process parameters. The optimal processing condition was determined after establishing

Large-area etching (open area > 20%) under a high-frequency

correlations of the etch rate, uniformity, and sidewall damage on

(HF) condition with non-optimized processing parameters results

a 6-in Si wafer to parameters such as the coil power, run pressure,

in damage to the etched sidewall. Therefore, in this study,

platen power for passivation etching, and SF6 gas flow rate.

optimization was performed under an LF condition. The HF method, which is typically used for TSV technology, applies a

3. RESULTS AND DISCUSSIONS

high etch rate and cannot be easily adapted to processes that are sensitive to sidewall damage. With all other conditions being the same, Fig. 1(a) shows that, in contrast to the HF condition (13.56

Optimized photoresist (PR) masks and a SiO2 layer were used

MHz), etching performed under LF (380 Hz) did not incur

as etching masks in this study. Given that the etching method of

sidewall damage. The high etch rate, which is typical of the HF

the device used involves control of the plasma formation, etching

method, did not decrease significantly in the case of large-area

duration and uniformity may vary according to the intensity of the

etching under the LF condition. This result suggests that,

platen power during the initial passivation. As such, the process

compared to its HF counterpart, the LF method is more suitable

cycle ran as follows: passivation, etch 1 (boost), etch 2 (delay),

for large-area etching, provided that the etch rate and uniformity

passivation, etch 1, etch 2, and so forth. C4F8 gas was used in the

Table 1. Parameters of the DRIE process Boost (Re) SF6 (sccm)

C4F8 (sccm)

400 Cycle

Time (sec)

Run press. (Pa)

Coil (W)

Platen (W)

2

4

2500

100.115.130

400

3

6

2500

Fix

Fix

Fix

Fix

Fix

variable

SF6 (sccm)

C4F8 (sccm)

Time (sec)

Run press. (Pa)

Coil (W)

Platen (W)

9

8,9,10

2500, 3500, 4000

15

Fix

variable

variable

Fix

Delay(Si etch) 700, 800, 900 variable

X

11

J. Sensor Sci. & Tech. Vol. 24, No. 1, 2015

I 12 I

Chung Mo Yang, Hee Yeoun Kim, and Jae Hong Park

Fig. 5. Variation in etching profile with coil power.

Fig. 2. Dependence of etch rate and uniformity on platen power (relations between platen power and etch rate, and uniformity).

Fig. 6. Dependence of etch rate and uniformity on run pressure (relations between pressure and etch rate, and uniformity).

Fig. 3. Variation in etching profile with platen power.

Fig. 4 shows the dependence of the etch rate and uniformity on the coil power. The SEM images (Fig. 5) compare the corresponding sidewall damage incurred. Etch rates increase, in general, with increasing coil power; however, Fig. 6 demonstrates that this phenomenon is canceled out in the case of large-area etching. The SEM image (Fig. 5) revealed that etching at a coil power of 4000 W results in severe sidewall damage. It can be inferred that although the increase in coil power increases the etch rate owing to increased plasma formation, the accompanying increase in the Fig. 4. Dependence of etch rate and uniformity on coil power (relations between coil power and etch rate, and uniformity).

etch depth, induced by the excessive rate, results in severe sidewall damage. As shown in Fig. 6, the uniformity improves and the etch rate

passivation step, and the duration was set at 3 s. In addition, etch

decreases with increasing run pressure, which was confirmed by

1 (2 s) removes the passivating film, and etch 2 (7 s) is the actual

the result of our experiment. Moreover, the absence of sidewall

Si etching process performed using the standard recipe.

damage confirms that the run pressure does not influence its occurrence.

The platen power was varied in order to check the effect of the 2 s pre-Si etching used for removing the passivating film, and

Fig. 7 shows the results of varying the flow rate of the etching

etching cycles were performed at a platen power of 130, 115, and

gas SF6. Increasing flow rates resulted in both increased etch rates

100 W. In the actual Si etching process step, the aforementioned

and uniformity of the wafer.

standard recipe was applied with platen power, coil power, run

The processing-parameter-dependent results of the experiments

pressure, SF6 content, C4F8 content, and gas exchange interval of

performed for optimization of the etching profile in terms of etch

SF6/C4F8 set as 15 W, 3000 W, 4 Pa, 700 sccm, 400 sccm, and 2

rate, uniformity, and sidewall damage in the case of large Si area

s/3 s, respectively. Fig. 2 shows that a platen power of 100 W

etching can be summarized as follows. When LF is applied, the

yielded a better combination of etch rate and uniformity compared

platen power, coil power, and SF6 should be low, whereas the run

to that resulting from 130 W. Furthermore, the SEM cross-

pressure has little effect on the etching performance. Under the

sectional images (Fig. 3) show that there was no sidewall damage

optimal LF condition of 380 Hz, the platen power, coil power, and

after etching at either platen power.

SF6 were set at 115 W, 3500 W, and 700 sccm, respectively. In

J. Sensor Sci. & Tech. Vol. 24, No. 1, 2015

12

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

I 13 I

nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under the LF condition. The HF method, which is typically used for TSV technology, applies a high etch rate and cannot be easily adapted to processes that are sensitive to sidewall damage. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and SF6 should be low,

Fig. 7. Dependence of etch rate and uniformity on flow rate of SF6 gas (relations between flow rate of SF6 and etch rate, and uniformity).

whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and SF6 were set at 115 W, 3500 W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, C4F8 content of 400 sccm, and a gas exchange interval of SF6/C4F8 = 2 s/3 s.

ACKNOWLEDGMENT This work was supported by the Daegu Technology Business Program (ACC-2013-DGI-00557) funded by the Ministry of Science, ICT and Future Planning, the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and

Fig. 8. Etching profile at optimized condition.

Technology (grant number: 2012R1A1A2007707), and the Nano addition, the aforementioned standard recipe was applied as

Material Technology Development Program through the National

follows: run pressure of 4 Pa, C4F8 content of 400 sccm, and a gas

Research Foundation of Korea (NRF) funded by the Ministry of

exchange interval of SF6/C4F8 = 2 s/3 s. The SEM cross section in

Science, ICT and Future Planning (2012M3A7B5049567).

Fig. 8 shows the etching profile of a large Si wafer area (open area

REFERENCES

> 20%) obtained by applying the aforementioned experimentally optimized conditions.

[1] H. Jansen, M. Boer, R. Wiegerink, N. Tas, E. Smulders, C. Neagu, and M. Elwenspoek, “RIE lag in high aspect ratio trench etching of silicon”, Microelectron. Eng., Vol. 35, pp. 45-50, 1997. [2] D. Y. Choi, N. H. Kim, and S. Y. Kim, “Reduction of loading effects with the sufficient vertical profile for deep trench silicon etching by using decoupled plasma sources”, J. Mater. Process Technol., Vol. 209, pp. 5818-5829, 2009. [3] M. K. Hooda, M. Wadhwa, S. Verma, M. M. Nayak, P. J. George, and A. K. Paul, “A systematic study of DRIE process for high aspect ratio microstructuring”, Vacuum, Vol. 84, pp. 1142-1148, 2010, [4] M. M. Lee and M. C. Wu, “Thermal annealing in hydrogen for 3-D profile transformation on silicon-on-insulator and sidewall roughness reduction”, J. Microelectromech. Syst., Vol. 15, pp. 338-345, 2006. [5] C. Linder, T. Tschan, and N. F. De Rooij, “Handbook of

4. CONCLUSIONS This study aimed to optimize the etching profile, an important factor in the DRIE process, which is a key processing step in the production of various MEMS structures. An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters. The optimal processing condition was derived after establishing correlations of the etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate. Large-area etching (open area > 20%) under an HF condition with 13

J. Sensor Sci. & Tech. Vol. 24, No. 1, 2015

I 14 I

Chung Mo Yang, Hee Yeoun Kim, and Jae Hong Park

nanostructured materials and nanotechnology 1 (Synthesis and Processing)”, Academic Press, Vol. 3. pp. 23-25, 2000. [6] M. Gad-el-Hak, The MEMS Handbook, CRC Press, pp. 145-178, 2002. [7] M. Esashi, M. Takinami, Y. Wakabayashi, and K. Minami “High rate directional deep dry etching for bulk Si micromaching”, J. Micromech. Microeng., Vol. 5, pp. 5-10, 1995. [8] Y. Zhao, H. Jansen, M. de Boer, E. Berenschot, D. Bouwes,

J. Sensor Sci. & Tech. Vol. 24, No. 1, 2015

M. Gironès, J. Huskens, and N. Tas, “Combining retraction edge lithography and plasma etching for arbitrary contour nanoridge fabrication”, J. Micromech. Microeng.,Vol. 10, pp. 095022-095027, 2010. [9] J. J. Gandìa, J. Cárabe, and M. T. Gutiérrez, "Influence of TCO dry etching on the properties of amorphous-silicon solar cells”, J. Mater. Process Technol., Vol, 143, pp. 358361, 2003.

14