Session 1: Manufacturing Challenges

No Change is Innocuous Peter Elenius E&G Technology Partners 1840 E. Warner Road, Suite A105, #249 Tempe, AZ 85284 Phone:(602) 332-8272 Email:[email protected]

Dr. Ray Kruzek Radiant Technology Corporation 1335 S. Acacia Ave Fullerton, CA 92831 Phone:(714) 991-0200 Email:[email protected]

Abstract - In the semiconductor industry an axiom that is rigorously adhered to is “No Change is Innocuous”. This axiom has resulted from the many lessons learned over the years of how seemingly minor changes to the materials or processes resulted in significant or at times catastrophic impacts to either the yield or reliability of the chips produced. This paper will introduce some of the concerns that are known relative to the introduction of Pb free solders for flip chip (FC) and wafer level package (WLP) technology. As stated, these are the known topics of concern. The impacts that are not known may be larger and usually make themselves known early in the production cycle where the cost is significantly greater to fix them. Another aspect of this paper will address the reflow technology required for both the solder bumping of the wafer and the subsequent attachment of these bumped chips to either an IC (integrated circuit) package or directly to the motherboard. An important aspect of the reflow technology during the transition period (mixed use of 63Sn/Pb and Pb free) is to be able to rapidly change between reflow profiles. An example of CoO (Cost of Ownership) will be given for varying profile change over times. In some cases, a suboptimal reflow process may cause a yield loss. The cost of this potential yield loss will be shown for the FC/WLP bumping application. In summary, the axiom of “No Change is Innocuous” has a long history of being right in the semiconductor industry. Many of issues that have been foreseen have been addressed by some companies but it is still too early to know what the unknown issues are.

FC & WLP OVERVIEW FC & WLP devices are interconnected to the outside world through solder bumps. These solder bumps can range in size from 50 to 500 microns depending on the application and the pitch of the interconnection. The IC utilizes a final metal layer for both interconnection and the formation of the pad locations. The IC’s final metal is not suitable for contact with the solder due to either not being solderable (i.e., Al) or being too readily consumed (i.e., Cu, Au) by the solder. All solder bumping processes create some type of barrier layer called a UBM (Under Bump Metallurgy) between the IC’s final metal and the solder of the bump. The UBM is normally created with PVD (Physical Vapor Deposition, a.k.a. sputtering), plating or a combination of these processes.

In Figure 1 is an example of a flip chip bump structure from Flip Chip Technologies. In this case the UBM is a sputtered thin film that consists of layers of Al, NiV and Cu.1 Solder Bump

Sputtered UBM (Al/NiV/Cu)

Device Passivation

Final Metal Pad

Figure 1 - Example of FC Bump Construction

REQUIREMENTS OF THE UBM A UBM must provide the following capabilities: 1

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Adhesion to wafer passivation

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Low ohmic contact to final metal

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Robust solder barrier layer

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Final metal layer is solder wettable

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Protect IC metal from the environment

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Minimize stress on silicon

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Ability to be used on probed wafers

With the conversion to Pb free solders the most important issues are maintaining a robust solder diffusion barrier as well as minimizing the stress on the silicon. These will be discussed and some results shown in the following sections.

BUMPING PROCESSES To understand the impact of the conversion to Pb free solders to both FC and WLP technology, it is helpful to understand the technologies used to deposit the solder. Each technology has unique capabilities and limitations. Some of the technologies described below are incapable of depositing a Pb free solder and some will have significant challenges in being able to consistently produce the chosen alloy. Described below are high level descriptions of four solder deposition technologies and their inherent limitations. The reader is encouraged to review the references listed to gain a greater understanding of each of these technologies. Evaporation Evaporation of the UBM and solder bump is a technology originally practiced by IBM 2 and more recently by some of their licensees. In this process both the UBM and the solder are evaporated through a metal mask onto the wafer. Due to the low vapor pressure of tin (Sn) it is difficult to cost effectively evaporate high Sn content solders. High Sn content solders include both 63Sn/Pb as well as the proposed Pb free alloys. Even if the high Sn content solder could be deposited, the UBM used in these systems is optimized for a bump Pb content of greater than 95%. Due to these limitations and other shortcomings this technology is being phased out. Plating In preparation for plating3 a PVD deposition of a seed layer is done and then a thick photo-resist layer is patterned. The first plating process step is the deposition of a nickel or copper stud in the photo-resist opening. This is followed by the plating of the solder on top of the stud.

Plating technologies are challenged when it is necessary to maintain either very accurate alloy control and/or plate ternary (three element) alloy systems. For the Pb free technologies the binary systems of Sn/Ag and Sn/Cu the liquidus temperature of the alloy is unforgiving for small changes in the alloy. The most popular Pb free alloy of Sn/Ag/Cu requires either complex control in the plating of this ternary alloy or the plating of layers and then a reflow process to attempt to homogenize the bump structure alloy. Significant effort 4 has been put into the development of plated Pb free bump technology. There are no known Pb free plated bump technologies being offered on the market today. Solder Paste Solder paste technologies offer significant flexibility in solder alloy used. The alloy content is controlled during the paste manufacturing, prior to the bumping process. It is critical that the flux and reflow process and technology be properly developed to optimize a high yielding process. There are two primary solder paste processes in practice today. The first deposits the paste through a stencil that is then removed prior to reflow. The second process uses an in-situ stencil formed from a dry film solder mask.5 In this process the solder paste fills the openings and is then reflowed while the solder mask is still in place. The solder mask is removed from the wafer after the wafer is reflowed. Solder paste technology is often viewed as not being capable of fine pitches. However Fujitsu with their “Advanced Printing Process” 5 (second process from above) has demonstrated that pitches of 100um are possible. Sphere Placement The placement of solder spheres is commonly done for WLPs using spheres ranging from 250 to 500 microns in diameter. An emerging field is the placement of solder spheres that range from 80 to 200 microns for flip chip applications. Solder spheres like solder paste have the solder alloy formed and controlled prior to the bumping process.

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UBM BARRIER LAYER

SOLDER JOINT CRACK PROPAGATION

As previously mentioned one of the critical function of the UBM is to act as a solder barrier. The UBM can fail by either dissolution or diffusion. The dissolution occurs rapidly when the solder is molten. Diffusion occurs over the lifetime of the bump. It is well known that the breakdown or consumption of the UBM solder barrier is a function of the UBM used and the tin content of the solder bump.6, 7

The solder joints that connect the IC to either the IC substrate or a motherboard will fail at some point. To test for the fatigue life of the solder joints accelerated tests are performed for the assembly by cycling between a low temperature dwell of 0 to -65C and a high temperature dwell of 100 to 140C. The dwell times at each extreme range from 3 to 5 minutes and ramp times range from