NCN49599 Product Preview Power Line Carrier Modem The NCN49599 is a powerful power line communication SoC combining low power Cortex M0 processor with a high precision analogue front end. Based on a dual 4800 Baud S−FSK channel technology, it offers an ideal compromise between speed and robustness for operations in a harsh environment. It is functional compatible with its predecessor NCN49597, extending frequencies up to Cenelec D band for use in applications such as e-metering, home automation and street lighting. The NCN49599 benefits for more than 10 years of field experience in eMetering and delivers innovative features such as a smart synchronisation and automatic baud rate detection. Fully reprogrammable, it also supports building automation standard or full custom protocol. The configurable GPIOs allow connecting peripherals such as LCD or metering ICs.
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1 56 QFN56 8x8, 0.5P CASE 485CN
Features
• Power Line Carrier Modem for 50 and 60 Hz Mains • Embedded 1.2 A Highly Linear 2 stage Power Amplifier with current • • • • • • • • • • • • •
limitation and thermal protection. Embedded ARM Cortex M0 Processor, Programmable Embedded Software Compliant with CENELEC EN 50065−1 Dual S−FSK Channel Programmable Carrier Frequencies in CENELEC A−D Band Half Duplex Data Rate Selectable: 300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz) 360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz) Repetition and Smart Synchronization Algorithm Boost the Robustness of Communication Selectable UART/Full Duplex UART to Application Microcontroller SCI Port to Application Microcontroller SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb Power Supply 3.3 V and 12 V Junction Temperature Range: −40°C to +125°C These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS 56 1 ON
ARM
NCN49599 0C599−001 AWLYYWWG e3
XXXX Y ZZ
= Date Code = Plant Identifier = Traceability Code
ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 38 of this data sheet.
Typical Applications
• • • • • •
AMR: Automated Remote Meter Reading In Home Display Building Automation Solar Power Streetlight Control Transmission of Alerts (Fire, Gas Leak, Water Leak)
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. P0
1
Publication Order Number: NCN49599/D
NCN49599 APPLICATION Application Example Meter Interface
JTAG Interface 3V3_D
+12 D7
3V3_A
R19 C19
R3
R1
TX_OUT
A−
C5 +12 D1
+12
R5
A_OUT
R4
R6
R12
B−
C4
R14
B_OUT
C10
D2
A+ C6
R8
R10
1:2
B+
R9
Tr 1
C11
R7
+12
R13
C7
D3
C8
RX_OUT
41 39
C16
49
53
43
6
VDD
VDD
VDDA
TX_ENB
C1
C17
TXD/PRES VCC
C3
C2
ENB
R2
3V3_D
C18
12, 13, 14, 20 15, 16
51 52 1 54, 55 50
26
TXD
27
RXD
35
BR0
34
BR1
30
45
29 RX_IN
MAINS
REF_OUT
Application m Controller
RESB TEST
SDO SDI SCK
46
28 31
CSB
47
33
SEN
42
8, 9, 10, 11, 17, 18, 36
R11
D4
T_REQ
38
NCN49599
R18
32
37
2
3V3_D
U1
25
Optional External Flash
C9
R16
R17
22
21 Y1
XOUT
56
XIN
3
VEE
VSS
24
VEE
7 VSS
VSSA
44
C13 C14
GPIO bus
19 EXT_CLK_EN
C12
3V3_D
23 VDD1V8
ZC_IN
R15
5
4 RLIM
48
D5
ILIM
ALC_IN 3V3_A
PC20130109.1
C15
D6
Figure 1. Typical Application for the NCN49599S−FSK Modem
Figure 1 shows an S−FSK PLC modem build around NCN49599. For synchronization the line frequency is coupled in via R15, a 1 MW resistor. The Schottky diode pair D5 clamps the voltage within the input range of the zero cross detector. In the receive path a 2nd order high pass filter blocks the mains frequency. The corner point defined by C7, C8, R10 and R11. In the transmit path a 3th order low pass filter build around the internal power operational amplifier suppresses the 2nd and 3rd harmonics to be in line with the CENELEC EN 50065−1 specification. The filter
components are tuned for a space and mark frequency of 63.3 and 74 kHz respectively, typically for e−metering in the CENELEC A−band. The output of the amplifier is coupled via a DC blocking capacitor C10 to a 2:1 pulse transformer Tr1. The secondary of this transformer is coupled to the mains via a high voltage capacitor C11. High energetic transients from the mains are clamped by the protection diode combination D3, D4 together with D1, D2. Because the mains is not galvanic isolated care needs to be taken when interfacing to a microcontroller or a PC!
Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component
Function − Remark
Typ Value
Tolerance
Unit
C1
TX_OUT coupling capacitor
470
±20 %
nF
C2
Low pass transmit filter
470
±10 %
pF
C3
Low pass transmit filter
68
±10 %
pF
C4
Low pass transmit filter
3
±10 %
pF
C5
Low pass transmit filter
2,7
±10 %
nF
Decoupling block capacitor
100
−20 +80%
nF
C6, C16, C17, C18, C19 C7, C8
High pass receive filter
1
±10 %
nF
C9, C13
VREF_OUT ; VDD1V8 decoupling cap − ceramic
10
−20 +80%
mF
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NCN49599 Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component
Typ Value
Tolerance
Unit
C10
TX coupling cap; 1A rms ripple @ 70 kHz
10
±20%
mF
C11
High Voltage coupling capacitor; 630 V
220
±20%
nF
C12
Zero Cross noise suppression
100
±20%
pF
X−tal load capacitor
36
±20%
pF
R1
Low pass receive filter
3,3
±1%
kW
R2
Low pass receive filter
8,2
±1%
kW
Low pass transmit and High pass receive filter; Voltage Bias ; Pull up
10
±1%
kW
R4
Low pass transmit filter
3
±1%
kW
R5
Low pass transmit filter
1
±1%
kW
R6
Low pass transmit filter
1,6
±1%
kW
R10
High pass receive filter
15
±1%
kW
R11
High pass receive filter
30
±1%
kW
R14
TX Coupling resistor ; 0.5 W
0,47
±1%
W
R15
Zero Cross coupling HiV
1
±5%
MW
R16
Current protection
5
±1%
kW
R17
ILIM LED current
3,3
±5%
kW
C14, C15
R3, R7, R8, R9, R12, R13, R18, R19
Function − Remark
D1, D2
High current Schottky Clamp diodes
D3, D4
Unidirectional transient voltage suppressor
D5
Double low current Schottky clamp diode
D6
ILIM LED indication (optional)
D7
Bidirectional transient voltage suppressor
Y1
X−tall
Tr1
2:1 Coupling transformer
U1
PLC modem
MBRA430 P6SMB6.8AT3G BAS70−04 LED 1SMA12CA 48 MHz
NCN49599
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NCN49599 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol
Min
Max
Unit
Absolute max. power amplifier supply
Rating
VCC_ABSM
VEE − 0.3
13.2
V
Absolute max. digital power supply
VDD_ABSM
VSS − 0.3
3.9
V
Absolute max. analog power supply
VDDA_ABSM
VSSA − 0.3
3.9
V
Absolute max. difference between digital and analog power supply
VDD − VDDA_ABSM
−0.3
0.3
V
Absolute max. difference between digital and analog ground
VSS − VSSA_ABSM
−0.3
0.3
V
Absolute max. difference between digital and power ground
VSS − VEE_ABSM
−0.3
0.3
V
NON 5V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, ENB, TDO, TDI, TCK, TMS, TRSTB, TEST VIN_ABSM
VSS − 0.3
VDD + 0.3
V
VOUT_ABSM
VSS − 0.3
VDD + 0.3
V
Absolute maximum input for digital 5V safe inputs
V5VS_ABSM
VSS − 0.3
6.0
V
Absolute maximum voltage at 5V safe output pin
VOUT5V_ABSM
VSS − 0.3
3.9
V
Absolute maximum input for normal digital inputs and analog inputs Absolute maximum voltage at any output pin 5V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0 .. IO7, RESB
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Normal Operating Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the Normal Operating Conditions section and for the reliability specifications as listed in Detailed Hardware Description section. Functionality outside these limits is not implied. Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be less than 0.1% of the useful life as defined in Detailed Hardware Description section. Table 3. OPERATING RANGES Symbol
Min
Max
Unit
Power Supply Voltage Range
Rating
VDD
3.0
3.6
V
Power Operational Amplifier Voltage Range
VCC
6.0
12.0
V
Junction Temperature Range
TJ
−40
125
°C
Ambient Temperature Range
TA
−40
85
°C
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NCN49599 PIN DESCRIPTION QFN Packaging
VDDA
VSSA RX_OUT RX_IN REF_OUT ZC_IN EN A+ A− A_OUT VCC B_OUT1 B_OUT2 VEE
43
44
45
46
47
48
49
50
51
52
53
54
55
56
B− B+ VEE RLIM ILIM VDD VSS IO3 IO4 IO5 IO0 TDO TDI TCK
1
42
2
41
3
40
4
39
5
38
6
37
NCN49599
7 8
36 35
9
34
10
33
11
32
12
31
13
30
14
29
ALC_IN TX_OUT NC TX_EN TEST RES IO1 BR0 BR1 SEN IO2 CSB SDO SDI
28
27
26
25
24
23
22
21
20
19
17
18
16
15
SCK RXD TXD VDD VSS VDD1V8 XOUT XIN TXD/PRES EXT_CLK_EN IO7 IO6 TRST TMS
Figure 2. QFN Pin−out of NCN49599 (Top view)
Table 4. NCN49599QFN PIN FUNCTION DESCRIPTION Pin No.
Pin Name
I/O
Type
Description
1
B−
In
A
Negative (−) input of operational amplifier B
In
2
B+
A
Positive (+) input of operational amplifier B
3, 56
VEE
P
Negative supply for power amplifiers A and B
4
RLIM
A
Output B current limit set resistor
5
ILIM
D
Current limit logic flag
6, 25
VDD
P
3.3V digital supply
7, 24
VSS
P
Digital ground
8..11, 17, 18, 32, 36
IO0 .. IO7
In/Out
D, 5V Safe
General Purpose I/O’s
12
TDO
Out
D, 5V Safe
Test data output
TDI
In
D, 5V Safe, PD
Test data input
TCK
In
D, 5V Safe, PD
Test clock
TMS
In
D, 5V Safe, PD
Test mode select
TRSTB
In
D, 5V Safe, PD
Test reset bar (active low)
EXT_CLK_EN
In
D, 5V Safe
External Clock Enable input
TXD/PRES
Out
D, 5V Safe
Output of transmitted data (TXD) or PRE_SLOT signal (PRES)
XIN
In
A
13 14 15 16 19 20 21
Out
Xtal input (can be driven by an external clock)
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NCN49599 Table 4. NCN49599QFN PIN FUNCTION DESCRIPTION Pin No.
Pin Name
22
I/O
Type
Description
Out
A
Xtal output (output floating when XIN driven by external clock)
VDD1V8
P
1V8 regulator output. Foresee a decoupling capacitor
TXD
Out
D, 5V Safe, OD
SCI transmit output
27
RXD
In
D, 5V Safe
SCI receive input (Schmitt trigger input)
28
SCK
Out
D, 5V Safe
SPI interface external Flash
29
SDI
In
D, 5V Safe
SPI interface external Flash (Schmitt trigger input)
30
SDO
Out
D, 5V Safe
SPI interface external Flash
31
CSB
In
D, 5V Safe
SPI interface external Flash (Schmitt trigger input)
SEN
In
D, 5V Safe, PD
SPI interface Enable external Flash
34
BR1
In
D, 5V Safe
SCI baud rate selection
35
BR0
In
D, 5V Safe
SCI baud rate selection
37
RESB
In
D, 5V Safe
Master reset bar (Schmitt trigger input, active low)
TEST
In
D, 5V Safe, PD
Hardware Test enable (Schmitt trigger input)
TX_ENB
Out
D, 5V Safe, OD
TX enable (active low)
XOUT
23 26
33
38 39 40
NC
41
TX_OUT
Out
A
Transmitter output
42
ALC_IN
In
A
Automatic level control input
43
VDDA
P
3.3V analog supply
44
VSSA
P
Analog ground
45
RX_OUT
Out
A
Output of receiver low noise operational amplifier
46
RX_IN
In
A
Positive input of receiver low noise operational amplifier
47
REF_OUT
Out
A
Reference output for stabilization
48
ZC_IN
In
A
50/60 Hz input for mains zero cross detection
49
ENB
In
D
Enable / shutdown power amplifier (active low)
50
A+
In
A
Positive (+) input of operational amplifier A
51
A−
In
A
Negative (−) input of operational amplifier A
52
A_OUT
Out
A
Output of operational amplifier A
53
VCC
P
Positive supply for power amplifiers A and B
54
B_OUT1
Out
A
Output of operational amplifier B
55
B_OUT2
Out
A
Output of operational amplifier B
P:
Not connected pin. Tie to GND.
Power pin
5V Safe:
A:
Analog pin
Out:
D:
Digital pin
PD:
Internal Pull Down resistor
OD:
Open Drain Output
In:
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IO that support the presence of 5V on bus line Output signal Input signal
NCN49599 Table 5. NCN49599QFN PIN FUNCTION DESCRIPTION IN ROM MODE* Pin No.
Pin Name
11
IO0/RX_DATA
32
IO2/T_REQ
36
IO1/CRC
I/O
Type
Out
D, 5V Safe, OD
Description
In
D, 5V Safe
Out
D, 5V Safe, OD
Data reception indication (in ROM mode) Transmit Request input (in ROM mode) Correct frame CRC indication (in ROM mode)
*ROM mode: IO0,IO1 and IO2 has predefined function when NCN49599 boots from ROM
Detailed Pin Description VDDA
VDDA is the positive analog supply pin. Nominal voltage is 3.3 V. A ceramic decoupling capacitor CDA = 100 nF must be placed between this pin and the VSSA. Connection path of this capacitance to the VSSA on the PCB should be kept as short as possible in order to minimize the serial resistance. REF_OUT
REF_OUT is the analog output pin which provides the voltage reference used by the A/D converter. This pin must be decoupled to the analog ground by a 1 mF ceramic capacitance CDREF. The connection path of this capacitor to the VSSA on the PCB should be kept as short as possible in order to minimize the serial resistance. VSSA
VSSA is the analog ground supply pin. VDD
VDD is the 3.3 V digital supply pin. A ceramic decoupling capacitor CDD = 100 nF must be placed between this pin and the VSS. Connection path of this capacitance to the VSS on the PCB should be kept as short as possible in order to minimize the serial resistance.
Figure 3: Recommended Layout of the Placement of Decoupling Capacitors RX_IN
VSS
RX_IN is the positive analog input pin of the receiver low noise input op−amp. Together with RX_OUT and REF_OUT, an active high pass filter is realized. This filter removes the main frequency (50 or 60 Hz) from the received signal. The filter characteristics are determined by external capacitors and resistors. A typical application schematic can be found in paragraph 50/60 Hz Suppression Filter.
VSS is the digital ground supply pin. VDD1V8
This is an additional power supply pin to decouple an internal LDO regulator. The decoupling capacitor should be placed as close as possible to this output pin as illustrated in Figure 3.
ZC_IN
VEE
ZC_IN is the mains frequency analog input pin. The signal is used to detect the zero cross of the 50 or 60 Hz sine wave. This information is used, after filtering with the internal PLL, to synchronize frames with the mains frequency. In case of direct connection to the mains it is advised to use a series resistor of 1 MW in combination with two external clamp diodes in order to limit the current flowing through the internal protection diodes.
VEE is the ground of the power amplifier. It is important to foresee a separate power ground line to this connection able to conduct 1.2 A without significant voltage drop. A recommended layout is illustrated in Figure 3. VCC
VCC is the supply connection to the power amplifier. This connection should be able to conduct 1.2 A without significant voltage drop. A decoupling capacitor should be placed as close as possible to this power pin as illustrated in Figure 3.
RX_DATA (in ROM Mode Only)
RX_DATA is a 5 V compliant open drain output. An external pull−up resistor defines the logic high level as illustrated in Figure 4. A typical value for the pull−up resistance “R” is 10 kW. The signal on this output depends on the status of the data reception. If NCN49599 waits for
RX_OUT
RX_OUT is the output analog pin of the receiver low noise input op−amp. This op−amp is in a negative feedback configuration.
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NCN49599 configuration RX_DATA outputs a pulse train with a 10 Hz frequency. After Synchronization Confirm Time out RX_DATA = 0. If NCN49599 is searching for synchronization RX_DATA = 1.
The crystal is a classical parallel resonance type with its fundamental frequency equal to 48 MHz. For a typical load capacitance CL = 18 pF specified by the manufacturer of the crystal, the value of CX = 36 pF. The crystal has to fulfill impedance characteristics specified in the NCN49599 data sheet. As an oscillator is sensitive and precise, it is advised to put the crystal as close as possible on the board and to ground the case.
+5V R
XOUT
Output
XOUT is the analog output pin of the oscillator. When the clock signal is provided from an external generator, this output must be floating. When working with a crystal, this pin cannot be used directly as clock output because no additional loading is allowed on the pin (limited voltage swing).
VSSD
EXT_CLK_E
EXT_CLK_E allows the user to connect an external clock instead of using a quartz. When this pin pulled to VDD an external clock has to be applied to the XIN pin. When EXT_CLK_E is connected to VSS, the quartz oscillator is operational.
PC20090722. 2
Figure 4. Representation of 5V Safe Output TDO, TDI, TCK, TMS, and TRSTB
All these pins are part of the JTAG bus interface. The JTAG interface is used during production test of the IC and will not be described here. Input pins (TDI, TCK, TMS, and TRSTB) contain internal pull−down resistance. TDO is an output. When not used, the JTAG interface pins may be left floating.
TXD
TXD/PRES is the output for either the transmitting data (TX_DATA) or a synchronization signal with the time−slots (PRE_SLOT). TXD/PRES. More information can be found in paragraph Local Port.
TXD is the digital output of the asynchronous serial communication (SCI) unit. In half−duplex transmission (when booting from ROM) and in full−duplex mode (booted from Flash or after download over UART) it is used to realize the communication between the NCN49599 and the application microcontroller. The TXD is an open drain IO (5 V safe). External pull−up resistances (typically 10 kW) are necessary to generate the 5 V level. See Figure 4 for the circuit schematic.
XIN
RXD
TXD/PRES
XIN is the analog input pin of the oscillator. It is connected to the interval oscillator inverter gain stage. The clock signal can be created either internally with the external crystal and two capacitors or by connecting an external clock signal to XIN. For the internal generation case, the two external capacitors and crystal are placed as shown in Figure 5. For the external clock connection, the signal is connected to XIN and XOUT is left unused.
XTAL_IN
XTAL_OUT
EXT_CLK_E
This is the digital input of the asynchronous SCI unit. It is used in both half−duplex and full−duplex transmission (see TXD pin description). This pin supports a 5 V level. It is used to realize the communication between the NCN49599 and the application microcontroller. RXD is a 5 V safe input. T_REQ (in ROM Mode Only)
T_REQ is the transmission request input of the Serial Communication Interface when used in half−duplex mode. When pulled low its initiate a local communication from the application micro controller to NCN49599. T_REQ is a 5 V safe input. See also paragraph Serial Communication Interface. BR1, BR0
PC20120530.2
BR0 and BR1 are digital input pins. They are used to select the baud rate (bits/second) of the Serial Communication Interface unit in half−duplex mode. The rate is defined according to Table 29 BR1, BR0 Baud Rate. The values are taken into account after a reset, hardware or software. Modification of the baud rate during function is not possible. BR0 and BR1 are 5 V safe.
48 MHz
CX
CX VSSA
Figure 5. Placement of the Capacitors and Crystal with Clock Signal Generated Internally
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NCN49599 CRC (in ROM Mode Only)
gain. Low threshold is fixed to 0.4 V. A value under this threshold will result in an increase of the gain. The high threshold is fixed to 0.6 V. A value over this threshold will result in a decrease of the gain. A serial capacitance is used to block the DC components. The level adaptation is performed during the transmission of the first two bits of a new frame. Eight successive adaptations are performed. See also paragraph Amplifier with Automatic Level Control (ALC).
CRC is a 5 V compliant open drain output. An external pull−up resistor defines the logic high level as illustrated in Figure 4. A typical value for this pull−up resistance “R” is 10 kW. The signal on this output depends on the cyclic redundancy code result of the received frame. If the cyclic redundancy code is correct CRC = H during the pause between two time slots. RESB
RESB is a digital input pin. It is used to perform a hardware reset of the NCN49599. This pin supports a 5 V voltage level. The reset is active when the signal is low (0 V).
SCK, SDI, SDO, CSB
TEST
SEN is the SPI enable signal. When pulled low NCN49599 will boot from the internal program ROM. When pulled high (connected to VDD) the SPI interface is active and the IC will boot from the external Flash. Boot up sequences are described in more detail in Reference 1.
These signals form the SPI interface to an optional external Flash. See Reference 1. SEN
TEST is a digital input pin with internal pull down resistor used to enable the Hardware Test Mode of the chip. When TEST is left open or forced to ground Normal Mode is enabled. When TEST is forced to VDD the Hardware Test Mode is enabled. This mode is used during production test of the IC and will not be described here. TEST pin is not 5 V safe.
IO0 .. IO7
IO0 to IO7 are 8 general purpose input/output pins. When booting from ROM (SEN = VSS) IO0 .. IO2 have predefined functions: RX_DATA, CRC and T_REQ respectively. When booting from external Flash the user have access to all 8 of them. More information can be found in Reference 1.
TX_ENB
TX_ENB is a digital output pin. It is low when the transmitter is activated. The signal is available to turn on the line driver. TX_ENB is a 5 V safe with open drain output, hence a pull−up resistance is necessary achieve the requested voltage level associated with a logical one. See also Figure 4 for reference.
A−, A+, A_OUT, B−, B+, B_OUT1, B_OUT2
These are the interface pins to the 2 highly linear power operational amplifiers. Op Amp B is capable to drive 1.2 A. RLIM
TX_OUT
RLIM is the connection to the current limit set resistor defining the current protection level of power Op Amp B . Connecting a 5 kW resistor between RLIM and VEE sets the current limit to ILIMIT = 1.2 A.
TX_OUT is the analog output pin of the transmitter. The provided signal is the S−FSK modulated frames. A filtering operation must be performed to reduce the second and third order harmonic distortion. For this purpose an active filter is suggested. See also paragraph Transmitter Output TX_OUT.
ILIM
ILIM is the current limitation flag. This digital output is logic high when the output current of Op Amp B IOUT_B > ILIMIT.
ALC_IN
ALC_IN is the automatic level control analog input pin. The signal is used to adjust the level of the transmitted signal. The signal level adaptation is based on the AC component. The DC level on the ALC_IN pin is fixed internally to 1.65 V. Comparing the peak voltage of the AC signal with two internal thresholds does the adaptation of the
ENB
This digital input enables both power amplifiers A and B when ENB is driven low. A logic high will shutdown the amplifiers and put the outputs A_OUT, B_OUT1 and B_OUT2 in tri−state.
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NCN49599 ELECTRICAL CHARACTERISTICS DC and AC Characteristics Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator. Table 6. OSCILLATOR Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Crystal frequency
(Note 1)
fCLK
−100 ppm
48
+100 ppm
MHz
Duty cycle with quartz connected
(Note 1)
Start−up time
(Note 1)
Tstartup
Load capacitance external crystal
(Note 1)
CL
Series resistance external crystal
(Note 1)
RS
Maximum Capacitive load on XOUT
XIN used as clock input
CLXOUT
Low input threshold voltage
XIN used as clock input
VILXOUT
High input threshold voltage
XIN used as clock input
VIHXOUT
0.7 VDD
V
Low output voltage
XIN used as clock input, XOUT = 2 mA
VOLXOUT
0.3
V
High input voltage
XIN used as clock input
VOHXOUT
VDD − 0.3
V
35
1. Guaranteed by design. Maximum allowed series loss resistance is 60 W
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65
%
15
ms
18 1
6
pF 60
W
15
pF
0.3 VDD
V
NCN49599 Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN Table 7. ZERO CROSS DETECTOR AND 50/60 HZ PLL Parameter
Test Conditions
Symbol
Min
Max
Unit
ImpZC_IN
−20
20
mA
During 1 ms
ImavgZC_IN
−2
2
mA
With protection resistor at ZC_IN
VMAINS
90
550
V
Rising threshold level
(Note 2)
VIRZC_IN
1.9
V
Falling threshold level
(Note 2)
VIFZC_IN
0.85
V
Hysteresis
(Note 2)
VHYZC_IN
0.4
V
Lock range for 50 Hz (Note 3)
MAINS_FREQ = 0 (50 Hz)
Flock50Hz
45
55
Hz
Lock range for 60 Hz (Note 3)
MAINS_FREQ = 0 (60 Hz)
Flock60Hz
54
66
Hz
Lock time (Note 3)
MAINS_FREQ = 0 (50 Hz)
Tlock50Hz
15
s
Lock time (Note 3)
MAINS_FREQ = 0 (60 Hz)
Tlock60Hz
20
s
Frequency variation without going out of lock (Note 3)
MAINS_FREQ = 0 (50 Hz)
DF60Hz
0.1
Hz/s
Frequency variation without going out of lock (Note 3)
MAINS_FREQ = 0 (60 Hz)
DF50Hz
0.1
Hz/s
25
ms
Maximum peak input current Maximum average input current Mains voltage (ms) range
Jitter of CHIP_CLK (Note 3)
JitterCHIP_CLK
−25
Typ
2. Measured relative to VSS 3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed by the digital test patterns.
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NCN49599 Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB
To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz ± 100 ppm. Table 8. TRANSMITTER EXTERNAL PARAMETERS Parameter
Test Conditions
Symbol
Min
Maximum peak output level
fTX_OUT = 23 kHz fTX_OUT = 148.5 kHz Level control at max. output
VTX_OUT
0.85 0.76
Second order harmonic distortion
fTX_OUT = 148.5 kHz Level control at max. output
Third order harmonic distortion
Max
Unit
1.15 1.22
Vp
HD2
−55
dB
fTX_OUT = 148.5 kHz Level control at max. output
HD3
−57
dB
(Notes 4 and 6)
DfTX_OUT
30
Hz
(Note 4)
CLTX_OUT
20
pF
Frequency accuracy of the generated sine wave Capacitive output load at pin TX_OUT Resistive output load at pin TX_OUT
Typ
RLTX_OUT
5
TdTX_ENB
0.25
0.5
ms
Automatic level control attenuation step
ALCstep
2.9
3.1
dB
Maximum attenuation
ALCrange
20.3
21.7
dB
Low threshold level on ALC_IN
VTLALC_IN
0.46
0.34
V
High threshold level on ALC_IN
VTHALC_IN
0.72
0.54
V
Input impedance of ALC_IN pin
RALC_IN
111
189
kW
PSRRTX_OUT
10 35
Turn off delay of TX_ENB output
(Note 5)
Power supply rejection ration of the transmitter section
(Note 7) (Note 8)
kW
dB
4. 5. 6. 7.
This parameter will not be tested in production. This delay corresponds to the internal transmit path delay and will be defined during design. Taking into account the resolution of the DDS and an accuracy of 100 ppm of the crystal. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The signal level at TX_OUT is measured to determine the parameter. 8. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The signal level at TX_OUT is measured to determine the parameter.
The LPF filter + amplifier must have a frequency characteristic between the limits listed below. The absolute output level depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB reference value is measured at 50 kHz with a signal amplitude of 100 mV. Table 9. TRANSMITTER FREQUENCY CHARACTERISTICS Attenuation Frequency (kHz)
Min
Max
Unit
10
−0.5
0.5
dB
145.5
−1.3
0.5
dB
195
−4.5
−1.5
dB
245
−3.0
dB
500
−18.0
dB
1000
−36.0
dB
2000
−50
dB
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NCN49599 Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT Table 10. RECEIVER EXTERNAL PARAMETERS Parameter
Test Conditions
Symbol
Input offset voltage 42 dB
AGC gain = 42 dB
Input offset voltage 0 dB
Max
Unit
VOFFS_RX_IN
5
mV
AGC gain = 0 dB
VOFFS_RX_IN
50
mV
Max. peak input voltage (corresponding to 62.5% of the SD full scale)
AGC gain = 0 dB (Note 9)
VMAX_RX_IN
1.15
Vp
Input referred noise of the analog receiver path
AGC gain = 42 dB (Notes 9 and 10)
NFRX_IN
150
nV/ǠHz
Input leakage current of receiver input Max. current delivered by REF_OUT Power supply rejection ratio of the receiver input section
AGC gain = 42 dB (Note 11)
Min
Typ
0.85
ILE_RX_IN
−1
1
mA
IMax_REF_OUT
−300
300
mA
PSRRLPF_OUT
10
dB
35
dB
AGC gain = 42 dB (Note 12)
AGC gain step
AGCstep
5.5
6.5
dB
AGC range
AGCrange
39.9
44.1
dB
Analog ground reference output voltage
VREF_OUT
1.52
1.78
V
SNAD_OUT
54
VCLIP_AGC_IN
1.05
Signal to noise ratio at 62.5 % of the SD full scale
(Notes 9 and 13)
Clipping level at the output of the gain stage (RX_OUT)
dB 1.65
Vp
9. Input at RX_IN, no other external components. 10. Characterization data only. Not tested in production. 11. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and REF_OUT output is measured to determine the parameter. 12. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is measured to determine the parameter. 13. These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB.
The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below. The absolute output level depends on the operating condition. Table 11. RECEIVER FREQUENCY CHARACTERISTICS Attenuation Frequency (kHz)
Min
Max
Unit
10
−0.5
0.5
dB
148.5
−1.3
0.5
dB
195
−4.5
−2.0
dB
245
−3.0
dB
500
−18.0
dB
1000
−36.0
dB
2000
−50
dB
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NCN49599 Power Amplifier Parameters: Pin A+, A−, A_OUT, B+, B−, BOUT1&2, VSS, VEE, ENB Table 12. POWER AMPLIFIER GENERAL PARAMETERS Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Output shutdown time
ENB 0 ³ 1
60
Output enable time
ENB 1 ³ 0
5
10
ms
Quiescent Current
ENB = 0
IQ_EN
20
40
mA
ENB = 1
IQ_DIS
140
200
mA
Thermal shutdown
(Note 14)
Recovery from thermal shutdown
(Note 14)
+150
ns
+160
°C
+135
°C
14. Characterization data only. Not tested in production.
Table 13. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP A Parameter
Test Conditions
Symbol
Input Offset Voltage
VCC = +12 V, VEE = 0 V
Offset vs Power Supply Input Bias Current Input Voltage Noise Density
Typ
Max
Unit
VOS
±3
±10
mV
VCC = +6 V, VEE = *6 V
PSRR
25
150
mV/V
(Note 15)
IB
1
nA
f = 1 kHz, VIN = GND, BW = 131 kHz (Note 15)
en
Common−Mode Voltage Range Common−Mode Rejection Ratio
VEE * 0.1 v VCM v VCC * 3
Min
250
VCM
VEE −0.1
CMRR
70
Differential input impedance Common−Mode input impedance Open−Loop Gain
80
RL = 500 W (Note 15)
Gain Bandwidth Product Full Power Bandwidth
GWP G = +5, Vout = 11 VPP (Note 15)
Slew Rate Total Harmonic Distortion + Noise
Voltage Output Swing from Rail
0.2
nV/ǠHz VCC − 3
V
85
dB
0.2 | 1.5
GW | pF
0.2 | 3
GW | pF
100
dB
80
MHz
1.5
MHz
SR
60
V/ ms
G = +1, RL = 500 W, VO = 8 VPP, f = 1 kHz, CIN = 220 mF, COUT= 330 mF
THD+N
0.015
%
G = +1, RL = 50 W, VO = 8 VPP, f = 100 kHz, CIN = 220 mF, COUT = 330 mF
THD+N
0.023
%
VCC = +12 V, VEE = 0 V
From Positive Rail
IL = − 12 mA
VOH
0.3
1
V
From Negative Rail
IL = + 12 mA
VOL
0.3
1
V
ISC
280
mA
Z0
0.25
W
CLOAD
100
pF
Short*Circuit Current Output Impedance
Closed Loop G = +4, f = 100 kHz
Capacitive Load Drive 15. Characterization data only. Not tested in production.
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NCN49599 Table 14. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP B Test Conditions
Symbol
Typ
Max
Unit
Input Offset Voltage
Parameter
VCC = +12 V, VEE = 0 V
VOS
±3
±10
mV
Offset vs Power Supply
VCC = +12 V, VEE = 0 V
PSRR
25
150
mV/V
(Note 16)
IB
1
nA
f = 1 kHz, VIN = GND, BW = 131 kHz
en VCM
VEE −0.1
VEE * 0.1 v VCM v VCC * 3
CMRR
70
Input Bias Current Input Voltage Noise Density Common*Mode Voltage Range Common*Mode Rejection Ratio
Min
125
nV/ǠHz VCC − 3
V
85
dB
Differential input impedance
0.2 | 11
GW | pF
Common*Mode input impedance
0.2 | 22
GW | pF
100
dB
60
MHz
Open*Loop Gain
80
RL = 5 W (Note 16)
Gain Bandwidth Product Full Power Bandwidth
GWP G = +2, Vout = 11 VPP (Note 16)
400
kHz
SR
70
V/ ms
G = +1, RL = 50 W, VO = 8 VPP, f = 1 kHz
THD+N
0.015
%
G = +1, RL = 50 W, VO = 8 VPP, f = 100 kHz
THD+N
0.067
%
Slew Rate Total Harmonic Distortion + Noise
Voltage Output Swing from Rail From Positive Rail
From Negative Rail
Short*Circuit Current Output Impedance
200
VCC = +12 V, VEE = 0 V IOUT = − 1.2 A @ TJ = 25°C
VOH
0.7
1
V
IOUT = − 1.0 A @ TJ = 125°C
VOH
0.7
1
V
IOUT = + 1.2 A @ TJ = 25°C
VOH
0.4
1
V
IOUT = + 1.0 A @ TJ = 125°C
VOH
0.4
1
V
RLIM = 5 kW
ISC
1.2
A
Closed Loop G = +1, f = 100 kHz
Enabled Mode
ENB = 0
Z0
0.065
W
Shutdown Mode
ENB = 1
Z0
12
MW
CLOAD
500
nF
Capacitive Load Drive 16. Characterization data only. Not tested in production.
Power−on−Reset (POR) Table 15. POWER−ON−RESET Parameter
Test Conditions
Symbol
Min
VPOR
2.1
TRPOR
1
Test Conditions
Symbol
Min
Low output voltage
IXOUT = 3 mA
VOL
High output voltage
IXOUT = −3 mA
VOH
POR threshold Power supply rise time
0 to 3V
Typ
Max
Unit
2.7
V ms
Digital Outputs: TDO, CLK_OUT Table 16. DIGITAL OUTPUTS: TDO, CLK_OUT Parameter
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0.85 VDD
Typ
Max
Unit
0.4
V V
NCN49599 Digital Outputs with Open Drain: TX_ENB, TXD Table 17. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, RX_DATA, CRC, T_REQ Parameter Low output voltage
Test Conditions
Symbol
Min
IXOUT = 4 mA
VOL
Test Conditions
Symbol
0 to 3 V
VIH
0.8 VDD
ILEAK
−10
Typ
Max
Unit
0.4
V
Max
Unit
0.2 VDD
V
Digital Inputs: BR0, BR1 Table 18. DIGITAL INPUTS: BR0, BR1 Parameter Low input level High input level
Min
Typ
VIL
Input leakage current
V 10
mA
Max
Unit
0.2 VDD
V
50
kW
Max
Unit
0.80 VDD
V
Digital Inputs with Pull Down: TDI, TMS, TCK, TRSTB, TEST Table 19. DIGITAL INPUTS WITH PULL DOWN: TDI, TMS, TCK, TRSTB, TEST Parameter
Test Conditions
Symbol
Low input level
Typ
VIL
High input level Pull down resistor
Min
(Note 17)
VIH
0.8 VDD
RPU
7
Symbol
Min
V
17. Measured around a bias point of VDD/2.
Digital Schmitt Trigger Inputs: RXD, RESB Table 20. DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB Parameter
Test Conditions
Rising threshold level
VT+
Falling threshold level
VT−
0.2 VDD
Input leakage current
ILEAK
−10
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Typ
V 10
mA
NCN49599 Current Consumption Table 21. CURRENT CONSUMPTION Parameter
Test Conditions
Symbol
Current consumption in receive mode
Current through VDD and VDDA (Note 18)
Current consumption in transmit mode
Min
Typ
Max
Unit
IRX
60
mA
Current through VDD and VDDA (Note 18)
ITX
60
mA
Current consumption when RESB = 0
Current through VDD and VDDA (Note 18)
IRESET
4
mA
Current consumption when ENB = 0
Quiescent current though VCC
IQ_EN
20
40
mA
Current consumption when ESNB = 1
Quiescent current though VCC
IQ_HiZ
120
150
mA
18. fCLK = 48 MHz.
INTRODUCTION General Description The NCN49599 is a single chip half duplex S−FSK modem dedicated to power line carrier (PLC) data transmission on low− or medium−voltage power lines. The device offers complete handling of the protocol layers from the physical up to the MAC. NCN49599 complies with the CENELEC EMC standard EN 50065−1 and the IEC 61334−5−1 standards. It operates from a 3.3 V and 12 V power supply and is interfaced to the power line by an integrated power amplifier and transformer. An internal PLL is locked to the mains frequency and is used to synchronize the data transmission at data rates of 300, 600, 1200, 2400 and 4800 baud for a 50 Hz mains frequency, or 360, 720, 1440, 2880 and 5760 baud for a 60 Hz mains frequency. In both cases this corresponds to 3, 6, 12 or 24 data bits per half cycle of the mains period. S−FSK is a modulation and demodulation technique that combines some of the advantages of a classical spread spectrum system (e.g. immunity against narrow band interferers) with the advantages of the classical FSK system (low complexity). The transmitter assigns the space frequency fS to “data 0” and the mark frequency fM to “data 1”. The difference between S−FSK and the classical FSK lies in the fact that fS and fM are now placed far from each other, making their transmission quality independent from each other (the strengths of the small interferences and the signal attenuation are both independent at the two frequencies). The frequency pairs supported by the NCN49599 are in the range of 9 − 150 kHz with a typical separation of 10 kHz. The conditioning and conversion of the signal is performed at the analog front−end of the circuit. The further processing of the signal and the handling of the protocol is digital. At the back−end side, the interface to the application
is done through a serial interface. The digital processing of the signal is partitioned between hardwired blocks and a microprocessor block. The microprocessor is controlled by firmware. Where timing is most critical, the functions are implemented with dedicated hardware. For the functions where the timing is less critical, typically the higher level functions, the circuit makes use of the ARM microprocessor core. The processor runs DSP algorithms and, at the same time, handles the communication protocol. The communication protocol, in this application, contains the MAC = Medium Access Control Layer. The program is stored in a masked ROM. Depending on the status of the SEN input, after power on reset NCN49599 will boot from internal ROM or external Flash or over the Serial Communication Interface. The working data necessary for the processing is stored in an internal RAM. At the back−end side the link to the application hardware is provided by a Serial Communication Interface (SCI). The SCI is an easy to use serial interface, which allows communication between an external processor used for the application software and the NCN49599 modem. The SCI works on two wires: TXD and RXD. Baud rate is programmed by setting 2 bits (BR0, BR1). Because the low protocol layers are handled in the circuit, the NCN49599 provides an innovative architectural split. Thanks to this, the user has the benefit of a higher level interface of the link to the PLC medium. Compared to an interface at the physical level, the NCN49599 allows faster development of applications. The user just needs to send the raw data to the NCN49599 and no longer has to take care of the protocol detail of the transmission over the specific medium. This last part represents usually 50% of the software development costs.
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NCN49599 CLIENT Application
SERVER Application
SERVER Application
SPY Application
TEST Application
NCN49597 in MASTER mode
NCN49597 in SLAVE mode
NCN49597 in SLAVE mode
NCN49597 in MONITOR mode
NCN49597 in TEST mode
Major User Type
Minor User Type
Figure 6. Application Examples
• Minor type:
NCN49599 is intended to connect equipment using Distribution Line Carrier (DLC) communication. It serves two major and two minor types of applications: • Major types: ♦ Master or Client: A Master is a client to the data served by one or many slaves on the power line. It collects data from and controls the slave devices. A typical application is a concentrator system ♦ Slave or Server: A Slave is a server of the data to the Master. A typical application is an electricity meter equipped with a PLC modem.
♦
♦
Spy or Monitor: Spy or Monitor mode is used to only listen to the data that comes across the power line. Only the physical layer frame correctness is checked. When the frame is correct, it is passed to the external processor. Test Mode: The Software Test Mode is used to test the compliance of a PLC modem conforms to CENELEC. EN 50065−1 by a continuous broadcast of fS or fM.
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PC201111 12.2
NCN49599 Functional Description The block diagram below represents the main functional units of the NCN49599: VCC
B− B+ RLIM ILIM A_OUT
A− A+
VDD 1V8 VDDA
B_OUT1 B_OUT2
Current Protect
B
A
NCN49599 TSD Communication Controller
Power Amplifier
EN
VDDD
Transmitter (S−FSK Modulator)
TX_ENB LP Filter
TX_OUT
D/A
Receiver (S−FSK Demodulator)
AAF
AGC
A/D
Test Control
S−FSK Demodulator
IO[7:3] RX_DATA CRC TXD/PRES
5
JTAG I /F TEST RESB
POR Watchdog Timer 1 & 2
REF
REF_OUT
5
Local Port
ARM Risc Core
RX_OUT RX_IN
4
Flash SPI Clock and Control
ZC_IN
Zero crossing
PLL
VEE
VSSA
Clock Generator & Timer
VSSD
TO Application Micro Controller
BR1
Transmit Data & Sine Synthesizer
ALC_IN
FROM Line Coupler
TxD RxD T_REQ BR0
Serial Comm. Interface
OSC
Program/Data RAM
Program ROM
XIN XOUT EXT_CLK_E
SPI I/F SEN
TO External Flash
Interrupt Control
PC20130109.2
Figure 7. S−FSK Modem NCN49599 Block Diagram Power Amplifier
automatic gain control (AGC) block. This operation maximizes the dynamic range of the incoming signal. The signal is then converted to its digital representation using sigma delta modulation. From then on, the processing of the data is done in a digital way. By using dedicated hardware, a direct quadrature demodulation is performed. The signal demodulated in the base band is then low pass filtered to reduce the noise and reject the image spectrum.
The Power Amplifier block contains a Class A/B, low distortion line driver. Its design is optimized to accept a signal from the transmitter. The output stage is designed to drive up to 1.2 A peak into an isolation transformer or simple coil coupling to the mains. At output current of 1.2 A, the output voltage is guaranteed to swing within 1 V or less of either rail giving the user improved SNR. The input stage contains an operational amplifier which can be configured as a unity gain follower buffer or used to provide the first stage of a 4−pole low pass filter. Current protection is set with a single resistor, RLIM, together with a current limit flag. Thermal protection is set by a voltage level at the VWARN pin. The output stage goes into a high−impedance state once the junction temperature has exceeded +150°C.
Clock and Control
According to the IEC 61334−5−1 standard, the frame data is transmitted at the zero cross of the mains voltage. In order to recover the information at the zero cross, a zero cross detection of the mains is performed. A phase−locked loop (PLL) structure is used in order to allow a more reliable reconstruction of the synchronization. This PLL permits as well a safer implementation of the ”repetition with credit” function (also known as chorus transmission). The clock generator makes use of a precise quartz oscillator master. The clock signals are then obtained by the use of a programmed division scheme. The support circuits are also contained in this block. The support circuits include the necessary blocks to supply the references voltages for the AD and DA converters, the biasing currents and power supply sense cells to generate the right power off and startup conditions.
Transmitter
The NCN49599 Transmitter function block prepares the communication signal which will be sent on the transmission channel during the transmitting phase. This block is connected to a power amplifier which injects the output signal on the mains through a line−coupler. Receiver
The analog signal coming from the line−coupler is low pass filtered in order to avoid aliasing during the conversion. Then the level of the signal is automatically adapted by an
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NCN49599
t
48 bit @ 2400 baud 20 ms
PC20100609.1
Figure 8. Data Stream is in Sync with Zero Cross of the Mains (example for 50 Hz) Communication Controller
Local Port
The Communication Controller block includes the micro−processor, its peripherals: RAM, ROM, UART, TIMER, and the Power on reset. The processor uses the ARM Reduced Instruction Set Computer (RISC) architecture optimized for IO handling. For most of the instructions, the machine is able to perform one instruction per clock cycle. The microcontroller contains the necessary hardware to implement interrupt mechanisms, timers and is able to perform byte multiplication over one instruction cycle. Depending on the status of the SEN input, after power on reset NCN49599 will boot from internal ROM, external Flash or over the Serial Communication Interface. Booting from ROM will make the modem work conform to the IEC−61334−5 standard. The RAM contains the necessary space to store the working data. The back−end interface is done through the Serial Communication Interface block which works in half−duplex or full−duplex mode. This back−end is used for data transmission with the application micro controller and for the definition of the modem configuration.
The controller uses 3 output ports to inform about the actual status of the PLC communication. RX_DATA indicates if Receiving is in progress, or if NCN49599 is waiting for synchronization, or of it configures. CRC indicates if the received frames are valid (CRC = OK). TXD/PRES is the output for either the transmitting data (TX_DATA) or a synchronization signal with the time−slots (PRE_SLOT). Serial Communication Interface
When booting from ROM the local communication is a half duplex asynchronous serial link using a receiving input (RxD) and a transmitting output (TxD). The input port T_REQ is used to manage the local communication with the application micro controller and the baud rate can be selected depending on the status of two inputs BR0, BR1. These two inputs are taken in account after an NCN49599 reset. Thus when the application micro controller wants to change the baud rate, it has to set the two inputs and then provoke a reset. When booting from Flash or over the SCI, the Serial Communication Interface is Full Duplex.
DETAILED HARDWARE DESCRIPTION Clock and Control According to the IEC 61334−5−1 standard, the frame data is transmitted at the zero cross of the mains voltage. In order to recover the information at the zero cross, a zero cross detection of the mains is performed. A phase−locked loop (PLL) structure is used in order to allow a more reliable reconstruction of the synchronization. The output of this
block is the clock signal CHIP_CLK, 8 times over sampled with the bit rate. The oscillator makes use of precise 48 MHz quartz. This clock signal together with CHIP_CLK is fed into the Clock Generator and time block. Here several internal clock signals and timings are obtained by the use of a programmed division scheme.
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Zero crossing
ZC_IN
PLL
CHIP_CLK
PRE_SLOT
PRE_FRAME_CLK
FRAME_CLK
BYTE_CLK
BIT_CLK
Clock and Control
PRE_BYTE_CLK
NCN49599
Clock Generator & Timer
PC20120530.1
OSC
EXT_CLK_E
XIN
XOUT
Figure 9. Clock and Control Block Zero Cross Detector
case of direct connection to the mains it is advised to use a series resistor of 1 MW in combination with two external Schottky clamp diodes in order to limit the current flowing through the internal protection diodes.
ZC_IN is the mains frequency analog input pin. The signal is used to detect the zero cross of the 50 or 60 Hz sine wave. This information is used, after filtering with the internal PLL, to synchronize frames with the mains frequency. In
Clock & Control
3V3_A
FROM MAINS
BAS70−04 1 MW
ZC_IN
Debounce Filter
100 pF
ZeroCross
PLL
CHIP_CLK
PC2010608.1
Figure 10. Zero Cross Detector with Falling Edge De−bounce Filter
The zero cross detector output is logic zero when the input is lower than the falling threshold level and a logic one when the input is higher than the rising threshold level. The falling
edges of the output of the zero cross detector are de−bounced by a period between 0.5 ms and 1 ms. The Rising edges are not de−bounced.
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NCN49599 VMAINS
VIRZC _IN VIFZC _IN
t
ZeroCross
tZCD
tDEBOUNCE = 0,5 .. 1 ms 10 ms PC20090620 .1
Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz) 50/60 Hz PLL
crossings. The PLL locks on the zero cross from negative to positive phase. The bit rate is always an even multiple of the mains frequency, so following combinations are possible:
The output of the zero cross detector is used as an input for a PLL. The PLL generates the clock CHIP_CLK which is 8 times the bit rate and which is in phase with the rising edge
Table 22. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY BAUD[2:0]
Baudrate
CHIP_CLK
000
300
2400 Hz
001
600
4800 Hz
1200
9600 Hz
011
2400
19200 Hz
100
4800
38400 Hz
000
360
2880 Hz
010
MAINS_FREQ
50 Hz
001
720
5760 Hz
010
1440
11520 Hz
011
2880
23040 Hz
100
5760
46080 Hz
60 Hz
In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.
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NCN49599 V MAINS
VIR ZC _IN
t 6 bit @ 300 baud
ZeroCross
tZCD PLL in lock CHIP _CLK Start of Physical PreFrame 10 ms
(*) PC 20090 619 .3
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 13 mS = tZCD to compensate for the zero cross delay.
Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)
a number value stored in register R_ZC_ADJUST[7:0]. The adjustment period or granularity is 13 ms. The maximum adjustment is 255 x 13 ms = 3.32 ms which corresponds with 1/6th of the 50 Hz mains sine period.
The phase difference between the zero cross of the mains and CHIP_CLK can be tuned. This opens the possibility to compensate for external delay tZCD (e.g. opto coupler) and for the 1.9 V positive threshold VIRZC_IN of the zero cross detector. This is done by pre−loading the PLL counter with Table 23. ZERO CROSS DELAY COMPENSATION R_ZC_ADJUST[7:0]
Compensation
0000 0000
0 ms
0000 0001
13 ms
0000 0010
26 ms
0000 0011
39 ms
…
…
1111 1111
3315 ms
Oscillator
The oscillator works with a standard parallel resonance crystal of 48 MHz. XIN is the input to the oscillator inverter gain stage and XOUT is the output. XIN
XOUT
EXT_CLK_E
PC20120530.2
48 MHz
CX
CX VSSA
Figure 13. Placement of the Capacitors and Crystal with Clock Signal Generated Internally
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NCN49599 For correct functionality the external circuit illustrated in Figure 13 must be connected to the oscillator pins. For a crystal requiring a parallel capacitance of 18 pF CX must be around 36 pF. (Values of capacitors are indicative only and are given by the crystal manufacturer). To guarantee startup the series loss resistance of the crystal must be smaller than 60 W. EXT_CLK_E should be strapped to VSSA. If an external clock of 48 MHz is used, this signal should be connected to XIN and EXT_CLK_E needs to be pulled to VDD The oscillator output fCLK = 48 MHz is the base frequency for the complete IC. The clock frequency for the ARM fARM = fCLK. The clock for the transmitter, fTX_CLK is equal to fCLK / 4 or 12 MHz. All the transmitter internal clock signals will be derived from fTX_CLK. The clock for the receiver,
fRX_CLK is equal to fCLK / 8 or 6 MHz. All the receiver internal clock signals will be derived from fRX_CLK. Clock Generator and Timer
The CHIP_CLK and fCLK are used to generate a number of timing signals used for the synchronization and interrupt generation. The timing generation has a fixed repetition rate which corresponds to the length of a physical subframe. (see paragraph Reference 1) The timing generator is the same for transmit and receive mode. When NCN49599 switches from receive to transmit and back from transmit to receive, the R_CHIP_CNT counter value is maintained. As a result all timing signals for receive and transmit have the same relative timing. The following timing signals are defined as:
Start of the physical subframe
R_CHIP_CNT
2871 2872
2879
0
1
2
3
4
5
6
7
8
9
63
64
65
CHIP_CLK
BIT_CLK
BYTE_CLK
FRAME_CLK
PRE_BYTE_CLK
PRE_FRAME_CLK
PRE_SLOT
PC20090619.1
Figure 14. Timing Signals
PRE_BYTE_CLK is a signal which is 8 CHIP_CLK sooner than BYTE_CLK. This signal is used as an interrupt for the internal microcontroller and indicates that a new byte for transmission must be generated. PRE_FRAME_CLK is a signal which is 8 CHIP_CLK sooner than FRAME_CLK. This signal is used as an interrupt for the internal microcontroller and indicates that a new frame will start at the next FRAME_CLK. PRE_SLOT is logic 1 between the rising edge of PRE_FRAME_CLK and the rising edge of FRAME_CLK. This signal can be provided at the digital output pin
CHIP_CLK: is the output of the PLL and 8 times the bit rate on the physical interface. See also paragraph 50/60 Hz PLL. BIT_CLK: is active at counter values 0, 8, 16, .. 2872 and inactive at all other counter values. This signal is used to indicate the transmission of a new bit. BYTE_CLK: is active at counter values 0, 64, 128, .. 2816 and inactive at all other counter values. This signal is used to indicate the transmission of a new byte. FRAME_CLK: is active at counter values 0 and inactive at all other counter values. This signal is used to indicate the transmission or reception of a new frame.
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NCN49599 signal conditioning step, a digital to analog conversion is performed. As for the receive path, a sigma delta modulation technique is used. In the analog domain, the signal is low pass filtered, in order to remove the high frequency quantization noise, and passed to the automatic level controller (ALC) block, where the level of the transmitted signal can be adjusted. The determination of the signal level is done through the sense circuitry.
TXD/PRES when R_CONF[7] = 0 (See paragraph Local Port and Table 26, field R_CONF_TXD_PRES_SEL) and can be used by the external host controller to synchronize its software with the FRAME_CLK of NCN49599. Transmitter Path Description (S−FSK Modulator) For the generation of the space and mark frequencies, the direct digital synthesis (DDS) of the sine wave signals is performed under the control of the microprocessor. After a
Transmitter(S−FSK Modulator) TX_EN
ALC_IN
ALC control
TX_OUT
LP Filter
ARM Interface & Control Transmit Data & Sine Synthesizer
D/A
fMI
f MQ
fSI
fSQ
TO RECEIVER
PC20091019.1
Figure 15. Transmitter Block Diagram ARM Interface and Control
Sine Wave Generator
The interface with the ARM consists in a 8−bit data registers R_TX_DATA, 2 control registers R_TX_CTRL and R_ALC_CTRL, a flag TX_RXB defining transmit and receive and 2 16−bit wide frequency step registers R_FM and R_FS defining fM (mark frequency = data 1) and fS (space frequency = data 0). All these registers are memory mapped. Some of them are for internal use only and cannot be accessed by the user. Processing of the physical frame (preamble, MAC address, CRC) is done by the ARM.
A sine wave is generated with a direct digital synthesizer DDS. The synthesizer generates in transmission mode a sine wave either for the space frequency (fS, data 0) or for the mark frequency (fM, data1). In reception the synthesizer generates the sine and cosine waves for the mixing process, fSI, fSQ, fMI, fMQ (space and mark signals in phase and quadrature). The space and mark frequencies are defined in an individual step 16 bit wide register.
Table 24. FS AND FM STEP REGISTERS ARM Register
Hard Reset
Soft Reset
Description
R_FS[15:0]
0000h
0000h
Step register for the space frequency fS
R_FM[15:0]
0000h
0000h
Step register for the mark frequency fM
• R_FS[15:0]_dec = Round(218 x fS/fDDS) • R_FM[15:0]_dec = Round(218 x fM/fDDS)
The space and mark frequency can be calculated as: • fS = R_FS[15:0]_dec x fDDS/218 • fM = R_FM[15:0]_dec x fDDS/218
♦
Or the content of both R_FS[15:0] and R_FM[15:0] are defined as:
Where fDDS = 3 MHz is the direct digital synthesizer clock frequency.
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NCN49599 TX_ENB is 1 when the NCN49599 is in receive mode. TX_ENB is 0 when NCN49599is in transmit mode. When going from transmit to receive mode (TX_RXB goes from 1 to 0) the TX_ENB signal is kept active for a short period of tdTX_ENB. The control logic for the transmitter generates a signal TX_DATA which corresponds to the transmitted S−FSK signal. When transmitting fM TX_DATA is logic 1. When transmitting fS TX_DATA is logic 0. When the transmitter is not enabled (TX_RXB = 0) TX_DATA goes to logic 1 at the next BIT_CLK.
After a hard or soft reset or at the start of the transmission (when TX_RXB goes from 0 to 1) the phase accumulator must start at it’s 0 phase position, corresponding with a 0 V output level. When switching between fM and fS the phase accumulator must give a continuous phase and not restart from phase 0 When NCN49599 goes into receive mode (when TX_RXB goes from 1 to 0) the sine wave generator must make sure to complete the active sine period. The control logic for the transmitter generates a signal TX_ENB to enable the integrated power amplifier. BIT_CLK
TX_DATA
TX_RXB
TX_ENB
TX_OUT
tdTX_ENB
PC200 90610.1
Figure 16. TX_ENB Timing DA Converter
After hard or soft reset the level is set at minimum level (maximum attenuation) When going to reception mode (when TX_RXB goes from 1 to 0) the level is kept in memory so that the next transmit frame starts with the old level. The evaluation of the level is done during 1 CHIP_CLK period. Depending on the value of peak level on ALC_IN the attenuation is updated: • VpALC_IN < VTLALC: increase the level with one 6 dB step • VTLALC ≤ VpALC_IN ≤ VTHALC: don’t change the level • VpALC_IN > VTHALC: decrease the level with one 6 dB step The gain changes in the next CHIP_CLK period. An evaluation phase and a level adjustment take 2 CHIP_CLK periods. ALC operation is enabled only during the first 16 CHIP_CLK cycles after a hard or soft reset or after going into transmit mode. The automatic level control can be disabled by setting register R_ALC_CTRL[3] = 1. In this case the transmitter output level is fixed to the programmed level in the register R_ALC_CTRL[2:0]. See Reference 1.
A digital to analog SD converter converts the sine wave digital word to a pulse density modulated (PDM) signal. The PDM signal is converted to an analog signal with a first order switched capacitor filter. Low Pass Filter
A 3rd order continuous time low pass filter in the transmit path filters the quantization noise and noise generated by the SD DA converter. The typical corner frequency f−3dB = 138 kHz and is internally trimmed to compensate for process variation. This filter can be tuned to f−3dB = 195 kHz to allow operating in the D−band as described in Reference 1.
Amplifier with Automatic Level Control (ALC)
The pin ALC_IN is used for level control of the transmitter output level. First peak detection is done. The peak value is compared to two thresholds levels: VTLALC_IN and VTHALC_IN. The result of the peak detection is used to control the setting of the level of TX_OUT. The level of TX_OUT can be attenuated in 8 steps of 3 dB typical.
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NCN49599 Table 25. FIXED TRANSMITTER OUTPUT ATTENUATION ALC_CTRL[2:0]
Attenuation
000
0 dB
001
−3 dB
010
−6 dB
011
−9 dB
100
−12 dB
101
−15 dB
110
−18 dB
111
−21 dB
Power Amplifier
Coupling and filtering
The integrated power amplifier consists of 2 independent operational amplifiers. The first or input stage is designed to build a 2nd order low pass filter or to be used as unity gain follower buffer. The second or power stage is a low distortion Class A/B line driver able to deliver 1.2 A peak current with the output voltage guaranteed to swing within 1 V or less of either rail giving the user improved SNR. Current protection is set with a single resistor, RLim. The output stage goes into a high*impedance state once the junction temperature has exceeded +150_C
Because the complete analog part of the S−FSK modulator inside NCN49599 is referenced to the analogue ground REF_OUT, and its output is DC coupled to the TX_OUT pin, a decoupling capacitor C1 is needed when connecting it to the Power Amplifier. To suppress the second and third order harmonic of the generated S−FSK signal it is recommended to use a 2nd or 3th order low pass filter. In Figure 17 a MFB topology of a 3th order filter is illustrated to be compliant with the European CENELEC EN 50056−1 standard for signaling on low*voltage electrical installations in the frequency range 3 kHz to 148.5 kHz. R3
R4 R5
R6
R2
C3
R1
C1
C4
VCC
C2
C5
R8 B−
B+
A_OUT
A−
A+ R7
TO COUPLER
C6
B_OUT1
B_OUT2
A
Power Amplifier
EN
Transmitter (S−FSK Modulator)
R22 TX_EN
A TX_OUT
LP Filter
ARM Interface & Control
Figure 17. Power Amplifier and Filtering
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PC20120831.2
NCN49599 • The thermal resistance from junction to ambient Rthj−a • The output current I_outB or IL • The output voltage. V_outB or VL
Noise and stability
Optimal stability and noise rejection will be achieved with power*supply decoupling capacitors close to VCC.
The thermal resistance from junction to ambient Rthj−a strongly depends on board design. RthJA = 50 K/W in free air is a typical value which may be used even if NCN49599 is soldered on a PCB mounted in a small closed box, provided the transmission of frames are infrequent and widely spread in time. This typical value is also used in the generation of the curves plotted in Figures 18 and 19. Figure 18 shows the SOA in function of output current IL and output voltage VL with the ambient temperature as independent parameter. The maximum allowed current is 800 mA RMS. For that reason it is recommended to limit the output current by using RLIM = 5 kW. This current limitation is plotted as a horizontal line. The maximal output voltage is limited by VCC,max, VOH and VOL. This results in the straight line on the right hand side of the VL − IL plot. The area below and left from these limitations is considered as safe. The relation between output voltage and current is the impedance as seen at the output of the power operational amplifier. Constant impedance lines are represented by canted lines.
Current protection
The current protection is set by the RLIM resistor. It limits the output both when sourcing and sinking current. Once the protection is trigged the ILIM flag will go logic High signaling the user to take any necessary action. When the current output recovers, the ILIM flag will return to logic Low. To guarantee correct operation it is recommended to set RLIM = 5 kW This ensures the current will not exceed 1.2 A causing damage. See also paragraph Safe Operating Area. Thermal protection
In the event load conditions cause internal over*heating, the amplifier will go into shutdown to prevent damage. Thermal shutdown takes place at an internal junction temperature of approximately 160_C; the amplifier will recover to the Enabled mode when the junction temperature cools back down to approximately 145_C. Safe Operating Area
The Safe operating area (SOA) of the power amplifier is defined by 3 parameters:
Figure 18. SOA in VL–IL space (bottom left corner is safe) with RthJA = 50 K/W
exactly the same information as Figure 18 but might be easier to work with. Here constant current values are now represented as canted lines.
Although voltage−versus−current is the normal representation of safe operating area, a PLC line driver can only control one of these variables: voltage and current are linked through the mains impedance. Figure 19 displays
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NCN49599
Figure 19. SOA in ZL–VL Space (bottom right corner is safe)
Receiver Path Description
pass active filter to attenuate the mains frequency. This high pass filter output is followed by a gain stage which is used in an automatic gain control loop. This block also performs a single ended input to differential output conversion. This gain stage is followed by a continuous time low pass filter to limit the bandwidth. A 4th order sigma delta converter converts the analog signal to digital samples. A quadrature demodulation for fS and fM is than performed by an internal DSP, as well the handling of the bits and the frames.
Receiver Block Diagram
The receiver takes in the analog signal from the line coupler, conditions it and demodulates it in a data−stream to the communication controller. The operation mode and the baud rate are made according to the setting in R_CONF, R_FS and R_FM. The receive signal is applied first to a high pass filter. Therefore NCN49599 has a low noise operational amplifier at the input stage which can be used to make a high RX_OUT
RX_IN
Receiver (Analog Path) FROM DIGITAL
LOW NOISE OPAMP Gain
LPF
REF_OUT
4th order SD AD
TO DIGITAL
REF
1,65 V
PC20090610.2
Figure 20. Analog Path of the Receiver
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NCN49599 FROM TRANSMITTER
Receiver (Digital Path)
fMI
f MQ f SI
Quadrature Demodulator
fSQ nd
FROM ANALOG
2 Noise Shaper
st
1
Decimator
Decimator
fMQ
Compen− sator
nd
2
nd
2
Abs value accu
AGC Control
Sliding Filter
IS
Sliding Filter
Decimator
f SQ
nd
2
Decimator
Sliding Filter
QM
Decimator
fSI TO GAIN
IM
QS
fM
fS
Sliding Filter
PC20110610.3
Figure 21. Digital Path of the Receiver ADC and Quadrature Demodulation 50/60 Hz Suppression Filter
noise operational amplifier. REF_OUT is the analog output pin which provides the voltage reference (1.65 V) used by the A/D converter. This pin must be decoupled from the analog ground by a 1 mF ceramic capacitance (CDREF). It is not allowed to load this pin.
NCN49599 receiver input provides a low noise input operational amplifier in a follower configuration which can be used to make a 50/60 Hz suppression filter with a minimum number of external components. Pin RX_IN is the positive input and RX_OUT is the output of the input low R2 Received Signal
VIN
C2
C1
RX_OUT
RX_IN
2
3
Receiver (S−FSK Demodulator) LOW NOISE OPAMP TO AGC
R1 REF_OUT 4 1,65 V
CDREF
REF
VSSA
PC20090722.1
Figure 22. External Component Connection for 50/60 Hz Suppression Filter
50 Hz is obtained. Figure 22 represents external components connection. In a typical application the coupling transformer in combination with a parallel capacitance forms a high pass filter with a typical attenuation of 60 dB. The combined effect of the two filters decreases the voltage level of 230 Vrms at the mains frequency well below the sensitivity of the NCN49599.
RX_IN is the positive analog input pin of the receiver low noise input op−amp. Together with the output RX_OUT an active high pass filter is realized. This filter removes the main frequency (50 or 60 Hz) from the received signal. The filter characteristics are determined by external capacitors and resistors. Typical values are given in Table 26. For these values and after this filter, a typical attenuation of 85 dB at
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NCN49599 T
20
Vin/Vrx_out (dB)
−20
−60
−100
−140 10
100
1k Frequency (Hz)
10k
100k
Figure 23. Transfer Function of 50 Hz Suppression Circuit
Table 26. VALUE OF THE RESISTORS AND CAPACITORS Component
Value
Unit
C1
1.5
nF
C2
1.5
nF
CDREF
1
mF
R1
22
kW
R2
11
kW
f−3dB = 138 kHz and is internally trimmed to compensate for process variation.
Remark: The analog part of NCN49599 is referenced to the internal analog ground REF_OUT = 1.65 V (typical value). If the external circuitry works with a different analogue reference level one must be sure to place a decoupling capacitor.
A/D Converter
The output of the low pass filter is input for an analog 4th order sigma−delta converter. The DAC reference levels are supplied from the reference block. The digital output of the converter is fed into a noise shaping circuit blocking the quantization noise from the band of interest, followed by a decimation and a compensation step.
Auto Gain Control (AGC)
The receiver path has a gain stage which is used for automatic gain control. The gain can be changed in 8 steps of 6 dB. The control of the AGC is done by a digital circuit which measures the signal level after the AD converter, and regulates the average signal in a window around a percentage of the full scale. The AGC works in two cycles: a measurement cycle at the rising edge of the CHIP_CLK and an update cycle starting at the next CHIP_CLK.
Quadrature Demodulator
The quadrature demodulation block takes the AD signal and mixes it with the in−phase and quadrature phase of the fS and fM carrier frequencies. After a low pass filter and rectification the mixer output signals are further processed in software. There the accumulation over a period of CHIP_CLK is done which results in the discrimination of data 0 and data 1.
Low Noise Anti Aliasing Filter
The receiver has a 3rd order continuous time low pass filter in the signal path. This filter is in fact the same block as in the transmit path which can be shared because NCN49599 works in half duplex mode. The typical corner frequency
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NCN49599 Bit Sync
cross detector and loop delay in the Rx−filter circuitry will cause a shift between the physical transmitted bit and the received S−FSK signal as illustrated in Figure 24.
At the transmit side the data−stream is in sync and in phase with the zero crossing of the mains. The complex impedance of the power line together with propagation delay in the zero Mains
t
Transmitted bit stream
Bit 0
Bit1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Modulation
Transmission over the Power Line
PC20101119 .1
Bit delay
Figure 24. Bit Delay Cause by Transmission Over a Power Line
Communication Controller The Communication Controller block includes the ARM CORTEX M0 32 bit RISC processor, its peripherals: Data and Program RAM, Program ROM, TIMERS 1 and 2, Interrupt Control, SPI interface to an optional external Flash memory, TEST Control, Watchdog and Power On Reset (POR), I/O ports and the Serial Communication Interface (SCI). The micro−processor is programmed to handle the physical layer (chip synchronization), and the MAC layer conform to IEC 61334−5−1. The program is stored in a masked ROM. Depending on status of the SEN input, after power on reset NCN49599 will boot from internal ROM , external Flash or over the serial interface. The RAM contains the necessary space to store the program and the working data. The back−end interface is done through the Local Port and Serial Communication Interface block. This back−end is used for data transmission with the application micro controller (containing the application layer for concentrator, power meter, or other functions) and for the definition of the modem configuration. More boot options and further details can be found in Reference 1. The following section will give a brief overview of the functionality when boot from ROM. More details can be found in Reference 1.
To compensate for this delay between physical and demodulated bit a synchro bit value is introduced. It shifts forward the Hardware Demodulating process up to seven chip clocks. See Figure 25. CHIP_CLK
SBV[2:0] = 0
Bit 0
SBV[2:0] = 3
Bit1
Bit 2 PC20101119 .2
Figure 25. Compensation for Bit Delay by Shifting Forward the Start of the Demodulating Process
The synchro bit value can be set using register SBV [2:0]. Table 27. SYNCHRO BIT VALUE SBV[2:0]
Bit Delay
000
0 CHIP_CLK
001
1 CHIP_CLK
010
2 CHIP_CLK
011
3 CHIP_CLK
100
4 CHIP_CLK
101
5 CHIP_CLK
110
6 CHIP_CLK
111
7 CHIP_CLK
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NCN49599
Communication Controller Data / Program RAM
TxD RxD T_REQ BR0
Serial Comm. Interface
Program ROM
BR1 ARM Risc Core
Timer 1 & 2
5
Local Port
TO TRANSMIT FROM RECEIVER
POR
Interrupt Control
IO[9:3] RX_DATA CRC TXD/ PRES RESB
Watchdog
Test Control
Flash SPI
TEST
PC20 12053 0.4
SDI
SDO
CSB
SEN
Figure 26. Communication Controller Local Port
(CRC) is correct. TXD/PRES is the output for either the transmitting data (TX_DATA) or a synchronization signal with the time−slots (PRE_SLOT). When booting from ROM (SEN = VSS) IO[9:3] have no function. These IO’s can be addressed when booting from the external Flash. See also Reference 1.
The controller uses 3 output ports to inform the actual status of the PLC communication. RX_DATA indicates if NCN49599 is waiting for its configuration, if it is in research of synchronization, or if it is receiving data. CRC indicates if the received frames are valid: the cyclic redundancy code Table 28. OVERVIEW FUNCTIONALITY LOCAL PORT Port RX_DATA
CRC
Function Data reception
CRC OK
TX_DATA TXD/PRES PRE_SLOT
Value
Explanation
10 Hz
Waiting for configuration
0
After Synchro Confirm Time−out
1
Research of synchronization
Remark Output is oscillating
0 1
During the pause between 2 timeslots when a correct frame is received
0
Transmit of fS
1
Transmit of fM
0
See Figure 14
1
See Figure 14
R_CONF[7] = 1
R_CONF[7] = 0
Serial Communication Interface (SCI)
The Serial Communication Interface allows asynchronous communication. It can communicate with a UART = Universal Asynchronous Receiver Transmitter, ACIA = Asynchronous Communication Interface Adapter and all other chips that employ standard asynchronous serial communication. The serial communication interface has following characteristics: • Half duplex.
• • • • •
Standard NRZ format. Start bit, 8 data bits and 1 stop bit. Hardware programmable baud−rate via BR0 and BR1 pins (9600, 19200, 38400 and 115200 baud). 0−5 V levels with open drain for TxD. 0−5V levels for RxD and T_REQ. http://onsemi.com 33
NCN49599 3V3_D
NCN49597 TxD RxD T_REQ
Serial Comm. Interface
ARM Risc Core
Application Micro Controller
BR0 BR1 5
IO[9:3] RX_DATA CRC TXD/PRES
Local Port
Communication Controller PC 20120530.5
Figure 27. Connection to the Application Microcontroller Serial Communication Interface Physical Layer Description
The following pins control the serial communication interface. TXD: Transmit data output. It is the data output of the NCN49599 and the input of the application micro controller. RXD: Receive data input. It is the data input of the NCN49599 and the output of the application micro controller. T_REQ: Transmit Request input Request for data transmission received from the application micro controller BR0, BR1: Baud rate selection inputs. These pins are externally strapped to a value or controlled by the external application micro controller. Table 29. BR1, BR0 BAUD RATES BR1
BR0
SCI Baud Rate
0
0
115200
0
1
9600
1
0
19200
1
1
38400
IDLE (mark)
LSB Start
tBIT PC20080523.3
D0
MSB D1
D2
D3
D4
8 data bits
D5
D6
D7
IDLE(mark) Stop
tBIT
1 character
Figure 28. Data format Arbitration and Transfer
In order to avoid collisions between the data sent by the NCN49599 and the application micro controller, the NCN49599 is chosen as the transmitting controller. This means that when there is no local transfer, the NCN49599 can initiate a local communication without taking account of the application micro controller state. On the other hand, when the application micro controller wants to send data (using a local frame), it must first send a request for communication through the local input port named T_REQ (Transmitting Request). Then the NCN49599 answers with a status message. http://onsemi.com 34
NCN49599 Transfer from application micro controller to NCN49599
When the application micro controller wants to initiate a local transfer, it must pull down the T_REQ signal. The NCN49599 answers within the tPOLL delay with the status message in which the application micro controller can read if the communication channel is available. If the communication is possible, the application micro controller can start to send its local frame within the tSR delay. It should pull up the T_REQ signal as soon as the first character (STX) has been sent. If the beginning of the local frame is not received before the tSR delay was issued, the NCN49599 ignores the local frame. At the end of the data reception sent by the application micro controller on the RxD line, the NCN49599 sends a byte on the TxD line in order to inform about the status of the transmitting (=0x06) or (=0x15). Remark: If the application micro controller only wants to know the state of the NCN49599, it has just to pull up the T_REQ signal after the reception of the status message. T_REQ
tPOLL
TxD
StatusMessage
ACK tSR
tACK
RxD
Local Frame from Base Micro PC20080523.5
Figure 29. Transfer from Application microcontroller to NCN49599
If the length and the checksum of the local frame are both correct, the NCN49599 acknowledges with an character. In other cases, it answers with a character. In case of response, or no acknowledgement from NCN49599 in the tACK time−out, a complete sequence must be restarted to repeat the frame. Transfer from NCN49599 to application micro controller
When the NCN49599 wants to send a frame, it can directly send it without any previous request. T_REQ
TxD
Local Frame from NCN49599
Local Frame from NCN49599 tACK
RxD
t WBC
Local Frame from NCN49599 tACK
NAK
t WBC
ACK PC20080523.6
Figure 30. Transfer from NCN49599 to Application Micro Controller
If the length and the checksum of the local frame are both correct, the application micro controller acknowledges with an character. In other cases, it answers with a character. In case of response from the Application micro controller, the NCN49599 will repeat the frame only once after a delay corresponding to tWBC (Wait Before Continue). A non response from the application micro controller or a framing error when an character is awaited is considered as an acknowledgment.
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NCN49599 Character time−out in Reception
The time between two consecutive characters in a local frame should not exceed tIC (Time−out Inter Character):
tIC
Character PC20080523 .7
Character
t
Figure 31. Character Time−out
After this delay, the frame reception is finished. If the length and the checksum are both correct, the local frame is taken in account otherwise all previous characters are discarded. The time out Inter Character (tIC) is set by default at 10ms after a reset. The time out Inter character (tIC) is modified by the bit 7 of repeater parameter in the configuration frame. See Reference [1]: • Bit 7 = 1 −> the tIC value is constant at 10 ms,
• Bit 7 = 0 −> the tIC value represents 5 characters depending on the communication speed (defined by two local input ports BR0 and BR1).
Table 30. SERIAL COMMUNICATION TIME−OUT VALUES Time−out Tpoll
Meaning
Value
Delay max. awaited by the base micro between the T_REQ pull down and the status message transmission (delay polling)
20 ms
Tsr
Delay max. awaited by the NCN49599 between the end of the status transmitting and the reception of the STX character in the base micro frame (delay status/reception)
200 ms
Tack
Delay max. awaited by either the NCN49599 or the base micro between the end of a transmitting and the reception of the ACK or NAK character sent by the other (delay ack).
40 ms
Twbc
Delay max. awaited by either the NCN49599 or the base micro between the end of a reception and the transmission of the next frame (delay waiting before continue).
5 ms
Tic
Delay max. awaited by either the NCN49599 or the base micro between two characters (delay inter characters) Programmable with the bit 7 of repeater parameter in the configuration frame
Bit 7 = 1 Bit 7 = 0
10 ms 4800 baud
10 ms
9600 baud
5 ms
19200 baud
2.5 ms
38400 baud
1.25 ms
Watchdog
The watchdog supervises the ARM and in case the firmware doesn’t acknowledge at periodic times, a hard reset is generated. Configuration Registers
A number of configuration registers can be accessed by the user by sending a WriteConfig_Request over the SCI interface. See also Reference [1]. A brief overview of the accessible configuration registers is given below: R_CONFIG register configures the NCN49599 in the correct mode. The R_CONFIG register is controlled by the embedded software and can be accessed via a WriteConfig_Request.
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NCN49599 Table 31. R_CONF[9:0] ARM Register
Hard Reset
Soft Reset
Description
R_CONF[7]
0
−
TXD/PRES_SEL
R_CONF[5:3]
000
−
MODE
R_CONF[2:1]
00
−
BAUDRATE
R_CONF[0]
0
−
MAINS_FREQ
Where: TXD/PRES_SEL: 0: 1: MODE: 000 : 001 : 010 : 011 : 1xx : BAUDRATE: 00: 01: 10: 11: MAINS_FREQ: 0: 1:
TXD/PRES is PRE_SLOT output pin TXD/PRES is TX_DATA output pin Initialization Master Mode Slave Mode Reserved Test Mode 6 data bits per mains period = 300 baud @ 50 Hz 12 data bits per mains period = 600 baud @ 50 Hz 24 data bits per mains period = 1200 baud @ 50 Hz 48 data bits per mains period = 2400 baud @ 50 Hz 50 Hz 60 Hz
R_FS and R_FM step registers are defining the space and mark frequency. Explanation on the values can be found in paragraph Sine wave generator. This register can be accessed via a WriteConfig_Request. Table 32. FS AND FM STEP REGISTERS ARM Register
Hard Reset
Soft Reset
Description
R_FS[15:0]
0000h
0000h
Step register for the space frequency fS
R_FM[15:0]
0000h
0000h
Step register for the mark frequency fM
R_ZC_ADJUST register defines the value which is pre−loaded in the PLL counter. This is used to fine tune the phase difference between CHIP_CLK and the – to + zero cross of the mains. Explanation on the values can be found in paragraph 50/60 Hz PLL. Table 33. ZC_ADJUST REGISTERS ARM Register R_ZC_ADJUST[7:0]
Hard Reset
Soft Reset
Description
02h
02h
Fine tuning of phase difference between CHIP_CLK and rising edge of Mains zero cross
R_ALC_CTRL register enables or disables the Automatic Level Control. In case ALC is disabled the attenuation of the TX output driver is fixed according to the value in R_ALC_CTRL[2:0]. Explanation on the attenuation values can be found in paragraph Amplifier with Automatic Level Control. Table 34. ALC_CTRL REGISTERS ARM Register R_ALC_CTRL[3:0]
Where: R_ALC_CTRL[3]: R_ALC_CTRL[2:0]:
0: 1:
Hard Reset
Soft Reset
00h
00h
Description Control register for the automatic level control
Automatic level control is enabled Automatic level control is disabled and attenuation is fixed Fixed attenuation value
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NCN49599 Table 35. FIXED TRANSMITTER OUTPUT ATTENUATION ALC_CTRL[2:0]
Attenuation
000
0 dB
001
−3 dB
010
−6 dB
011
−9 dB
100
−12 dB
101
−15 dB
110
−18 dB
111
−21 dB
Reset and Low Power
NCN49599 has 2 reset modes: hard reset and soft reset. The hard reset initializes the complete IC (hardware and ARM) excluding the data RAM for the ARM. This makes sure that start−up of hardware and ARM is guaranteed. A hard reset is active when pin RESB = 0 or when the power supply VDD < VPOR (See Table 15). When switching on the power supply the output of the crystal oscillator is disable until a few 1000 clock pulses have been detected, this to enable the oscillator to start up. The soft reset initializes part of the hardware. The soft reset is activated when going into initialization mode for the duration of maximum 1 CHIP_CLK. Initialization mode is entered by R_CONF[5:3] = 000. The concept of NCN49599 has a number of provisions to have low power consumption. When working in transmit mode the analogue receiver path and most of the digital receive parts are disabled. When working in receive mode the analog transmitter and most if the digital transmit parts, except for the sine generation, are disabled. When the pin RESB = 0 the power consumption is minimal. Only a limited power is necessary to maintain the bias of a minimum number of analog functions and the oscillator cell. REFERENCE In this document references are made to: 1. Design Manual NCN49599 http://www.onsemi.com 2. EN 50065−1: Signaling on low−voltage electrical installations in the frequency range 3 kHz to 148.5 kHz http://connect.nen.nl/~/Preview.aspx?artfile=4257 28&RNR=66840 3. ERDF−CPT−Linky−SPEC−FONC−CPL version V1.0 Linky PLC profile functional specification http://www.erdfdistribution.fr/medias/Linky/ERD F−CPT−Linky−SPEC−FONC−CPL.pdf
4. DLMS UA 1000−2 Ed. 7.0 DLMS/COSEM Architecture and Protocols http://www.dlms.com/documentation/dlmsuacolou redbookspasswordprotectedarea/index.html 5. IEC 61334−5−1 Lower layer S−FSK Profile. http://webstore.iec.ch/preview/info_iec61334−5−1 %7Bed2.0%7Db.pdf 6. IEC 61334−5−1 Lower layer S−FSK Profile. http://webstore.iec.ch/preview/info_iec61334−5−1 %7Bed2.0%7Db.pdf
Table 36. ORDERING INFORMATION Temperature Range
Package
Shipping†
NCN49599MNG
−40°C – 125°C
QFN−56 (Pb−Free)
Tube
NCN49599MNTWG
−40°C – 125°C
QFN−56 (Pb−Free)
Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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NCN49599 PACKAGE DIMENSIONS QFN56 8x8, 0.5P CASE 485CN ISSUE O
ÉÉ ÉÉ
PIN ONE LOCATION
A B
D
L1 DETAIL A
E
ALTERNATE CONSTRUCTIONS
TOP VIEW DETAIL B
0.10 C 0.08 C
SIDE VIEW
SEATING PLANE
C
D2
MOLD CMPD
ALTERNATE CONSTRUCTION
A1 0.10
DETAIL A
DIM A A1 A3 b D D2 E E2 e K L L1
DETAIL B
(A3) A
NOTE 4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25mm FROM THE TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
ÉÉ ÉÉ
EXPOSED Cu
0.15 C 0.15 C
L
L
56X
RECOMMENDED MOUNTING FOOTPRINT*
C A B
M
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 8.00 BSC 6.50 6.70 8.00 BSC 6.50 6.70 0.50 BSC 0.20 −−− 0.30 0.50 0.05 0.15
8.30
L 0.10
M
56X
6.74
C A B
0.60
1 E2 8.30
6.74 1
K
56
e e/2 BOTTOM VIEW
56X
b 0.10
M
C A B
0.05
M
C
PKG OUTLINE
NOTE 3
0.50 PITCH
56X
0.32 DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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[email protected]
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NCN49599/D
