NAND Flash Module 69F96G24 69F192G24 FEATURES: Preliminary

NAND Flash Module Preliminary 69F96G24 69F192G24 FEATURES: High density 32Gbit per FLASH NAND die Supports higher speed designs with less capacitanc...
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NAND Flash Module Preliminary

69F96G24 69F192G24

FEATURES: High density 32Gbit per FLASH NAND die Supports higher speed designs with less capacitance/fewer I/O's to drive NAND Flash Interface Single Level Cell (SLC) Technology ONFI 2.2 Compliant Operating Voltage VCC 3.0 - 3.6V VCCQ 1.7 - 1.95V or 3.0-3.6V Page Size 8640 bytes (8192 + 448 spare bytes) Supports external BCH correction algorithms (16 bit correction per 540 bytes) Features High reliability data storage for demanding space applications Ceramic hermetic package with built-in TID shielding Three separate FLASH memory banks, supports TMR error correction Class E, I, H or K Speed Asynch: Up to asynch timing mode 5 (50MT/sec) Synch: Up to synchronous timing mode 5 (200MT/sec) Temperature Range -55⁰C to 125⁰C Endurance 60,000 cycles Feb 2015

Maxwell Technologies 1

Preliminary

NAND Flash

96Gb, 192Gb X 24 32Gb die FFh FCh FAh EEh EFh 70h

Supported Commands: Reset Synchronous Reset Reset LUN Get Features Set Features Read Status Read Status; Samsung only (Interleave) Read Status Enchanced (Multi-LUN) Change Read Column (Random data output) Change Read Column Enhanced Change Write Column (Random data input) Change Row Address Read Mode Read Page Read Page Interleaved (multi-plane) Read Page Cache Sequential Read Page Cache Random Read Page Cache Last Program Page Program Page Interleaved (multi-plane) Program Page Cache Erase Block Erase Block Interleaved (multi-plane) Copyback Read Copyback Program Copyback Program Interleaved (multi-plane) Read Unique ID Read Parameter Page Read ID

78h 05h 05h 85h 85h 00h 00h 00h 31h 00h 3Fh 80h 80h 80h 60h 60h 00h 85h 85h EDh ECh 90h

-

E0h E0h 30h 32h 31h 10h 11h 15h D0h D1h 35h 10h 11h -

Not Supported Odd to Even Page Copyback Non-sequential page programming 16 bit data bus width per Target/LUN Extended ECC Synchronous Mode: clock stopped for data input

Feb 2015

Maxwell Technologies 2

Preliminary

NAND Flash

96Gb, 192Gb X 24

Array Organization: 32Gb Die

Cycle First Second Third Fourth Fifth

DQ7 CA7 L BA7 BA15 L

DQ6 CA6 L PA6 BA14 L

DQ5 CA5 CA13 PA5 BA13 L

DQ4 CA4 CA12 PA4 BA12 L

DQ3 CA3 CA11 PA3 BA11 LUN

DQ2 CA2 CA10 PA2 BA10 BA18

DQ1 CA1 CA9 PA1 BA9 BA17

DQ0 CA0 CA8 PA0 BA8 BA16

CA[n] = Column Address PA[n] = Page Address BA[n] = Bank Address LUN = Logical Unit Address Row Address = LUN, Bank, Page Address BA[7] = Plane select Column Addresses above 8639 are invalid (page size = 8192 + 448) Memory Organization Bytes per page: 8192 Spare ECC bytes per page: 448 Pages per block: 128 Blocks per LUN: 4096 LUNs per chip enable: 2 Column address cycles: 2 Row address cycles: 3 Bits per cell: 1 Bad blocks maximum per LUN: 80 Block endurance: 60,000 Programs per page: 4 Number of bits ECC required: 8 (for 512 Bytes) Number of interleave address bits: 1

Feb 2015

Maxwell Technologies 3

Preliminary

NAND Flash

96Gb, 192Gb X 24

Package Organization

192Gb X 24

Package Sync

Async

CE#-1 DQS-1 CLK-1 DQ[7-0]-1

CE#-1 N/A-1 WE#-1 DQ[7-0]-1

Target-1 LUN 1

LUN 2

Target-2 CE#-2 DQS-2 CLK-2 DQ[7-0]-2

CE#-2 N/A-2 WE#-2 DQ[7-0]-2

LUN 1

LUN 2 R/B#

Target-3 CE#-3 DQS-3 CLK-3 DQ[7-0]-3

ALE W/R# CLE WP#

CE#-3 N/A-3 WE#-3 DQ[7-0]-3

LUN 1

LUN 2

ALE RE# CLE WP#

Architecture Independent 8 bit buses per package: 3 Targets per 8 bit bus: 1 LUNS per Target: 2 (2 die per 8 bit bus) (6 die per package)

DQ[7-0]-1 CE#-1 WE-1#/CLK-1 DQS-1 DQ[7-0]-2 CE#-2 WE#-2/CLK-2 DQS-2 DQ[7-0]-3 CE#-3 WE#-3/CLK-3 DQS-3 Shared

Feb 2015

ALE RE#, W/R# CLE WP# RB#

Maxwell Technologies 4

Preliminary

NAND Flash

96Gb, 192Gb X 24

Package Organization

96Gb X 24

Package Sync

Async

CE#-1 DQS-1 CLK-1 DQ[7-0]-1

CE#-1 N/A-1 WE#-1 DQ[7-0]-1

Target-1 LUN 1

Target-2 CE#-2 DQS-2 CLK-2 DQ[7-0]-2

LUN 1

CE#-2 N/A-2 WE#-2 DQ[7-0]-2

R/B#

Target-3 CE#-3 DQS-3 CLK-3 DQ[7-0]-3

ALE W/R# CLE WP#

CE#-3 N/A-3 WE#-3 DQ[7-0]-3

LUN 1

ALE RE# CLE WP#

Architecture Independent 8 bit buses per package: 3 Targets per 8 bit bus: 1 LUNS per Target: (1 die per 8 bit bus) (3 die per package)

DQ[7-0]-1 CE#-1 WE-1#/CLK-1 DQS-1 DQ[7-0]-2 CE#-2 WE#-2/CLK-2 DQS-2 DQ[7-0]-3 CE#-3 WE#-3/CLK-3 DQS-3 Shared

Feb 2015

ALE RE#, W/R# CLE WP# RB#

Maxwell Technologies 5

Preliminary

NAND Flash

Feb 2015

96Gb, 192Gb X 24

Maxwell Technologies 6

Preliminary

NAND Flash

96Gb, 192Gb X 24

Pinout Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Pin Description VCC VSS CLE CE#-1 CE#-2 CE#-3 VCC VSS WE#-CLK-1 RB# WE#-CLK-2 VCCQ VSSQ WE#-CLK-3 RE#-W/R# ALE VCC VSS DQS-1 VCCQ VSSQ DQ7 DQ6 DQ5 DQ4 VCCQ VSSQ DQ3 DQ2 DQ1 DQ0 VCCQ VSSQ VCC VSS

Pin Description VCCQ VSSQ DQ16 DQ17 DQ18 DQ19 VCCQ VSSQ DQ20 DQ21 DQ22 DQ23 VCCQ VSSQ DQS-3 VCC VSS WP# DQS-2 VCCQ VSSQ DQ15 DQ14 DQ13 DQ12 VCCQ VSSQ DQ11 DQ10 DQ9 DQ8 VCCQ VSSQ VCC VSS

Pin # 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36

Three 8 bit buses; Each with its own CS[0-2], DQS[0-2] & WE#CLK[0-2] Three chip selects for 6 die using Multi-LUN operation. All other control signals are shared; CLE, RB#, RE#-W/R#,ALE & WP#

Feb 2015

Maxwell Technologies 7

Preliminary

NAND Flash Feature Summary

Description ONFI 1.0, 2.0, 2.1, 2.2 Program page register clear enhancement Extended parameter page Interleaved(multi-plane) read operations Synchronous interface Odd to even page copyback Interleaved (multi-plane) operations Non-sequential page programming Multiple LUN operations 16 bit data bus width per LUN RESET LUN command Small data move CHANGE ROW ADDRESS CHANGE READ COLUMN ENHANCED READ UNIQE ID COPYBACK READ STATUS ENHANCED GET FEATURES & SET FEATURES Read cache commands PROGRAM PAGE CACHE Number of data bytes per page Number of spare bytes per page Number of bytes per partial page Numpber of spare bytes per partial page Number of pages per block Number of blocks per LUN Number of LUNs per chip enable Number of address cycles Column address cycles Row address cycles Number of bits per cell Bad blocks maximum per LUN Block endurance Guaranteed valid blocks at beginning Block endurance for guranteed valid blocks Number of programs per page Number of bits ECC correctability Number of interleaved address bits Interleaved read cache Interleaved address restrictions for cache operations Interleaved program cache support Interleaved block address restrictions Overlapped/concurrent interleaving I/O pin maximum capacitance per target Driver Strength; Overdrive 1 & 2 tPROG Typical (Page Program) tBERS Typical (Block Erase) tR max (Page Read) tCCS Typical (change column setup) Input pin capacitance, typical

Feb 2015

96Gb, 192Gb X 24 32Gb die Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 8192 448

128 4096 2 2 3 1 80 60,000 1 0 4 8 1 Yes Yes Yes No Yes Yes 515 us 7 ms 35 us 200 ns 6 pF

Maxwell Technologies 8

Preliminary

NAND Flash

96Gb, 192Gb X 24

Product Ordering Options 69F

XXX G

24

XX

F

X

Screening Flow K = Maxwell Class K H = Maxwell Class H I = Industrial (testing @ -55⁰C, +25⁰C +125⁰C ) E = Engineering (testing at +25⁰C )

Package F = Flat Pack Radiation Feature RP = RAD -PAK® Package Shielding

Data Width 24 = 24 bits wide

Total Gbits 96 = 96Gb 192 = 192Gb

Base Product 3.3V by 24 NAND FLASH SLC Nomenclature

Feb 2015

Maxwell Technologies 9

Preliminary

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