If the gate is “high”, the switch is on If the gate is “low”, the switch is off Drain
•
Digital integrated circuits use these transistors essentially as a voltage controlled switch
Gate
g=0 Source g=1
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1
nMOS Transistor
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2
nMOS Transistor
MOS: Metal Oxide Semiconductor
Cross Section Polysilicon Gate Source n+
Gate oxide Drain n+
L
Silicon Dioxide SiO2
Field-Oxide (SiO2)
p substrate Bulk (Body) Gate Drain
Source
Cross-section of an n-type transistor
B
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4
nMOS Transistor
nMOS Transistor Top View
•
Polysilicon Gate Source n+
L
Drain n+
•
W
p substrate
n areas have been doped with donor ions of concentration ND - electrons are the majority carriers p areas have been doped with acceptor ions of concentration NA - holes are the majority carriers
Bulk (Body)
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1
nMOS Transistor
nMOS Transistor
Source
Polysilicon Gate
Drain
VGS ≤ 0
Source
-
+
+
-
-
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
Drain
-
-
+ _
Gate oxide
Polysilicon Gate
Accumulation Mode
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nMOS Transistor
8
nMOS Transistor
Polysilicon Gate
Depletion Region Drain
-
Polysilicon Gate
VGS ≤ VT
Source
-
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-
-
+ _
Inversion Region VGS > VT
Source
-
-
Drain
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Depletion Mode
+ _
Inversion Mode
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nMOS Transistor
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10
nMOS Transistor
Depletion Region Polysilicon Gate
Inversion Region VGS > VT
Source
-
Drain
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+ _
n-channel enhancement MOS
Inversion Mode
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2
Threshold Voltage
Threshold Voltage
VT = VT 0 + γ ( − 2Φ F + VSB − 2Φ F ) •
Dependent on
•
Gate conductor material Gate insulator material Channel Doping Voltage difference between source and body
•
γ
is the body-effect coefficient and controls the impact of the source to bulk voltage Φ F is the Fermi potential and is dependent on doping levels • Fermi potential: potential difference between Fermi level and intrinsic Fermi level in the bulk of semiconductor.
ΦF =
kT N A ln q ni
k: Boltzmann constant, T: temperature, q: unit (electron) charge 3 March 2009
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pMOS Transistor
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pMOS Transistor Gate oxide
Polysilicon Gate Source
Drain
+ +
-
-
+ +
-
-
-
-
-
-
-
-
-
-
-
-
Accumulation Mode
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Source vs. Drain
16
nMOS Transistor Source
Drain
Gate
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Drain
Ids
Source
Gate
Gate
Ids
VGS > VT
Drain
+ _
+ _
VDS < VGS - VT
VDS < VGS – VT VGS – VDS > VT VGD > VT
Source nMOS: node with a higher voltage is drain, VD > VS
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pMOS: node with a higher voltage is source, VS > VD
17
Linear mode
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3
nMOS Transistor
MOS Transistor Characteristics Linear Mode: • VGS>VT and VGD>VT • Assume that VT is constant
Drain
Gate VGS > VT
+ _
+ _
VDS > VGS - VT
V2 I DS = kn (VGS − VT )VDS − DS 2
VDS > VGS – VT VGS – VDS < VT VGD < VT
Saturation mode
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• • • •
kn’
•
19
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MOS Transistor Characteristics
Example •
= ( µ nCox ) is called the process transconductance parameter Gain factor of nMOS: kn = kn’ W/L
•
Source
Saturation Mode: • VGS>VT and VGDVT, VDS>VGS-VT or VGDVGS-VT)
•
D
S
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Body Effect •
•
•
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Channel-Length Modulation We previously assumed a constant L In reality, when VDS > (VGS-VT), the channel is pinched off and the effective channel length is reduced. Net effect is that IDS is not constant in the saturated region.
•
We assumed that VSB=0 - i.e. the source potential equals the substrate potential In certain situations, this assumption is not true Has the effect of raising the threshold voltage •
26
•
•
A negative bias on the well or substrate causes the threshold to increase
Source
VDS > (VGS-VT)
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+
+
+
+
+
+
+
+
+
+
+
x 10
-4
VGS= 2.5 V 2
Linear region (VGS>VT, VDSVT, VDS>VGS-VT) I DS
-
28
Cutoff region (VGSVGS-VT) D
S
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•
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MOS Transistor
Velocity Saturation •
At small gate lengths, electric field becomes more pronounced Electrons get excited with enough energy to cause a substrate current This causes change of transistor parameters threshold voltage, current flow, etc.
Assumption was that carrier velocity is proportional to electric field When channel is small, and the voltage is large, the velocity can saturate
