Monolithic 3D IC: The Time is Now. Brian Cronquist and Zvi Or-Bach MonolithIC 3D Inc

Monolithic 3D IC: The Time is Now Brian Cronquist and Zvi Or-Bach MonolithIC 3D Inc. 2014 Intl. Workshop on Data-Abundant System Technology, April 20...
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Monolithic 3D IC: The Time is Now Brian Cronquist and Zvi Or-Bach MonolithIC 3D Inc.

2014 Intl. Workshop on Data-Abundant System Technology, April 2014

Agenda:  There is a Bright Future for the Semiconductor Industry, yet, we are reaching an Inflection Point  Monolithic 3D IC – The next generation technology driver  What is it?  Monolithic 3D provides more than just scaling

 Four paths proposed to enable monolithic 3D ICs  Path 3

 A few near–term applications  3D FPGA to prototype 2D SoC  Logic Redundancy  Memory on Logic

2014 Intl. Workshop on Data-Abundant System Technology, April 2014

The Bright Future The semiconductor opportunity is growing

$15-34 trillion, annual =>~$5T Semi /year

Source: McKinsey Institute Analysis 2014 Intl. Workshop Global on Data-Abundant System Technology,2013 April 2014

However… Semiconductor Industry is Facing an

Inflection Point Dimensional Scaling has reached Diminishing Returns

The Current 2D-IC is Facing Escalating Challenges  Lithography is

 On-chip interconnect is

 Dominating Fab cost  Dominating device cost and diminishing scaling’s benefits  Dominating device yield  Dominating IC development costs

 Dominating device power consumption  Dominating device performance  Penalizing device size and cost

2014 Intl. Workshop on Data-Abundant System Technology, April 2014

Cost per transistor is no longer scaling

Moore’s Law has stopped at 28nm

Embedded SRAM isn’t Scaling Beyond 28nm (1.1x instead off 4x) eSRAM > 60% of Die Area => End of Dimensional Scaling !

Dinesh Maheshwari, CTO, Memory Products Division at Cypress Semiconductors, ISSCC2014

Monolithic 3D – The next generation technology driver

“CEA-Leti Signs Agreement with Qualcomm to Assess Sequential (monolithic)3D Technology” Business Wire December 08, 2013

“Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” Geoffrey Yeap, VP of Technology at Qualcomm, Invited paper, IEDM 2013

MONOLITHIC 10,000x the Vertical Connectivity of TSV Enables:

TSV

Monolithic

Layer Thickness

∼50µ

~50nm

Via Diameter

~5µ

~50nm

Via Pitch

~10µ

~100nm

Wafer (Die) to Wafer Alignment

~1µ

~1nm

microns

nano-meters

Overall Scale

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Monolithic 3D version of the same 2D logic core is ½ silicon area and ¼ the footprint 22nm node 600MHz logic core

2D-IC

3D-IC 2 Device Layers

Comments

Metal Levels

10

10

Average Wire Length

6um

3.1um

Av. Gate Size

6 W/L

3 W/L

Since less wire cap. to drive

Die Size (active silicon area)

50mm2

24mm2

3D-IC  Shorter wires  smaller gates  lower die area  wires even shorter 3D-IC footprint = 12mm2

Power

Logic = 0.21W

Logic = 0.1W

Due to smaller Gate Size

Reps. = 0.17W

Reps. = 0.04W

Due to shorter wires

Wires = 0.87W

Wires = 0.44W

Due to shorter wires

Clock = 0.33W

Clock = 0.19W

Due to less wire cap. to drive

IntSim3D MonolithIC 3D Inc. Patents Pending Total = 1.6W Total = 0.8W

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The Monolithic 3D Challenge Why is it not already in wide use?  Processing on top of copper interconnects should not make the copper interconnect exceed 400oC  How to bring mono-crystallized silicon on top at less than 400oC  How to fabricate state-of-the-art transistors on top of copper interconnect and keep the interconnect below at less than 400oC

 Misalignment of pre-processed wafer to wafer bonding step is ~1um  How to achieve 100nm or better connection pitch  How to fabricate thin enough layer for inter-layer vias of ~50nm

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Layer Transfer (“Ion-Cut”/“Smart-Cut”)  The Technology Behind SOI Oxide

Hydrogen implant

Flip top layer and

of top layer

bond to bottom layer

Cleave using 400oC anneal or sideways mechanical force. CMP.

p- Si Top layer

Oxide p- Si

Oxide

Bottom layer

H

p- Si Oxide Oxide

H

p- Si

Oxide Oxide

 Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today

MonolithIC 3D - 3 Classes of Solutions  RCAT – Process the high temperature on generic structures prior to ‘smart-cut’, and finish with cold processes – Etch & Depositions  Gate Replacement (=Gate Last, HKMG) - Process the high temperature on repeating structures prior to ‘smart-cut’, and finish with ‘gate replacement’, cold processes – Etch & Depositions  Laser Annealing – Use short laser pulse to locally heat and anneal the top layer while protecting the interconnection layers below from the top heat

Two Major Semiconductor Trends help make Monolithic 3D Practical NOW  As we have pushed dimensional scaling:  The volume of the transistor has scaled  Bulk um-sized transistors transistors

FDSOI & FinFet nm

 Processing times have trended lower  Shallower & sharper junctions, tighter pitches, etc.

=> Much less to heat and for much shorter time

The Semi Industry Annealing Trend with Scaling

The Top Layer has a High Temperature (>1000°C) without Heating the Bottom Layers (1000°C

}

100x integration made possible VII. Enables Modular Design VIII. Naturally upper layers are SOI IX. Local Interconnect above and below transistor layer X. Re-Buffering global interconnect by upper strata XI. Others A. Image sensor with pixel electronics B. Micro-display

Reduction of Die Size & Power – Doubling Transistor Count

Extending Moore’s law  Reduction of Die Size & Power IntSim v2.0 free open source >600 downloads

  

Repeater count increases exponentially with scaling At 45nm, repeaters >50% of total leakage power of chip [IBM]. Future chip power, area could be dominated by interconnect repeaters [Saxena P., et al. (Intel), TCAD, 2004]

IV. Heterogeneous Integration  Logic, Memories, I/O on different strata  Optimized process and transistors for the function  Optimizes the number of metal layers  Optimizes the litho. (spacers, older node)

 Low power, high speed (sequential, combinatorial)  Different crystals – E/O

V. Multiple Layers Processed Simultaneously - Huge Cost Reduction (Nx) –”BICS”  Multiple thin layers can be process simultaneously, forming transistors on multiple layers  Cost reduction correlates with number of layers being simultaneously processed (2, 4, 8, 16, 32, 64, 128, ...)  Monocrystalline silicon enables MLC, thereby less layers needed

3D DRAM 3.3x Cost Advantage vs. 2D DRAM

Conventional stacked capacitor DRAM

Monolithic 3D DRAM with 4 memory layers

Cell size

6F2

Since non self-aligned, 7.2F2

Density

x

3.3x

26 (with 3 stacked cap. masks)

~26 extra masks for memory layers, but no stacked cap. masks)

Number of litho steps

MonolithIC 3D Inc. Patents Pending

VI. Logic Redundancy => 100x Integration Made Possible  It is well known the more we can integrate on one chip with reasonable yield, the better the cost & performance – Moore’s Law  Yield is the dominating criterion when to use PCB rather than on-chip integration

Innovation Enabling ‘Wafer Scale Integration’ – 99.99% Yield with 3D Redundancy Gene Amdahl -“Wafer scale integration will only work with 99.99% yield, which won’t happen for 100 years” (Source: Wikipedia)

 Swap at logic cone granularity  Negligible design and power penalty  Redundant 1µ above, no performance penalty

Server-Farm in a Box Watson in a Smart Phone …

MonolithIC 3D Inc. Patents Pending

VII. Enables Modular Design  Platform-based design could evolve to:  Few layers of generic functions like compute, radios, and one layer of custom design  Few layers of logic and memories and one layer of FPGA  ...

VIII. Upper Layers are naturally SOI  SOI wafers provides many benefits with one major drawback: cost of the blank wafer.  In monolithic 3D – all the upper strata are naturally SOI  At no cost

IX. Local Interconnect - Above and Below Transistor Layer  Increased complexity requires increased connectivity. Adding more metal layer increases the challenge of connecting upper layers to the transistor layer below.

Intel March, 2013

X. Re-Buffering Global Interconnect by Upper Strata  Global interconnect is done at the upper and thicker metal layers. It would increase efficiency if these layers could re-buffer instead of connecting to base layer using multiple vias and blocking multiple metal tracks. ⇒Use the layers above for re-buffering.

XI. Others A. Image Sensor with Pixel Electronics  With rich vertical connectivity, every pixel of an image sensor could have its own pixel electronics underneath

MonolithIC 3D Inc. Patents Pending

XI. Others B. Micro-display  Use of three crystal layers to form RGB LED arrays with drive electronics underneath

MonolithIC 3D Inc. Patents Pending

Step 1. Donor Layer Processing Step 1 - Implant and activate unpatterned N+ and P- layer regions in standard donor wafer at high temp. (~900oC) before layer transfer. Oxidize (or CVD oxide) top surface. SiO2 Oxide layer (~100nm) for oxide -to-oxide bonding with device wafer.

PN+ P-

Step 2 - Implant H+ to form cleave plane for the ion cut PN+ P-

MonolithIC 3D Inc. Patents Pending

H+ Implant Cleave Line in N+ or below

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Step 3 - Bond and Cleave: Flip Donor Wafer and Bond to Processed Device Wafer Cleave along H+ implant line using 400oC anneal or sideways mechanical force. Polish with CMP.

-

Silicon

N+

1um*

TSV pitch ~ 50-100nm

* [Reference: P. Franzon: Tutorial at IEEE 3D-IC Conference 2011]

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Ion-cut is great, but will it be affordable? Aren’t ion-cut SOI wafers much costlier than bulk Si today? •

Until 2012: Single supplier  SOITEC. Owned basic patent on ion-cut



Our industry sources + calculations  $60 ion-cut cost per $1500$5000 wafer in a free market scenario (ion cut = implant, bond, anneal).

Contents: Hydrogen implant Cleave with anneal

SOITEC basic patent expired Sep 2012



Free market scenario  After 2012 when SOITEC’s basic patent expires



SiGen and Twin Creeks Technologies using ion-cut for solar

Laser Spike Annealing  Types

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Major Thermal Process Steps in a Modern IC Process Step

Purpose

Thermal Budget

Replaceable?

With Laser?

Si3N4 LPCVD

STI and well

30 min – 700 °C

Yes

No

Liner Ox

STI

10 min –800 °C

Yes

No

TEOS Densification

STI

20 min – 1000 °C

Yes

Yes

Implant Activation

Well

20 sec – 1000 °C

Yes

Yes

Dummy Ox

Gate

2 min – 800 °C

Yes

No

Dummy a-Si deposition Selective epi deposition Silicide formation

Gate

20 min – 600 °C

Yes

No

SiGe and SiC S/D

20 min – 700 °C

Yes

No

S/D contact

5 min – 400 °C

Yes

Yes

Implant Activation

S/D, halo, Vt

5 sec – 950°C, +LSA

No

Yes

BIL oxide+N

Gate

5 min – 825 °C

Yes

No

HfO2 post ALD

Gate

30 sec – 700 °C

Yes

Yes

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IntSim: The CAD tool used for our simulation study [D. C. Sekar, J. D. Meindl, et al., ICCAD 2007]

Open-source tool, available for use at www.monolithic3d.com IntSim v1.0: Built at Georgia Tech in Prof. James Meindl’s group IntSim v2.0: Extended IntSim v1.0 to monolithic 3D using 3D wire length distribution models in the literature MonolithIC 3D Inc. Confidential, Patents Pending

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