Prof. Dr. J. Reichardt

Tools and Steps in the VHDL based ISE/ModelSim Design-Flow Specification Analysis Design of Block-Diagram

VHDL-Model on RT-Level

The only step where you really have to use your Brain! Text-Editor

*.vhd Functional VHDLsimulation *.vhd Synthesis and Implementation VHDL-Model on structural level with timing information

ModelSim XE *.do (Simulation control macro) Never forget the time-units (ns, us, ...) in time specifications

ISE 4.x / Webpack *.ucf (Device Pinout)

_timesim.vhd _timesim.sdf VHDL-based TimingSimulation

Generation of Programming File

ModelSim XE *.do (simulation control macro)

ISE 4.2 / iMPACT

*.svf or *.bit Programming and Test of CPLD or FPGA

Gxsload / Gxsport

Prof. Dr. J. Reichardt

ISE 4.2 CPLD and FPGA Designflows with External ModelSim_XE und Common Project Folder (J.R. 07.02.03) ISE: (Project configuration) 1. Start ISE from the desktop or via Windows Start→Programs→Xilinx ISE4→Project Navigator Create your common project ISE / Webpack folder: File→New Project Select your project folder. In Room R801 select C:\FNDTNWRK\lab Select the desired target hardware which could be either: - XC95108 pc84 (CPLD) Designflow: XST VHDL - XC4010XL-3pc84 (FPGA) Designflow: FPGA Express VHDL - XC2S50-5tq144 (Spartan FPGA) Designflow: XST VHDL For schematic entry based labs you will have to use: - XC95108 PC84 (CPLD) Designflow: Abel XST VHDL This always creates a NEW project folder and a *.NPL project file. ModelSim: (Functional VHDL-Simulation) 2. Start ModelSim from the desktop or via Windows Start→Programs→Xilinx ISE4→ModelSim 3. Create a Modelsim project (File->New->Project) in the just created project folder, give it the same name as the ISE-project. This creates a ModeSim project file *.MPF. 4. Copy /Create the VHDL-file(s) and DO-Files to the project folder (Hint: I do NOT encourage you to use the creation of VHD-files using the template which is offered by ISE because these templates use datatypes which are not suitable for this lab). 5. Design→Compile 6. Design→Load Design 7. Macro→Execute Macro ISE: (Design Implementiation) 8. Project→ Add Source (VHDL Module, eventually VHDL testbench) 9. "Synthesize", Check results with: View Synthesis Report 10. Open (+) and select "Implement Design" 11. Right mouse click (context menu): Properties Implementation User Constraints File: C:\fndtnwrk\xc95108.ucf or C:\fndtnwrk\xc4010xl.ucf (Select the ucf-file corresponding to the target hardware, File extension "ucf" NOT in capital letters!) Speed Grade: -15 OK 12. "Implement Design" 13. For CPLDs: "View Fitted Design (ChipViewer)" or. "Fitter Report" in order to analyze the pinout and logic equations For FPGAs: View "Place & Route Report" and "Pad Report" eventually: "ViewEdit Placed Design (Floorplanner)" or "ViewEdit Routed Design (FPGA Editor) " (Those tools are NOT part of the Webpack!!!) 14. "Generate Timing" For CPLDs: Timing Report For FPGAs: Analyze Post-Place&Route Static Timing 15. "Generate Post-Fit" respectively "Post-Place&Route Simulation Model", automatically creates _timesim.vhd (which is a structural VHDL-architecture named "structure") and _timesim.sdf (VITAL timing constants) ModelSim: (Post-Fit/Post-Route Timing Simulation) 16. Design→Compile _timesim.vhd 17. Design→Load Design first select: SDF-Tab : Add->Browse: _timesim.sdf, OK

Prof. Dr. J. Reichardt then select: Design-Tab, open the entity (E) and select architecture "structure". LOAD 18. Macro→Execute Macro (you can use the same Do-file as for the functional simulation) for CPLDs: ISE: (Creation of a SVF-program file) 19. "Configure Device (Impact)" starts the programmer tool Note: The flow first searches for a specific download cable which we don't use. The reltively wait time can be shortened if %xilinx_install_dir%\bin\nt\iMPACT.exe is started directly. Eventually an Impact-Icon exists on the desktop) Cable Communication Setup: Cancel 20. Mode→File Mode, then select the "SVF-STAPL" Tab, Answer the "Boundary Scan" note with "yes" 21. Output-→SVF-File→ Create SVF-File 22. Select the Xilinx-XC95108 CPLD symbol and click on it 23. Operations->Program (Erase before programming), OK 24. File→Exit (Save of CDF-Configuration file is not required) For FPGAs: ISE: (Create a *.BITprogram file) 19. "Generate Programming File" directly creates a *.BIT file which is used for FPGA programming GXSLOAD: (Download to the XS* Board) (supported only in R801 and R885) 25. Start Gxsload (V4.x) from the desktop or the windows start programs menu 26. Select the desired target board: XS95-108, XS40-010XL or XSA-50 27. Check the correct printer port (should be LPT 2 in the lab) 28. Open the project folder with the SVF- resp. BIT-file using windows explorer, Drag and Drop of program file into the FPGA/CPLD window of Gxsload 29. Activate "Load" in Gxsload

Prof. Dr. J. Reichardt

Short Guide for the Xilinx Schematic Entry Tool (ECS) (J.R. 07.02.03) ECS is a built-in schematic entry tool for Xilinx ISE which supports hierarchical designs. For XC9500 CPLDs a special design flow has to be chosen: Chose "Abel XST VHDL" while creating a schematic based project. In this design flow the schematic is first translated into a VHDL description (*.VHF files) so that it might be also simulated using a VHDL simulator. Create a new schematic project: File →New Project: Project-Name: C:\FNDTNWRK\Lab1 Device Family: XC9500 CPLDs Device: XC95108PC84 Design-Flow: Abel XST VHDL OK Create a new schematic in this project: Project→New Source: Schematic File-Name Lab1 Location: Add to project: ✔ Continue OK An empty schematic-window opens where you will have to: -

Place logic symbols Place input- and output buffers Wire the symbols and ports Place I/O markers on the schematic Rename the I/O markers Create a hierarchical symbol for a schematic Place user symbols on a new schematic

(, Category Logic) (, Category I/O) () (, Help: find "Adding an I/O marker") (select marker, chose context menu, object properties) (Tools → Create Symbol) (, Category: your project directory)

Save a schematic: File→ Save Add the schematic to the project: in ISE: Project→ Add Source (select the *.sch-file) (In hierarchical designs all *.sch files must be added!) Additional import notes: 1. The schematic editor uses the auto-repeat function which you can leave by pressing 2. Use Add Symbol / to open the symbol list window. Select a suitable category. Drag and drop the symbol horizontally to the schematic. Move it to the appropriate position. 3. You can't connect any two symbols directly to each other. A piece of wire must be in between the two symbols. Especially the I/O markers require a piece of wire in front of / behind the Input- / output buffers. 4. Connections to a higher schematic hierarchy level or to the outside world (from the top-level schematic) require I/O markers. Select the appropriate port direction (See the sub-window which opens: Select either Input or Output)) before you place the ports. Don't forget to rename the I/O ports to the desired signal names. The placement of I/O markers on the schematic must be very careful and accurate. 5. Note that the inputs and outputs from / to the outside world require input resp. output buffers (IBUF, OBUF) which must be located between the I/O markers and the first / last logic element. 6. In hierarchical designs it is helpful to rename the lower level instances to your individual demands

Prof. Dr. J. Reichardt

Command- (DO) file example for ModelSim XE # Model-Sim Macro-File # Here you'll find some examples for typical ModelSim commands: # Note that comment lines begin with an '#'. # J. Reichardt 13.08.02 # Note:!!! All timing parameters should specify quantity ns #----------------------------------------------------------------# Should be included in most cases: restart # Open the signals and wave windows #view structure view signals #view variables view wave # Default radix for input and output # Required if you wish to enter HEX-numbers from the keyboard radix hex # Display all signals in the waves-window: # General Syntax: add wave sim://* # Individual signal names can be specified in several "add wave" statements add wave sim:/seg7/* # First stimulus example: # Five individual signal value assignments partially at absolute time # (I recommend to always use time-units) force a 1 # The default time-step for one "run"-step is 100ns: run 100ns force a 2 run 100ns force a 3 @225ns force a 4 @250ns force a 7 @375ns run 200ns # Second stimulus example: # Periodical signal assignments (simulation will be continued!) # Set up a simple truth table with the -r(epeat) switch: # The signals periodically change between 0 and 1 # Value Time, Value Time force a(0) 0 0, 1 50ns -r 100ns force a(1) 0 0, 1 100ns -r 200ns force a(2) 0 0, 1 200ns -r 400ns force a(3) 0 0, 1 400ns -r 800ns # Finally force an individual signal value: force a 0 # Simulate for 1800ns run 1800ns # If you want to read something on the console you have to use the "echo" # or "examine" statements echo "The signal values are now:" examine a examine segments