Modelling of Systems on Chip Part of Tutorial A: Automatically Realising Embedded Systems From High-Level Functional Models Wido Kruijtzer, Victor Reyes NXP Semiconductors March 10, 2008

Outline NXP Products / challenges Abstraction Levels Functional Modeling Architecture Modeling Summary

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DATE 2008 Tutorial A - Wido Kruijtzer / Victor Reyes

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NXP Semiconductors – Reborn and Renewed Spin-out of Royal Philips Electronics’ Semiconductor Division #2 in Europe, Top-10 global supplier Sales of € 4.6 billion in 2007 37,000 employees / 7,500 engineers Investing € 950 million in R&D annually 25,000+ patents More than 26 R&D centers in 12 countries Headquarters: Eindhoven, The Netherlands Key focus areas: – Mobile & Personal, Home, Automotive & Identification, Multimarket 3

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Feature explosion in consumer products Imaging

Main display

Wired

USB

Aux display

Storage

Removable Flash

Camera

Small HDD

3D display

fixed flash

3D rendering Audio

audio codecs

SW features

Instant messaging

ring tones

PDA

MP3 Wireless

Java

GSM / GPRS modem

2-D game

UMTS / 3G Bluetooth

Setup & Control

Video

Mpeg2

FM tuner

Mpeg4

USB

H264

GPS

DivX

RF-ID WLAN DVB tuner

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Convergence of digital consumer products KID’S BEDROOM

MASTER BEDROOM

camera

Internet radio

broadband

INTERNET

TV-to-TV link

wireless LAN

home theater audio

portable display RF remote control STUDY

KITCHEN

Media Server (DVD+RW/HDD

LIVING ROOM

The connected home 5

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Some of today’s cars … ☺

http://www.aide-eu.org/pdf/aide_nf_050120_engstroem.pdf

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Convergence of digital consumer products Consequences: Large number of use cases Increasingly complex use cases Fast changing use cases with new applications appearing Format updates at a much higher rate than the device replacement rate Uncertain and diversified markets – Late / changing product specs, short product life cycles – Different customers / tiers have different requirements Move from implementations in hardware to software to cope with the variation and changes

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Exponential growth of SW in consumer products 100 MB 10x software increase every 6-7 years

10 MB Code size

1 MB

TV

100 KB 10 KB 1 KB 1970 No SW

← Moore’s law for memory (10x every 5 years)

1975

1980 1 KB

1985

1990

1995

64 KB

2000

2 MB

2005 30 MB

Source: Philips Consumer Electronics 8

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Consumer electronics Characteristics Cost pressure (< $100 for electronics of large TV) Low power consumption (no fan / mobile) Large series (> 0.5 million pieces) Robustness (no hazards, no reboots) Both control and signal processing Real-time constraints (no loss of data, guaranteed response) Increasing requirements for computation & communication (more functions, higher resolutions)

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Consumer domain demands SoC solutions Highly integrated Systems-on-Chip to satisfy constraints on – – – –

Cost Power consumption Form factor Ease of system integration

Enabled by large volumes – To amortize high NRE of SoC development – Need to target sufficiently large market

Optimized implementations with scarce resources – Memory, bandwidth, compute cycles

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Hybrid TV system DDR 64 MB

Channel Decoder

Hybrid Tuner

FLASH 32 MB

DDR 128 MB

NXP

NXP

PNX5100 HD MJC, 1080p@120Hz ColourWave Full up conversion Motion Blur

PNX8541

Up to 1080p @120hz Max. 1080p@60hz

DVI/HDMI

DVI/HDMI

DIGITAL AUDIO IN

DIGITAL AUDIO OUT

Audio AMP

PNX5100

Complete one chip TV:

Add on Picture Quality booster

•Cost sensitive midrange market

•Halo reduced HD Natural Motion

•Connectivity,OSD

•LCD Motion Blur Reduction

•Hybrid source decode

•Display color and Contrast enhancements

•De-interlacing •Audio/Video processing •Some video featuring

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Log Scale

Key industry trends – More Challenges ! Moore’s Law

Design Productivity

Cost of system design &integration is getting out of hand

Software Productivity 0.35µ0.25µ0.18µ0.15µ0.12µ0.1µ Imaging & Video Subs ys tem 2 x Mic B ia s S tereo ADC S tereo DAC S tereo DAC S tereo HF Amp.

(CoreS ig ht) TP IU

HDP

E TB

Dig . F ilter Dig . F ilter LML Dig . F ilter MTU

4k+4k TCM

ARM1176 351MHz

Increasing complexity

– At application, system, HW, and SW level – More (sub-)systems on one SoC – Single company cannot excel in all domains

Loosing grip on product quality – Exploding costs for verification – Degrading reliability and predictability

HP M VF P

E TM

I

RW M

M

M

S

P

M

2xL1 16+16kB

M

M

2 x CS I-2 2 x CCP 2 pa ra llel

IP 2032 S DRAM controlle r

2x R D16025C2 Telecom DS P 208MHz

TmVideo TM3270 350MHz

M M Wa sa bi L2 system ca che (64-bit, 351 MHz, 512 kbyte S RAM) S

M

2xL1 32+32kB

2xL1 8 +8kB

M

AXI2VP B

Keyboa rd GP ADC

ADC

Touchscreen

DAC

Da cctrl

Mis c reg s GP IO E XTINT RTC

E VP E mbedde d V ector P rocess or VD32040, 208MHz

Peripheral Subs ys tem

M P eriphera l mAXI (32-bit, 117 MHz )

AXI2VP B

ADC

P LL CGU

DP I-2 24-bit

Debug US B P rototype DMAC E J TAG OTG E xte nsion M M M3 M M Concentra tor (117MHz)

Video Conc. (117MHz)

L1 64+128kB

M

128kB Boot R OM

DBI-2 9-bit

Displa y Renoir

TV-out

M

Cellular/GPS Modem

Ra m-ba s ed Displa y E ng ine VDE

Video Renoir

Interrupt ctrl

S

AR M1156 Modem Contr. 234MHz

DS I seria l

RAM-le ss Color LCD controller P L110

2xTV DAC Mux Video & Ima g e proces sor

H.264 Accelera tor

LML

2x R D16025C1 Audio DS P 175MHz

MB X HR + VGP

D

S

2xTS R

2x IIS in 2xIIS out IOM2 2x timer

32+32 kB L1 ca che

M

3D Engine

Mux

Multi-core debug & trace TAP DAP

AF E

– Hundreds of man-years for HW/SW system – Diversity of products

WDRU

Osc

Memstick

AXI2MMIO

Ma g ic Ga te

M AXI2AHB

MC-E B I S MC

Irda -F IR

CAE

NDF -E CC

3x timer

4x I2C

Interrupt ctrl

2xS Dca rd

I2S

IP C F RU

5x UART

P WM

5x S P I

P CM/IOM2

S CON

J og Dia l

OTP DMA P L080 interfa ce

DCA? AMU? ARB

Sys tem Power Mgt (P owerWise) S P MU IE C

HP M AP C

SW Verification

More (programmable) cores in single SoC – Multi-core programming environments & debug

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Design Solutions NXP requires a design process that is Predictable in time and performance Efficient and high quality

The key elements of such a design process are Raising the level of abstraction – System Level Design, System Integration and Verification

High level of re-use – IP reuse (HW, SW) – Verification reuse – Architecture reuse (HW,SW, appl.tasks)

Nexperia platforms

Integrated design environments – Automation of design flow

Builder tools

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Outline NXP Products / challenges Abstraction Levels Functional Modeling Architecture Modeling Summary

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Design abstraction levels Specification capture T1

T2

T3

Function

T4

High level executable spec

SW

CPU

HW

SW CPU

SW (low level)

HW model (TLM)

mem

HW

mem

Functional verification

HW/SW partitioning Architecture selection

Synthesize Synthesize&

Compile

&Optimize Optimize

& Optimize

HW (RTL)

SW (code)

HW design

SW design

Architecture (TLM)

Implement’n (RTL)

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Design abstraction levels – System-AMS Specification

Functional Architectural Implementation

RF A(MS)

Digital System Interface

missing interactions

Verilog-A(MS)

D

C/C++ Simulink

SystemC

VHDL

SystemC-AMS

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Outline NXP Products / challenges Abstraction Levels Functional Modeling Architecture Modeling Summary

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DATE 2008 Tutorial A - Wido Kruijtzer / Victor Reyes

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NXP SoC Example (simplified view)

Linux

AC3

H264

MP3

MPEG-4

Audio subsystem

Image & Video subsystem

WLAN UMTS

Application subsystem

Radio subsystem

On-chip interconnect Shared off-chip memory subsystem

Connectivity subsystem

Bluetooth USB

A SoC is composed of coarse-grain SubSystems 20

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SoC Level Functional Model Why do we need a functional model? Functional verification of algorithm Single model for HW and SW parts. Explore algorithmic tradeoffs Estimate resource requirements – Computational load, Communication load

Audio

Image & Video

Radio

Connectivity

AC3 MP3

H264 MPEG-4

WLAN UMTS

Bluetooth USB

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SoC Level Functional Model (toplevel) Audio Radio WLAN

Control

~ 10 - 15K Loc

AC3

demux LCD

MPEG-4

PHY: ~ 10-15K Loc

~ 5K Loc

Image & Video

~ 15 - 30K Loc

Difficult to create an executable SoC level functional model Each sub-function contains hundreds of sub-blocks – Functional decomposition, Interfaces

Characteristic per functional sub-system differ – Different semantics needed • Dataflow, Process networks, Discrete Event, State Machines

– Different algorithmic tradeoffs 22

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SoC Level Functional Model – Use Cases Many (complex) application use cases to handle Radio

Control

WLAN

demux

Audio AC3 Audio Image & Video MPEG-4

Connectivity

AC3 Audio

Control demux

USB

Image & Video H264

Radio UMTS

Control demux

LCD

MP3 Audio

LCD

Bluetooth

Connectivity Image & Video

And many more ……

H264

LCD

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SoC functional model - Hurdles Different Models of Computation (semantics) Single functional model too complex to handle by single designer Limited tool support Many application use case to cover – “All in one” functional model not preferred

IP Re-use, platform based design Many design teams involved – Multi site, Multi culture

Solution : Divide & Conquer approach

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Functional Modeling at IP / Sub-System Level Audio

Image & Video

Radio

Connectivity

AC3

H264

WLAN

Bluetooth

MP3

MPEG-4

UMTS

USB

Benefits of multiple functional models: Complexity can be handled more easily Optimized tools available for implementations Specific implementation technology – Domain specific, single semantics

Specialized domain know-how (e.g. competence centre) Different life-cycles

re-use 25

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Functional Model Refinement Functional refinement directly to implementation level

Refinement

Audio

Image & Video

Radio

Connectivity

AC3

H264

WLAN

Bluetooth

MP3

MPEG-4

UMTS

USB

(RTL, C)

On-chip interconnect

off-chip Mem. ctrl

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Functional Refinement Code-generation & Co-simulation Image & Video

Radio

WLAN

H264

WLAN

UMTS

MPEG-4

UMTS

Radio

HDL code

Tesbench Code generation

Co-simulation Verification

C-code, HDL

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Functional Modeling – Multimedia Domain An interface centric design approach

T3

– Communicating tasks based on KPN

T1

– Optimal SW and HW interface types

HW

Task

TTL Task Transaction Level interface:

Task

– Parallel application models • Executable specifications

Task

TTL

– Platform interface • Integration of HW and SW tasks

– Structured design & programming

T4

SW

Aim: Close gap between specification and implementation

Mapping technology

T2

T TTL

Mapping A

S

K

S

Platform Infrastructure [CODES04]

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March 10,2008

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Example TTL based designs Smart Imaging Core TTL API

HLA MLA

Motion Segmentation

LLAs Smart Imaging Coprocessor

SW Shell ARM 9xx CPU

TTL SW Shell TTL interface

Motion Estimator Coprocessor

VLIW

HW Shell Interconnect

HW Shell TTL

Embedded Memory

Video Input

Memory Ctrl

Peripherals

Ext. SDRAM

[CODES05] , [DAES06] 29

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Functional modeling - Simulink Bluetooth - EDR Started with Simulink built-in models. Developed a complete TX chain, including analog/RF blocks. – Simulated the transfer function of the modulator and verified it against the Bluetooth standard specification

Converted the design into fixed-point format . – Verified the functionality of the fixed-point design against the Bluetooth standard.

Generated (manually) a bit-compatible RTL description of the Simulink fixed-point model. Evaluated the modulator on an FPGA platform. Next step: HDL generation directly from Simulink 30

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Functional modeling - ADS/Ptolemy Wireless LAN radio system

Functional model used as testbench for circuit design

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What’s next after functional modeling? Functional to implementation problems SoC integration happens at RTL / C level – Complex and error prone – Iterations are not possible (first implementation/configuration that work instead of best/optimized one)

Main usage of the Implementation level is for pre-silicon verification – But complete system is hard to simulate/verified all together

SoC integration at the implementation level introduces a big gap – Complex and error prone – Iterations are not possible (first implementation that work instead of best one)

An intermediate step before implementation is required Architecture level – Main usage is SoC integration, analysis and debug 32

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Outline NXP Products / challenges Abstraction Levels Functional Modeling Architecture Modeling Research challenges Conclusions

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Architectural Level – Key concepts Abstraction

TLM

– Increasing block granularity •

Gates (80’s), HDL (90’s), IP blocks (2000), SubSystems (2010)

– From RTL to TLM (Transaction Level Modeling) •

but TLM covers only HW architecture, all system aspects need to be modeled together (i.e. architecture, application, constraints, etc)

RTL Gate level

Separation of concerns – Computation / Communication / Cost – Behavior / interfaces

Refinement – Synthesis and transformation techniques

Standards – OSCI (SystemC and TLM standards) – SPIRIT (IP-XACT)

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Architectural model => Virtual prototype Available early in dev. cycle

Enables early HW/SW co-design & co-verif.

HW/SW architecture & Impl. problems identified early

IC design

Specification

Virtual Platform

Fab

Short system bring-up time

Demo Board

System Validated

System Pre Validated

HW dependent SW

System Integration

Technology Implementation:

Observability / Controlability / Debuggability

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But more than one architectural model is required Functional partitioning and relative performance exploration

SW development and optimization

System-level functional verification

HW development and optimization

Interconnect and memory hierarchy dimensioning

System-level performance verification

timeline SoC level Specification

IP / Subsystem level Implementation

SoC level (pre-silicon) Verification

Use-case driven approach Different activities per design phase – Specification: exploration and dimensioning (SoC level) – Implementation: SW and HW development and optimization (IP and SubSystem level) – Verification: functional and non-functional verification of both HW and SW together

Activities have different requirements 36

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Different use-cases, different requirements Use-case

Description

Functional partitioning and relative performance estimation

Enable extensive architectural exploration (what-if scenarios)

Interconnect and memory hierarchy dimensioning Application SW development and optimization

Middleware HW dependent

Focus on: task mapping, task scheduling, memory allocation, resource allocation, etc HW architecture dimensioning Focus on: bandwidth, latency, buffering, arbitration policies, etc End-user SW applications (platform services based) Multicore debugging Complex algorithms and codecs (H264, MP3, UMTS, AES etc) SW platform services Low-level drivers, HW abstraction layers (HAL) Must be very optimized

HW development and optimization

VP as a system-level test-bench for the HW IP

System-level functional verification

HW/SW integration and verification (complete SW stack)

System-level performance verification

Very accurate performance and power estimations

High Level Synthesis / RTL co-simulation (transactors)

Extensive verification of scenarios

Representative (worst-case) scenarios

RTL speed up x104

x102

Behavior accuracy

Timing accuracy

Mixed abstract performance and functional models

x102

Absolute ±10%

Fully functional models

Absolute ±1% Absolute ±10%

x103 x103 x102

Absolute ±10% Absolute ±20%

x104 x103

Relative (fidelity)

Absolute ±10%

Fully functional models

Absolute ±1%

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Different requirements, different models? In an ideal world one model fits all – Ultra fast models + 100% cycle accurate + push-button availability

Unfortunately today we still need the right model for the right use-case… but one model per use-case is an overkill – Huge effort to create and maintain every model – How to assure consistency between models?

Accuracy Speed

Model reuse and refinement is a must… but modeling is a multidimensional problem – High speed models contains very little time information – Very accurate models are typically slow and are difficult to create – No clear refinement paths from one model to another

Effort

And different types of models have different particularities – – – –

Processing units (CPU, DSP, etc) Interconnects (busses, bridges, routers, etc) Memory subsystem (L1-L2 cache, memory controllers, memories, etc) Peripherals (IO blocks and slave HW accelerators)

Getting to the right model is the critical task 38

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Modeling concepts Minimizing the modeling effort – Library of predefined building blocks to compose IP models – Well defined methodologies and guidelines – Standard set of IP interfaces to assemble IP models (avoid adaptors)

Modeling for speed – Minimize the number of simulation events / context switches – Coarse grain computation and communication – Binary translation techniques for processors / host-code emulation techniques

Modeling timing – Accurate timed models are very hard to create – Approximated timed models are easier (but when it is good enough? ) – Define accuracy windows, where the window size depends on the use-case

Refinement – Interfaces/Communication refinement – Behavior/Computation refinement – Cost (timing) refinement

Being tackle by OSCI TLM 2.0 standard proposal Still ad-hoc, proprietary solutions

[TLM] 39

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Abstraction Levels with SystemC Functional level

Architectural level

send() recv()

F1

F2

F3

F1 F2

F3 F4

CPU

HW coproc

Memory

Message level communication

F4

write(address) read(address)

Interconnect

Implementation level

HW coproc

CPU Memory

Transaction level communication

Signal level communication

Interconnect

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OSCI TLM 2.0 modeling styles T1 T2

UT T2

T1

LT request1

request2

AT

response1

response2

address2

address1

data2

data1

CA

status1

0

1

2

3

status2

4

5

6

7

8

time

(T) transaction (function call) 41

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How many models do we need? Use-case

Processor units

Functional partitioning and relative performance estimation

High-level tasks

Interconnect and memory hierarchy dimensioning

Traffic generators

SW development and optimization

Mapping technology

Interconnects

Memory subsystems

Peripherals

Functional models (AT), protocol independent

High-level tasks

Functional models (CA), protocol specific

Data sinks

Application

Fully functional models at the UT, LT level (Proc. IA ISS)

Middleware

Fully functional models at the LT, AT level (Proc. IA ISS)

HW dependent

Fully functional models at the CA level (Proc. CA ISS)

System-level functional verification

Fully functional models at the LT level (Proc. IA ISS)

System-level performance verification

Fully functional models at the CA level (Proc. CA ISS)

Buy, outsource

Mapping technology

In-house creation 42

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Creating efficiently functional IP models 2 functional models LT and CA, but… Time information on LT models can still range quite a bit – Optimizations to improve speed – Refinement towards AT

IP modeling libraries and methodology + Standard modeling libraries (SystemC, TLM, SCV)

CA models are not yet TLM but cycle-callable signal-level LT model

Automatic generation

Communication and computation refinement

IP spec

IP functionality design tools

IP structure design tools

AT model synthesis tools CA model

Automatic generation

RTL extraction tools

RTL HDL VHDL, Verilog

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IP modeling libraries and methodology Objectives: Reduce the modeling effort and learning curve for new model developers – Quickly create the most common parts of the IP model using building blocks

Enable model reuse and refinement – Add details gradually (both communication and computation) – Separation of concerns applied to modeling GMFL

IF adaptors monitors

Improve configurability of models SCML – Change model internals during construction/elaboration time

Align with industry standards – OSCI TLM 2.0 & IP-XACT 1.4

TLM 2.0

SCV

IEEE 1666 SystemC

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CoWare SCML Methodology for model re-use – Use-case determine for bus model – Re-use peripheral model for multiple use-cases

Separation of behavior, communication and timing Focus on communication refinement – generic interfaces + specific adaptors

Simple modeling pattern supported by a library of predefined blocks – SystemC Modeling Library (SCML) http://www.coware.com/solutions/tlm.php

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NXP GMFL Generic Modeling Features Library Library of predefined blocks built on top of SCML Extend and complement SCML capabilities – More methodology and guidelines

IP core child sc_module

t

parent sc_module

child sc_module

fA t

fC

Focus on behavior modeling and refinement – Explicit synchronization, data and control flow

child sc_module

fB t

Key concepts are: Hierarchical modeling – Structured, reusable code – Closer to HW designers

Sync. & storage channels

Generic core interfaces

Behavior blocks

Specialized ports

Time annotations

f

User defined functionality

Dynamic layout – Add/remove functionality during elaboration – Block refinement

Rd frame Process Wr frame

Loop { Rd pixel Process Wr pixel }

T frame

T pixel

Design and code-generation tool

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NXP GMFL design and code-generation tool Functional design tool (3rd party)

IP structure design tool

import SystemC code-generation

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Abstract (dynamic) performance simulations App. use-case Control run-time reconfiguration App. use-case App. App.use-case use-case Model Model model(s)

Requirements, constraints

mapping Stimuli generation

CMU

Performance Characterization

SoC model SystemC AT SystemC CA RTL

monitoring Tracing & visualization (analysis views)

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Application use-case modeling and mapping Executable application use-case model (simple semantics) – Synchronization & data communication – Dynamic data dependencies – Constraints (throughput, latency, etc)

F1 F3

F2

F4

Smart Traffic Generators (STG) – Direct mapping from app. use-case models – High level semantics adopted to bus protocol traffic – Possibility to simulate •

function/data dependencies

•

Synchronization between STG

•

Scheduling / interrupts / preemption

– Generic interface + specific adaptors

STG

STG

CMU

Scheduler

Traffic initiator

Scheduler

TLM 2.0

TLM 2.0

Bus adaptor

Configuration Manager Unit (CMU) – Multiple use-cases can be mapped on a STG – CMU on charge of use-case switching

Traffic initiator

Bus adaptor

SoC infrastructure model SystemC AT SystemC CA RTL

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Outline NXP Products / challenges Abstraction Levels Functional Modeling Architecture Modeling Summary

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Summary SoC design challenges require moving up in the abstraction level and exploit reuse at all levels Abstraction levels – Multiple domains (digital, analogue, RF) – Multiple languages (UML, C++, Simulink, SystemC, VHDL, Verilog-AMS, etc)

Functional modeling

divide & conquer

– Domain specific functions, different semantics, different algorithmic trade-offs – Multiple functional use-cases – Most tools provide a path to implementation

An integration level above implementation is required

Architectural Level

– Architecture model => Virtual prototype – Different architectural use-cases with different requirements => the right model for the right use-case – Getting to the models is still the critical task => how to tackle this •

IP Modeling methodologies and libraries

•

Automatic generation from different tools

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DATE 2008 Tutorial A - Wido Kruijtzer / Victor Reyes

March 10,2008

References [DAC2000] E.A. de Kock, G. Essink, W.J.M. Smits, P. van der Wolf, J-Y. Brunel, W.M. Kruijtzer, P. Lieverse, K.A. Vissers; “YAPI: Application Modeling for Signal Processing Systems “ in Proceedings of the 37th Design Automation Conference, Los Angeles, 2000 [CODES04] Pieter van der Wolf, Erwin de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink, “Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach”, Int. Conf. on Hardware/Software co-design and System synthesis, September 2004 [CODES05] Wido Kruijtzer, Winfried Gehrke, Victor Reyes, Ghiath Alkadi, Thomas Hinz, Jörn Jachalsky, Bruno Steux; “The Design of a Smart Imaging Core for Automotive and Consumer Applications: A Case Study” in Int. Conf. on Hardware/Software co-design and System synthesis, September 2005 [DAES06] Wido Kruijtzer, Victor Reyes, Winfried Gehrke; “Design, Synthesis and Verification of a Smart Imaging Core using SystemC” in Design Automation for Embedded Systems, An International Journal from Springer, Volume 10, Numbers 2-3, September 2006, pp. 127-155(29). Special Issue on SystemC-based System Modeling, Verification and Synthesis. DAC07: Slider [DAC2007] Walter Tibboel, Victor Reyes, Martin Klompstra, Dennis Alders ; “System-Level Design Flow Based on a Functional Reference for HW and SW” in Proceedings of the 44th Design Automation Conference, San Diego, 2007 [SCML] http://www.coware.com/solutions/scml_kit.php [TLM] http://www.systemc.org/downloads/standards/ [ESL book] Brian Bailey, Grant Martin, Andrew Piziali, “ESL Design and Verification: A Prescription for Electronic System Level Methodology” The Morgan Kaufmann Series in Systems on Silicon

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DATE 2008 Tutorial A - Wido Kruijtzer / Victor Reyes

March 10,2008

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