MIPS64 •

Registers – – – –

•

Data types – – – –

•

32 64-bit GPRs (int registers) 32 64-bit fp registers (dual use) R0=0 Additional special purpose registers 8-bit byte 2 bytes = half word 4 bytes = word 8 bytes = dword

Addressing modes – Immediate and displacement •

register indirect and absolute are easily represented

– Byte addressable 64-bit address •

Big or littleendian

– Load/store architecture

I-type instructions •

I-Type instruction: 6 bits

5 bits

Op code

•

rs

5 bits rt

16 bits immediate

Encodes: Loads and stores of bytes, half words, words, dwords – All immediate (rt ç rs op immediate) – Ex: Add base register rs to 16 bit offset

R-type instructions • R-Type instruction: 6 bits Op code

5 bits rs

Source registers

5 bits

5 bits

11 bits

rt

rd

func

Destination register

Op code variant

• Register-Register ALU operations: rd ç rs func rt – Function encodes data path operation: add, sub, slt, and, or – Read/write special registers and moves

1

J-type instructions • J-Type instruction: 6 bits

26 bits

Op code

immediate

• Encodes: – Jump and jump & link – Trap and return from exception

In summary… • Pitfalls – Designing “high-level” language instructions – Not considering compiler design when targeting code size

• Fallacies – There are “typical” programs – An architecture with flaws cannot be successful – You can design a flawless architecture

ALU components Data Path and Control Review

op Carry_in a b

Kirk W. Cameron, Ph.D. Assistant Professor Department of Computer Science and Engineering University of South Carolina

0 1

a b

+

sum

3/2 adder

1-bit logical unit for AND and OR Carry_out

2

1-bit Simplified ALU w/ subtraction

1-bit Simplified ALU Carry_in

Binvert

op

a b

Carry_in

a b

0 1

op

0 1

result

result

2

2

0

+

+

1 Carry_out

Carry_out

a + b + 1 = a + (b + 1) = a + ( −b) = a − b

32 bit ALU (ripple carry)

Edge-triggered Design

Carry_in Binvert

a0 b0

op

ALU0

ALU1

Clocks: necessary to update logic that holds state

• • • •

Frequency = inverse of cycle time Clock period = high clock followed by a low clock Edge-triggered clocking: all state changes occur on clock edge Active clock edge = edge of clock that causes state to change

– Free running signal with a fixed cycle time (clock period) result0

Carry_out

a1 b1

•

result1

Carry_out

Rising edge a32 b32

ALU32

Falling edge

Clock period

result32

Carry_out

Why use edge-triggering? State of input element

Setup time

Combinational Logic

State of output element

Hold time High Low High Low Clock period

*input values must be stable when active clock edge returns

3

6 bit register using D flip flops

Register Files • Set of registers that can be read and written by supplying a register number to be accessed – One set of registers operated on by a port

• Multiple-read ports: not too difficult • Multiple- write ports: problems arise

Read ports

Write Ports Read port 1

Write (clock)

Read port 1

Write register Register0 Register1 : : : Register n-1

Register0 Register1 : : : Register n-1

M U

M U

Register 0

X

Read port 2

D e c o d e r

M

Readdata1

Register0 C D Register1 C D : : : Register n-1 C D

Readdata1

Readdata2

U X

X : :

Register 1

: : Register n-1

Single Read Port Multi Read Port

Write data

Data Path for I-type instruction

Register Files • Example: 2 read ports, 1 write port, high-level view

6 bits Op code

• •

5 bits rs

5 bits

16 bits

rt

immediate

Assuming 32, 64-bit registers (R0..R31) Use same register file as R-type ALUop

Read Port 1 Read Port 2

rs

Readdata2

rt

Write

ReadReg1 ReadReg2 WriteReg

Readdata1 REGISTERS Readdata2

immediate

Write Data

ALU

Write Register Write Data

memwrite

Readdata1

zero

result

Data Memory address

Write Write data

Why not multiple writes? What if read and write at same time? Who goes first? Sign extend

memread

4

Data Path for R-type instruction 6 bits Op code

rs

5 bits

5 bits

11 bits

rt

rd

func

Assuming 32, 64-bit registers (R0..R31) Using 2 read ports and 1 write port – Inputs: 3 register #s (each 5 bits wide), data for write (64-bits) – Outputs: readdata1 and readdata2 (both 64 bits) ALUop

rs rt rd

ReadReg1 ReadReg2 WriteReg

Readdata1 REGISTERS Readdata2

Write Data

ALU

• •

5 bits

zero result

Write

5