Midterm Exam Statistics

Midterm Exam Statistics Number of Occurrence 6 Mean=16 Standard Deviation: 2 5 4 3 2 1 0 10 15 EECS 247- Lecture 18 16 17 Nyquist Rate ADCs-S...
Midterm Exam Statistics Number of Occurrence

6

Mean=16 Standard Deviation: 2

5 4 3 2 1 0

10

15

EECS 247- Lecture 18

16

17

17.5

18

EE247 Lecture 18 • ADC Converters – Sampling (continued) • Sampling switch considerations – Switch induced distortion • Sampling switch conductance dependence on input voltage • Clock voltage boosters

– Sampling switch charge injection & clock feedthrough • Complementary switch • Use of dummy device • Bottom-plate switching – Track & hold circuits – T/H circuit incorporating gain & offset cancellation EECS 247- Lecture 18

Summary of Last Lecture • DAC Converters (continued) • Dynamic element matching – DAC reconstruction filter

• ADC Converters – Sampling (continued) • Sampling switch considerations – Thermal noise due to switch resistance – Sampling switch bandwidth limitations – Switch induced distortion • Sampling switch conductance dependence on input voltage EECS 247- Lecture 18

Practical Sampling Summary So Far! • kT/C noise

C ≥ 12k BT

φ1

22 B VFS 2

vIN

vOUT M1

• Finite Rsw Æ limited bandwidth 0.72 R device speed Æ During the period (t- to toff) current in channel discharges channel charge acquired during the previous ½ clock cycle into low impedance signal source

• Only source of error Æ Clock feedthrough from Cov to Cs EECS 247- Lecture 18

Switch Clock Feedthrough Slow Clock VG

VH

Cov D

VO Cs

ΔV = −

Cov Cov + Cs

(Vi +Vth −VL )

wh e re ε = −

Vi +Vth

Vi VL

t

VO

ΔV

Vi

Co v

(Vi +Vth −VL ) Cs Vo = Vi + Δ V ⎛ C ⎞ C C Vo = Vi − o v (Vi + Vth −VL ) = Vi ⎜ 1 − o v ⎟ − o v (Vth −VL ) ⎜ Cs Cs ⎟⎠ Cs ⎝ Vo = Vi (1 + ε ) + Vos ≈−

VG

Cov Cs

; Vo s = −

EECS 247- Lecture 18

Cov Cs

t- toff

t

(Vth −VL )

Switch Charge Injection & Clock Feedthrough Slow Clock- Example VG

VH

VO

M1

Vi

VG

10μ/0.18μ

Cs=1pF

VL

C' ov = 0.1 fF / μ Cox = 9 fF / μ 2 Vth = 0.4V

Vi +Vth

Vi

VL = 0

ΔV

Vi

10 μ x0.1 fF / μ =− = − .1% Cs 1pF Allowing ε = 1/ 2LSB → ADC r e solution > RS1A minimizes the non-linear component of R = RS1A+ RS1

– Typically, S1A is a wide (much lower resistance than S1) & constant VGS switch – In practice size of S1A is limited by the (nonlinear) S/D capacitance that also adds distortion – If S1A’s resistance is negligible Æ delay depends only on S1 resistance – S1 resistance is independent of VIN Æ error due to finite time-constant Æ independent of VIN

EECS 247- Lecture 18

Differential Flip-Around T/H

S11

S12

Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuit During input sampling phaseÆ amp outputs shorted together Ref:

W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931

EECS 247- Lecture 18

Differential Flip-Around T/H

φ1’ φ1 φ2 • Gain=1 • Feedback factor=1 EECS 247- Lecture 18

Differential Flip-Around T/H Issues: Input Common-Mode Range

• ΔVin-cm=Vout_com-Vsig_com Æ Amplifier needs to have large input common-mode compliance

EECS 247- Lecture 18

Differential Flip-Around T/H Issues: Input Common-Mode Range

• ΔVin-cm=Vout_com-Vsig_com Æ Amplifier needs to have large input common-mode compliance

EECS 247- Lecture 18

Input Common-Mode Cancellation

• Note: Shorting switch M3 added Ref: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008 EECS 247- Lecture 18

Input Common-Mode Cancellation

Track mode (φ high) VC1=VI1 , VC2=VI2 Vo1=Vo2=0

Hold mode (φ low) Vo1+Vo2 =0 Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))

Æ Input common-mode level removed EECS 247- Lecture 18

T/H + Charge Redistribution Amplifier

Track mode: (S1, S3 Æon S2Æ off)

VC1=Vos –VIN , VC2=0 Vo=Vos EECS 247- Lecture 18