MERGER board (CREAM experiment) J. Bouvier
To cite this version: J. Bouvier. MERGER board (CREAM experiment). 2007, 74 p.
HAL Id: in2p3-00146224 http://hal.in2p3.fr/in2p3-00146224 Submitted on 14 May 2007
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Internal report LPSC 07-48 Version 8 May 2007
MERGER board ( CREAM experiment ) Serializer board of the data PMT matrix for the CHERCAM detector
Joël BOUVIER Data Acquisition Team
MERGER Board, Version 8 ,May 2007 1. Overview The purpose of this board is to interface the DAQ_FEE boards, board located behind the PMT, which assumes the conversion of the analog value issue by the PMT, and the SPARSIFICATION board, which assumes the interface with the CREAM balloon. Its main tasks are: Manage the power voltage for the DAQ_FEE boards Transfer the command from the SRPARSIFICATION board to the DAQ_FEE boards Manage the data transfer from the DAQ_FEE boards to the MERGER board ( serial acquisition data ) Serial to parallel conversion for the data to the SPARSIFICATION board 2. Block Diagram 2.1. Logical parts block diagram A block diagram concerning the logical parts of the design are shown in Annex 1 : Logical parts block diagram with 21 bits SERDES page 22 2.2. Power parts block diagram A block diagram concerning the power parts of the design are shown in Annex 2 : Power parts block diagram page 23 3. Data acquisition command description The following description is available for the command bus from the SPARSIFICATION board and to the DAQ_FEE boards. For most command the MERGER board behaves like a command repeater to the DAQ_FEE board. The command is sent via a serial link and validated by an enable signal ( low level active ). The number of signals necessary for this function is equal to 3 : A clock signal ( CK40 ) Data signal ( DATA ) A Strobe signal ( /ENABLE ) Two command types are defined: Command with argument Command without argument For safety reason no commands are defined with a code equal to 0xFF ( hexadecimal representation ) because if, for any reasons, the data line becomes unconnected the data view by the receptor is a continuous high level logic. The Data and Strobe signals are generated on the rising edge of the Clock signal and the most significant bit of the coded commands is always sent first. 3.1. Command with argument This command type is used for initializing a value into the DAQ_FEE board or into the MERGER board. All the command of this type is issue by the SPARSIFICATION board. The command is coded on 16 bits word and a timing diagram relative to this function is showing on the Figure 1 : command with argument. Page 1/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 the most significant bit is sent first. Its structure is : The first 8 bits is for the command definition The others for the data value. CK40 /ENABLE DATA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
x
Figure 1 : command with argument From SPARSIFICATION CLK ENIN_N DIN To row CLK_ROW_BRD(0) EN_N_ROW_BRD(0) DOUT_ROW_BRD(0)
For more information about the command with argument refer to the SPARSIFICATION box documentation. The declared command is :
Initialization of the DAQ_FEE internal delay : This command type is for initialize the delay between the TRIGGER command and the start of the analog conversion. There is one delay value per DAQ_FEE board. The command is defined like below : Bit(15..12) represents the column number. The numbers available are 0 to 4 and 8 to C ( hexadecimal value ). Bit(11..8) represents the row number. The numbers available are 0 to 4 and 8 to C (hexadecimal value ). Bit(7..0) represents the data value ( for more information about the description of this value refer to the DAQ_FEE documentation )
Initialization of the MERGER internal register : This command type is for initialize the MERGER internal register. This one are also sent to the DAQ_FEE which not interpreted them. By default, at the power up or after a RESET state all the MERGER internal register have a zero value. The command is defined like below : Bit(15..12) D ( hexadecimal value ). This value represents a command to the MERGER internal register. Bit(11..8) represents the address register which is to be initialized. ( 16 possible value ) Bit(7..0) represents the data which be writing into the internal register.
Page 2/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 The declared registers are : Address
Name
Designation This register represents the LED intensity value used for the test of the matrix. The low significant bit is equal to xx mV.
0
LED_VALUE_LSB
The assignment register is like the following description : D[15..14] : don’t care D[13..12] :
00 01 10
Normal operation 1 K to Gnd 100 K to gnd
11
Three state
the last 3 values are Power 1
LED_VALUE_MSB
down modes D[11..0] : Data to convert By default this 16 bit register is set to 0. For more information’s see the AD5328 datasheet component. This command indicates to the MERGER board that is entering in a test mode. For the following Acquisition Trigger command ( x50 ) receiving from the
2
LED_ON
SPARSIFICATION board it must generate this sequence of action : generated a LED pulse command transmit the Acquisition Trigger command to the DAQ_FEE boards
3
LED_OFF
This command indicates to the MERGER board that is entering in a standard mode. For the following Acquisition Trigger command ( x50 ) receiving from the SPARSIFICATION board it must generate this sequence of action : transmit the Acquisition Trigger command to the DAQ_FEE boards
The Annex 4 shown show the functionality of functions LED_ON and LED_OFF. If an function need more than one register ( ex. 16 bit register ) the global value is transferred to the function when the More Significant Byte ( MSB ) is received. 3.2. Command without argument This command type is used for driving the DAQ_FEE board or the MERGER board. Most of the commands are issue by the SPARSIFICATION board however the MERGER board can also send some commands to the DAQ_FEE board. Page 3/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
The command is coded on 8 bits word and a timing diagram relative to this function is showing on the Figure 2.
CK40 /ENABLE 7
DATA
6
5
4
3
2
1
0
x
Figure 2 : command without argument From SPARSIFICATION CLK ENIN_N DIN To row CLK_ROW_BRD(0) EN_N_ROW_BRD(0) DOUT_ROW_BRD(0)
The declared command is:
1
1
Acquisition Trigger : 0x50 This command is used when a trigger is generated by the master trigger; this command comes from the SPARSIFICATION board.
Calibration gain 1 : 0x51 This command is used to indicate to the DAQ_FEE boards that the next Acquisition trigger must be treated like CALIBRATION GAIN 1. This command comes from the SPARSIFICATION board.
Calibration gain 5 : 0x52 This command is used to indicate to the DAQ_FEE boards that the next Acquisition trigger must be treated like CALIBRATION GAIN 5. This command comes from the SPARSIFICATION board.
Normal aquisition : 0x53 This command is used to indicate to the DAQ_FEE boards that the next Acquisition trigger must be treated like NORMAL ACQUISITION. This command comes from the SPARSIFICATION board.
Enable To Transmit Data : 0x54 This command is used to ask at the DAQ_FEE board to send their acquired data’s. This command is sent by the MERGER board to the row one after the others with a delay after it have received a Acquisition Trigger command.
1
1
1
For more information about this command see the SPARSIFICATION board documentation Page 4/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 4. Data acquisition reading 4.1. Read data principle 4.1.1. General read data principle
COLUMN 0
COLUMN 1
COLUMN 2
COLUMN 3
COLUMN 4
COLUMN 5
COLUMN 6
COLUMN 7
COLUMN 8
DAQ_FEE
COLUMN 9
The reading principle is to acquire data’s, for one MERGER board, one half of the matrix data row by row the second half being made by the 2nd MERGER board. The following figure shows the relative position of the MERGER boards and the detector.
MERGER_1 FLEX_9
FROM POWER MODULE
FLEX_8
TO HOUSEKEEPING DAQ
ROW 7
FLEX_7
TO / FROM SPARSIFICATION BOARD
ROW 6
FLEX_6
ROW 5
FLEX_5
ROW 4
FLEX_4
FROM POWER MODULE
ROW 3
FLEX_3
TO HOUSEKEEPING DAQ
ROW 2
FLEX_2
TO / FROM SPARSIFICATION BOARD
ROW 1
FLEX_1
ROW 0
FLEX_0
ROW 9 Data connector ROW 8 Flex of liaison
MERGER_0
PMT MATRIX BOTTOM VIEW Figure 3 : DAQ matrix implementation The acquisition of the complete matrix needs 2 MERGER boards which work in parallel and independently. The following functional description is for one MERGER board, the second being the same functionally. During the acquisition of a row, the 4 others are in idle mode. This mode is obtained by putting the clock to the DAQ_FEE board in a fixed state. This operation is doing by disabling the clock driver component; previously the DAQ_FEE board has entered in a stable state when it finished the last receiving command ( for more information see the documentation of the DAQ_FFE board and the Data acquisition command description chapter in the present documentation ). So the clock lines on the disabled flexes are in a three state which is seen by the receiver 2 component on the DAQ_FEE board like a high level logic ( for more information see the 2
A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or undriven and parallel terminated ( extract of the MAX9173 documentation, Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe from MAXIM ) Page 5/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 documentation about the LVDS receiver ). 4.1.2. Row read data principle
ROW 9
Group_12 Group_13 Group_14 Group_15
COLUMN 0
COLUMN 1
COLUMN 2
COLUMN 3
MERGER_1
FLEX_9 DAQ_FEE_2 DAQ_FEE_1 DAQ_FEE_0 Value_0 Value_0 Value_0 Value_1 Value_1 Value_1 FLEX_8 Value_2 Value_2 Value_2 . . . . . . . . . FLEX_7 Value_12 Value_12 Value_12 Value_13 Value_13 Value_13 Value_14 Value_14 Value_14 Value_15 Value_15 Value_15 FLEX_6
DAQ_FEE_9 DAQ_FEE_8 DAQ_FEE_7 Data connector Value_0 Value_0 Value_0 Group_0 Value_1 Value_1 Value_1 Group_1 ROW 8 Group_2 Value_2 Value_2 Value_2 . . . Flex of liaison . . . . . . ROW 7 Group_12 Value_12 Value_12 Value_12 Value_13 Value_13 Value_13 Group_13 Value_14 Value_14 Value_14 Group_14 6 Group_15 ROW Value_15 Value_15 Value_15
Group_0 Group_1 Group_2
COLUMN 4
COLUMN 5
COLUMN 6
COLUMN 7
COLUMN 8
DAQ_FEE
COLUMN 9
For a row acquisition, each DAQ_FEE board has 16 values to be transmitted to the SPARSIFICATION board. After receiving an Enable To Transmit Data command, each DAQ_FEE board transmit their data on their dedicated data serial line like the timing determined in the Annex 6 : Row Data Acquisition Sequence without gap between 2 words. The most significant bit of a value is always sent first and the low significant value of a DAQ_FEE board is also always sent first. When all the word ( 10 x 18 bits ) of a specific index ( for example all the Value_0 of the row) are stored in the MERGER board, they are retransmitted, in parallel and in sequence, to the SPARSIFICATION board while the data of the immediately superior index is send from the DAQ_FEE boards. The configuration of the different index is shown in the following figure ( Figure 4 : Group words definition ).
ROW 5
FLEX_5
ROW 4
FLEX_4 DAQ_FEE_2 DAQ_FEE_1 DAQ_FEE_0 Value_0 Value_0 Value_0 Value_1 Value_1 Value_1 FLEX_3 Value_2 Value_2 Value_2 . . . . . . . . . FLEX_2 Value_12 Value_12 Value_12 Value_13 Value_13 Value_13 Value_14 Value_14 Value_14 Value_15 Value_15 Value_15 FLEX_1
DAQ_FEE_9 DAQ_FEE_8 DAQ_FEE_7 Value_0 Value_0 Value_0 Value_1 Value_1 Value_1 ROW 3 Value_2 Value_2 Value_2 . . . . . . . . . ROW 2 Value_12 Value_12 Value_12 Value_13 Value_13 Value_13 Value_14 Value_14 Value_14 ROW 1 Value_15 Value_15 Value_15
ROW 0
FROM POWER MODULE TO HOUSEKEEPING DAQ TO SPARSIFICATION BOARD
FROM POWER MODULE TO HOUSEKEEPING DAQ TO SPARSIFICATION BOARD
FLEX_0
MERGER_0
PMT MATRIX BOTTOM VIEW Figure 4 : Group words definition VALUE_X is defined like the following description :
D[17…D14]
D13
D12
D[11…0]
Position Pmt
Fault
Gain
Pmt ADC values
Page 6/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 4.2. MERGER board acquisition time All the following calculations are done with a basis frequency equal to 40 MHz. 4.2.1. Row time acquisition calculation The row time acquisition, from the DAQ_FEE board, is given by the following formula: Trta = Tcst + Tmct + Tact + Tdfttd + Tfsmf
3
With Trta : Row_time_acquisition : acquisition time for one row Tcst : Clock_synchronisation_time : time where the command is passing through the MERGER FPGA . This value includes the time where the basis clock is valid before the generation of the command. This time is a multiple of the period_basis_clock = 18 x 25 ns = 450 ns Tmct : merger_command_time : command sending time from the MERGER board to the DAQ_FEE boards = number_of_command_bit x number_of_basis_clock x period_basis_clock = 8 x 1 x 25 ns = 200 ns Tact : acknolewdge_command_time : time which permit an command interpretation by the DAQ_FEE board = constant = 100 ns Tdfttd : daq_fee_time_transmit_data : time necessary to transmit all the data through the DAQ_FEE boards to the MERGER board. = ( Acquisition time for one word ) x Number of words = ( 18 x 8 x 25 ns ) x 16 = 3 600 x 16 = 57 600 ns Tfsmf : Finite_State_machine_finished : Time required for finish a row data acquisition ( a necessary time for the Row acquisition Finite State Machine to go in standby state ) = 8 x 25 ns = 200 ns. Trta = 450 ns + 200 ns + 100 ns + 57 600 ns + 200 ns = 58 550 ns = 58,55 µs 4.2.2. Matrix time acquisition calculation The matrix is managed by two MERGER board. Each of them acquire the data of half of the matrix. The two MERGER board working in parallel the entire matrix acquisition time is equal to the half matrix acquisition time made by one MERGER board. The matrix time acquisition is equal to the row time acquisition multiplied by the number of rows managed by one MERGER board. Tmta = Trta * 5 = 58,550 µs * 5 = 292,75 µs
3
Annex 6 : Row Data Acquisition Sequence shows graphically how the calculation is done. Page 7/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 5. Data acquisition transferring After receiving the data from the DAQ_FEE board, the MERGER board must send these one to the SPARSIFICATION board through a high speed data link in a limited time to minimize the acquisition dead time.
COLUMN 0
COLUMN 1
COLUMN 2
COLUMN 3
COLUMN 4
COLUMN 5
COLUMN 6
COLUMN 7
COLUMN 8
COLUMN 9
The MERGER board must also add some information to the received data to identify precisely the data origin ( which DAQ_FEE board have generated which data ); This information are defined as the coordinates of the DAQ_FEE board in the matrix. These coordinates are defined like below :
ROW 9
C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 C: 1100 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 8
C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 C: 1011 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 7
C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 C: 1010 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 6
C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 C: 1001 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 5
C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 C: 1000 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 4
C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 C: 0100 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 3
C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 C: 0011 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 2
C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 C: 0010 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 1
C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 C: 0001 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
ROW 0
C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 C: 0000 R: 1100 R: 1011 R: 1010 R: 1001 R: 1000 R: 0100 R: 0011 R: 0010 R: 0001 R: 0000
MERGER_1
MERGER_0
PMT MATRIX BOTTOM VIEW The value are in binary representation, C represents Column and R represents Row. These information can be add because the MERGER board knows on which rows and on which dedicated line it received each data. To minimize the dead time and the MERGER board resources, the transferring principle is based on the fact that a data is transferred when it was received completely by chart MERGER, the transfer being made while the following data is to be received. The MERGER board, receiving 10 data simultaneously ( one data by line of DAQ_FEE boards ) applies a priority on this one and transmits in first the data of the line 0 then that of line 1 and so on. The physical interface between MERGER and SPARSIFICATION board is made by a couple of integrated circuit : one of them is a parallel to serial transmitter ( located on the MERGER board ) and the other is a serial to parallel receiver ( located on the SPARSIFICATION board ). These circuits are designed for a high speed serial link. These circuits works with a 21 bit parallel bus, more than the one word to be transmit ( 26 bits ). The transmission of data thus requires two transfers in accordance with the signal waveform locates in the Page 8/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 following chapter ( chapter 5.1 Output signal waveform with a 21 bits Channel link page 9). the description of the words and the transmitted bits is made in a chapter which follows ( chapter 5.2 Output word assigning bits with a 21 bits Channel link page 9 ). 5.1. Output signal waveform with a 21 bits Channel link MERGER board 0 GROUP_0 receiving
D
GROUP_1 receiving 0
WORD[18..0]
1
300 ns 150 ns
2
3
150 ns
4
5
6
7
GROUP_2 receiving 8
9
0
1
2
3
4
5
6
7
8
GROUP_0 sending
GROUP_1 sending
GROUP_1 receiving
GROUP_2 receiving
9
0
DAT[19] 50 ns
50 ns
DAT[20] 50 ns
DAT[18..0]
MERGER board 1 GROUP_0 receiving
D
150 ns
0
WORD[18..0]
1
300 ns 150 ns
2
150 ns
3
4
5
6
7
8
9
0
1
2
3
GROUP_0 sending
4
5
6
7
8
9
GROUP_1 sending
DAT[19] 50 ns
50 ns
DAT[20] 50 ns
DAT[18..0]
DATOUT[20] DATOUT[19] DATOUT[18..0]
value[0,0]_MSB
value[0,0]_LSB
value[1,0]_MSB
value[1,0]_LSB
value[2,0]_MSB
value[8,0]_LSB
value[9,0]_MSB
value[9,0]_LSB
5.2. Output word assigning bits with a 21 bits Channel link The MERGER board sends all the data’s in two 21 bits words. The MERGER board sends first WORD0 then WORD1. This 2 words are defined as below : WORD0 Label
/Valid DATA
Low/High
Unused
Fault
Gain Value
Column Number
Row Number
Channel Number
Output
D[20]
D[19]
D[18..14]
D[13]
D[12]
D[11..8]
D[7..4]
D[3..0]
Data
‘Valid DATA’
‘0’
“00000”
‘Fault’
‘Gain Value’
‘Column Number’
‘Row Number’
‘Channel Number’
Number of bits
1
1
5
1
1
4
4
4
Page 9/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
0
MERGER Board, Version 8 ,May 2007 WORD1 Label
/Valid DATA
Low/High
Unused
ADC DATA
Output
D[20]
D[19]
D[18..12]
D[11..0]
Data
‘Valid DATA’
‘1’
Number of bits
1
1
“0000000” “ADC_DATA” 7
12
Common data word signification : D[21] D[20]
Valid_DATA Low/High
bit which indicate when set to 1 that the word is a valid data Indicate when set to : 0 the word is the Most Significant Word of the acquired data 1 the word is the Low Significant Word of the acquired data and the last word of the data
Word 0 Specific bit signification : D[13] D[12]
D[11..8] D[7..4] D[3..0]
Fault
when set to ‘1’ indicate that the associated module wire is malfunctioning. Normally this bit is ‘0’ state. Gain Value indicates which gain is associated to the ADC data value : ‘0’ : gain 5 ‘1’ : gain 1 Column Number Indicates on which column the data has been taken. The defined value are 0 to 4 and 8 to C ( in hexadecimal notation ) Row number Indicates on which row the data has been taken. The defined value are 0 to 4 and 8 to C ( in hexadecimal notation ) Channel Number Indicates the number of sensor in the DAQ_FEE board which the ADC_DATA is associated.
Word 1 Specific bit signification : D[11..0]
ADC DATA
Digital channel value
All the unused bits are send as low level logic. For more information about the bit definition see the DAQ_FEE board documentation. 5.3. MERGER board sending time Here is the calculation of the time necessary for transmitting an acquired data row to the SPARSIFICATION board. To have a constant flow of dated from the DAQ_FEE boards to the SPARSIFICATION board, this time must be lower than the Row time acquisition ( Tdata_group ) calculated above. The sending time, to SPARSIFICATION board, between 2 data’s must be at least equal to 300 ns (for more information about this timing see the SPARSIFICATION board documentation) The data group, which must be transferred, contains 10 words. The group sending time can be calculating according to the formula : Tsending_time = number_of_word x time_between_2_data = 10 x 300 ns = 3 µs Page 10/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 6. Matrix acquisition time calculation The matrix acquisition time can be expresses by the sum of : - TRIGGER command time duration - TRIGGER command MEGER board internal delay - Analog to Digital time duration for all the channel - Matrix reading acquisition time 6.1. TRIGGER command time duration The TRIGGER command is a command without argument and it’s defined like a 8 bit command. Its duration is equal to 8 x basis_clock = 8 x 25 ns = 200 ns 6.2. TRIGGER command MERGER board internal delay The internal delay is equal to 10 basis_clock ( 250 ns = 10 x 25 ns ). 6.3. Analog to Digital conversion time duration for all the channel This time is defined like a constant and it’s equal to 47,6 µs. 6.4. Matrix reading acquisition time With the principle of reading/transmitting explains in a previous chapter, the matrix reading acquisition time can be expresses as follows Matrix_reading_acquisition_time = Row_reading_acquisition_time * number_of_row + last_row_sending_time
= 58,55 µs * 5 + 3 µs Matrix_reading_acquisition_time
= 295,75 µs
Matrix Acquisition time = Trigger command time duration + trigger command MERGER board internal delay + Analog to Digital time duration + Matrix reading acquisition time = 200 ns + 250 ns + 47 600 ns + 295 750 ns = 342 600 ns Matrix Acquisition time = 343,8 µs 7. FPGA “MERGER” The design of this board is based on a FPGA ( ACTEL PROASIC PLUS ) and driver/receiver components. All the complete functions are defined in the FPGA which are the core of this board. 7.1. Internal architecture Rule : Rule :
Each signal output is driven by a flip flop for having a constant delay between this output and the basis clock. The calculate delay is easiest to know. In the most case each input is sample by one Flip flop for having a good functionally of the Finite State machine.
The design is divided in 3 subsystem : Command module Core module IO_data module DAC module Page 11/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
The Command module manages the command reception ( from the SPARSIFICATION box ) and the command emitting to the DAQ_FEE boards. This is the module which generates the Enable To Transmit Data command to the selected row. The Core module is the primary Finite State Machine ( FSM ) which manages the good working of the “MERGER” FPGA. The IO_data module manages the storage of the data send by the DAQ_FEE boards and the sending of them to the SPARSIFICATION box. The DAC module manage the interface between the FPGA and the Digital to Analog converter component which define the analog power applied to the calibration LED. A synoptic concerning the design internal general architecture is shown in Annex 7 page 27. 7.1.1. Core module architecture A MERGER CORE sub-module architecture is shown in Annex 8 : MAIN and SLAVE MERGER_CORE sub-module architecture page 28. 7.1.2. IO_data module architecture An IO data module architecture is shown in Annex 9 : MERGER_DATA_IO sub-module architecture page 31. This annex is divided in different figure which represent the different element which is inside. Figure 9 : IO_data module architecture page 31 Figure 10 : MERGER_DIN_IO elementary sub module page 31 Figure 11 : Merger_FSM_IO module architecture page 32 Figure 12 : MERGER_DOUT_IO Module architecture page 33 Figure 13 : MERGER_DOUT_IO Module timing diagram page 34 Figure 14 : Merger_Shift_IO FSM module architecture page 34 7.2. Package 7.2.1. Pin description SPARFICATION Box connection : Ckin :
basis clock,
generated by the SPARFICATION board, nominal value : 40MHz RSTin_N : RESET signal, low level active. This signal is coming back the SPARSIFICATION board. Din : DATA in. This serial data link coming from the SPARSIFICATION board receives the acquisition command. Enin_N : /ENABLE in, low level active. This serial link coming from the SPARSIFICATION board is the enable signal for the DATA_in line. PD_N : /Power_Down Output. This signal controls the selection of the SERDES component. When set to 0, put the SERDES component in low power but, in this application, always set to 1. CK_SERDES : Transmit clock Output. Generated by the FPGA to the SERDES component for the data transmission through the SERDES components to the SPARSIFICATION board. Nominal value : 20 MHz. This signal is generated only with a 21 bits SERDES link. With a 28 bits SERDES link this function is assumed by the basis clock, Ckin. Page 12/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 DAT[20..0] :
Figure 10
DATA_OUT[20..0] Output, data bus to the SPARSIFICATION board. The number of bits is function of the SERDES type link : 21 bits ( DATA_OUT(20..0)) for a 21 SERDES link Internal board connection : NO_ME :
board number.
This signal is set by a resistor jumper to low or high level Low level : MERGER board number 0 High level : MERGER board number 1 POR_RESET : Power on Reset : high level active, this signal become active at the power on of the MERGER board, It is generated by the 5V/3V3 DC/DC converter included on the board. Rows connection : RST[4..0] : ROW RESET, ROW :
ROW[4..0][3],
Dout :
Data out[4..0].
EN_N :
ENABLE[4..0],
SEL :
SELECT[4..0],
ENDR :
ENDR[4..0],
DR[9..0] :
DR[4..0][9..0],
PW_ROW
PW_ROW[4..0]
output, high level active, Reset signal for the DAQ_FEE board placed on the row. Each row has his own signal. output. More significant bit of the address of the row. It is only the replicate state of the NO_ME input. Each row has its own signal output, Serial data link to the DAQ_FEE board placed on the row ( the command is sent on this line. Each row has its own signal output, low level active. This signal is the enable of the data which sent on the Data out line. Each row has its own signal output, high level active. Selects the output driver when the ROW is selected to receive a command. Each row has its own signal. Enable Data to Receive, output, high level active. Selects the input receiver when the ROW is selected to transmit a data. Each row has its own signal. Data Return. Signal data from the DAQ_FEE board. There are 10 data signal by row, each coming from each DAQ_FEE board placed on the ROW. Each row has its own signals. Row Power Enable : high level active. When this bit is set to one the DAQ_FEE present on the row is powered.
LED connection : LED_VAL :
LED_VAL,
output, high level active, Validation signal for the LED. This one is powered only when this signal is active. LED_DAC_D : LED_DAC_D, output. Serial data signal for the Digital to Analog converter. LED_DAC_CK : LED_DAC_CK, output, rising edge sensitive. Serial Clock signal for the Digital to Analog converter. LED_DAC_EN : LED_DAC_EN, output, low level active. Enable signal for the Digital to Analog Converter. This component is selected only if this signal is active. SPARE : SPARE, spare output for future applications. Page 13/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
7.2.2. Pin count The design needs 119 Input/Output pins distributed in the following way : 56 inputs 63 outputs 7.2.2.1. Connection with the SPARSIFICATION box The connection with the SPARSIFICATION board use 4 inputs and 23 outputs defined like below : Ckin : input Din : input Enin_N : input RSTin_N : input PD_N : output CK_SERDES : output DAT[20..0] : output 7.2.2.2. Connection with the rows The following counting must be multiplied by 5 because the board drives 5 rows. The connection, with one row, use 10 inputs and 7 Outputs defined like below : RST : output ROW : output Dout : output EN_N : output SEL : output ENDR : output DR[9..0] : 10 inputs PW_ROW : output 7.2.2.3. Connection with the LED
LED_VAL LED_DAC_D LED_DAC_CK LED_DAC_EN SPARE
: output : output : output : output : output
7.2.2.4. Flag input Input/Output connected to a signal used only on the board ( 2 inputs ) NO_ME : input POR_RESET : input 7.2.3. Component pin out 7.2.3.1. Component pin out ( listed by name ) Pin Report – 2006 Pinchecksum: NOT-AVAILABLE Product: Designer Release: v7.0 Version: 7.0.0.11 Page 14/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Design Name: merger Family: PA Package: 456 BGA Port
Pin
CK_SERDES
K25
Function
GL1
Output Load
Port
Pin
35
dr_row1[4]
G2
Function
Output Load ---
CLK
M1
---
dr_row1[5]
G1
---
DAC_DIN
M23
35
dr_row1[6]
H2
---
DAC_SCLK
P22
35
dr_row1[7]
H1
---
DAC_SYNC_N
P23
35
dr_row1[8]
J2
---
DAT[0]
L26
35
dr_row1[9]
J1
---
DAT[1]
L25
35
dr_row2[0]
A13
---
DAT[2]
M26
35
dr_row2[1]
B12
---
DAT[3]
M25
35
dr_row2[2]
A12
---
DAT[4]
P25
35
dr_row2[3]
A11
---
DAT[5]
R26
35
dr_row2[4]
B11
---
DAT[6]
R25
35
dr_row2[5]
A10
---
DAT[7]
T26
35
dr_row2[6]
B10
---
DAT[8]
T25
35
dr_row2[7]
A9
---
DAT[9]
U26
35
dr_row2[8]
B9
---
DAT[10]
U25
35
dr_row2[9]
A8
---
DAT[11]
V26
35
dr_row3[0]
B19
---
DAT[12]
V25
35
dr_row3[1]
A19
---
DAT[13]
W26
35
dr_row3[2]
B18
---
DAT[14]
W25
35
dr_row3[3]
A18
---
DAT[15]
Y26
35
dr_row3[4]
B17
---
DAT[16]
Y25
35
dr_row3[5]
A17
---
DAT[17]
AA26
35
dr_row3[6]
B16
---
DAT[18]
AA25
35
dr_row3[7]
A16
---
DAT[19]
AB25
35
dr_row3[8]
B15
---
DAT[20]
K26
35
dr_row3[9]
A15
---
DAT_IN_ACK
AB1
35
dr_row4[0]
J26
---
DIN
AB10
---
dr_row4[1]
J25
---
dout_row[0]
P3
35
dr_row4[2]
H26
---
dout_row[1]
G3
35
dr_row4[3]
H25
---
dout_row[2]
B13
35
dr_row4[4]
G26
---
dout_row[3]
C17
35
dr_row4[5]
G25
---
dout_row[4]
G24
35
dr_row4[6]
F26
---
dr_row0[0]
R2
---
dr_row4[7]
F25
---
dr_row0[1]
R1
---
dr_row4[8]
E26
---
dr_row0[2]
T2
---
dr_row4[9]
E25
---
dr_row0[3]
T1
---
en_n_row[0]
R3
35
dr_row0[4]
U2
---
en_n_row[1]
E3
35
dr_row0[5]
U1
---
en_n_row[2]
A14
35
dr_row0[6]
V2
---
en_n_row[3]
C19
35
dr_row0[7]
V1
---
en_n_row[4]
H24
35
dr_row0[8]
W2
---
endr_row[0]
V3
35
dr_row0[9]
W1
---
endr_row[1]
H3
35
dr_row1[0]
E2
---
endr_row[2]
C10
35
dr_row1[1]
E1
---
endr_row[3]
C16
35
dr_row1[2]
F2
---
endr_row[4]
F24
35
dr_row1[3]
F1
---
ENIN_N
AB9
---
Page 15/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Port
Pin
LED_CMD
R24
Function
Output Load
Port
Pin
35
row3_row[3]
C20
Function
Output Load 35
LED_DAC_CK
P22
35
row3_row[4]
J24
35
LED_DAC_D
M23
35
rst_row[0]
Y1
35
LED_DAC_EN
P23
35
rst_row[1]
F3
35
NO_ME
AC17
---
rst_row[2]
C12
35
PD_N
K24
35
rst_row[3]
C14
35
por_reset_g
M22
---
rst_row[4]
D24
pw_row[0]
Y2
35
rstin_n_g
N23
pw_row[1]
D3
35
sel_row[0]
U3
pw_row[2]
C13
35
sel_row[1]
H4
35
pw_row[3]
C15
35
sel_row[2]
C11
35
pw_row[4]
E24
35
sel_row[3]
C18
35
row3_row[0]
T3
35
sel_row[4]
J23
35
row3_row[1]
C2
35
SPARE
M24
35
row3_row[2]
B14
35
trig_received
AB16
35
GL4
35 GL3
--35
7.2.3.2. Component pin out ( listed by pin ) Pin Report 2006 Pin checksum: NOT-AVAILABLE Product: Designer Release: v7.0 Version: 7.0.0.11 Design Name: merger Family: PA Package: 456 BGA Nber
Port
A1
Function
State
Nber
VDDP
Reserved
Port
Function
State
A25
VDDP
Reserved
VDDP
A2
VDDP
Reserved
A26
A3
Not Bonded
Unconnected
AA1
Unassigned
A4
Not Bonded
Unconnected
AA2
Unassigned
A5
Not Bonded
Unconnected
AA3
Unassigned
A6
Not Bonded
Unconnected
AA4
Unassigned
Not Bonded
A7
Reserved
Unconnected
AA5
VDD
Reserved
A8
dr_row2[9]
Fixed
AA22
VDD
Reserved
A9
dr_row2[7]
Fixed
AA23
A10
dr_row2[5]
Fixed
AA24
A11
dr_row2[3]
Fixed
AA25
DAT[18]
Fixed
A12
dr_row2[2]
Fixed
AA26
DAT[17]
Fixed
A13
dr_row2[0]
Fixed
AB1
DAT_IN_ACK
A14
en_n_row[2]
Fixed
AB2
Unassigned
A15
dr_row3[9]
Fixed
AB3
Unassigned
A16
dr_row3[7]
Fixed
AB4
Unassigned
A17
dr_row3[5]
Fixed
AB5
VDD
Reserved
A18
dr_row3[3]
Fixed
AB6
VDD
Reserved
A19
dr_row3[1]
Fixed
AB7
VDD
Reserved
Unassigned Unassigned
Fixed
A20
Not Bonded
Unconnected
AB8
A21
Not Bonded
Unconnected
AB9
ENIN_N
Unassigned Fixed
A22
Not Bonded
Unconnected
AB10
DIN
Fixed
A23
Not Bonded
Unconnected
AB11
Unassigned
A24
Not Bonded
Unconnected
AB12
Unassigned
Page 16/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Nber
State
Nber
AB13
Unassigned
AD10
Unassigned
AB14
Unassigned
AD11
Unassigned
AB15
Unassigned
AD12
Unassigned
Fixed
AD13
Unassigned
AB17
Unassigned
AD14
Unassigned
AB18
Unassigned
AD15
Unassigned
AB16
Port
Function
TRIG_RECEIVED
AB19
Port
Function
State
Unassigned
AD16
Unassigned
AB20
VDD
Reserved
AD17
Unassigned
AB21
VDD
Reserved
AD18
Unassigned
AB22
VDD
Reserved
AD19
AB23
Unassigned
AD20
Not Bonded
Unconnected
AB24
Unassigned
AD21
TCK
Reserved
AB25
DAT[19]
Unassigned
Fixed
AD22
VPP
Reserved
Unconnected
AD23
Not Bonded
Unconnected
AC1
Unassigned
AD24
VDDP
Reserved
AC2
Unassigned
AD25
Not Bonded
Unconnected
AC3
Unassigned
AD26
Not Bonded
Unconnected
AB26
Not Bonded
AC4
VDDP
Reserved
AE1
VDDP
Reserved
AC5
Not Bonded
Unconnected
AE2
VDDP
Reserved
AC6
Unassigned
AE3
Not Bonded
Unconnected
AC7
Unassigned
AE4
Not Bonded
Unconnected
AC8
Unassigned
AE5
Not Bonded
Unconnected
AC9
Unassigned
AE6
Not Bonded
Unconnected
AC10
Unassigned
AE7
Not Bonded
Unconnected
AC11
Unassigned
AE8
Unassigned
AC12
Unassigned
AE9
Unassigned
AC13
Unassigned
AE10
Unassigned
AC14
Unassigned
AE11
Unassigned
AC15
Unassigned
AE12
Unassigned
AC16
Unassigned
AE13
Unassigned
AC17
Fixed
AE14
Unassigned
AC18
NO_ME
Unassigned
AE15
Unassigned
AC19
Unassigned
AE16
Unassigned
AC20
Unassigned
AE17
Unassigned
AC21
TMS
Reserved
AE18
Unassigned
AC22
TDO
Reserved
AE19
Unassigned
AC23
VDDP
Reserved
AE20
Not Bonded
Unconnected
AC24
RCK
Reserved
AE21
Not Bonded
Unconnected
AC25
Not Bonded
Unconnected
AE22
Not Bonded
Unconnected
Unassigned
AE23
VPN
Reserved
Unconnected
AE24
TRST
Reserved
AC26 AD1
Not Bonded
AD2
Unassigned
AE25
VDDP
Reserved
AD3
VDDP
Reserved
AE26
VDDP
Reserved
AD4
Not Bonded
Unconnected
AF1
VDDP
Reserved
AD5
Not Bonded
Unconnected
AF2
VDDP
Reserved
AD6
Not Bonded
Unconnected
AF3
Not Bonded
Unconnected
AD7
Unassigned
AF4
Not Bonded
Unconnected
AD8
Unassigned
AF5
Not Bonded
Unconnected
AD9
Unassigned
AF6
Not Bonded
Unconnected
Page 17/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Nber
Port
Function
State
Nber
AF7
Not Bonded
Unconnected
AF8
Not Bonded
Port
Function
State
C4
Not Bonded
Unconnected
Unconnected
C5
Not Bonded
Unconnected
AF9
Unassigned
C6
Not Bonded
Unconnected
AF10
Unassigned
C7
Unassigned
AF11
Unassigned
C8
Unassigned
AF12
Unassigned
C9
Unassigned
AF13
Unassigned
C10
endr_row[2]
Fixed
AF14
Unassigned
C11
sel_row[2]
Fixed
AF15
Unassigned
C12
rst_row[2]
Fixed
AF16
Unassigned
C13
pw_row[2]
Fixed
AF17
Unassigned
C14
rst_row[3]
Fixed
AF18
Not Bonded
Unconnected
C15
pw_row[3]
Fixed
AF19
Not Bonded
Unconnected
C16
endr_row[3]
Fixed
AF20
Not Bonded
Unconnected
C17
dout_row[3]
Fixed
AF21
Not Bonded
Unconnected
C18
sel_row[3]
Fixed
AF22
Not Bonded
Unconnected
C19
en_n_row[3]
Fixed
AF23
TDI
Reserved
C20
row3_row[3]
Fixed
AF24
Not Bonded
Unconnected
C21
Not Bonded
Unconnected
AF25
VDDP
Reserved
C22
Not Bonded
Unconnected
AF26
VDDP
Reserved
C23
Not Bonded
Unconnected
B1
VDDP
Reserved
C24
VDDP
Reserved
B2
VDDP
Reserved
C25
Not Bonded
Unconnected
B3
Not Bonded
Unconnected
C26
Not Bonded
Unconnected
B4
Not Bonded
Unconnected
D1
Not Bonded
Unconnected
B5
Not Bonded
Unconnected
D2
Not Bonded
Unconnected
B6
Not Bonded
Unconnected
D3
B7
Not Bonded
Unconnected
D4
VDDP
Reserved
Unassigned
D5
Not Bonded
Unconnected
Not Bonded
Unconnected
B8
pw_row[1]
Fixed
B9
dr_row2[8]
Fixed
D6
B10
dr_row2[6]
Fixed
D7
Unassigned
B11
dr_row2[4]
Fixed
D8
Unassigned
B12
dr_row2[1]
Fixed
D9
Unassigned
B13
dout_row[2]
Fixed
D10
Unassigned
B14
row3_row[2]
Fixed
D11
Unassigned
B15
dr_row3[8]
Fixed
D12
Unassigned
B16
dr_row3[6]
Fixed
D13
Unassigned
B17
dr_row3[4]
Fixed
D14
Unassigned
B18
dr_row3[2]
Fixed
D15
Unassigned
B19
dr_row3[0]
Fixed
D16
Unassigned
B20
Not Bonded
Unconnected
D17
Unassigned
B21
Not Bonded
Unconnected
D18
Unassigned
B22
Not Bonded
Unconnected
D19
Unassigned
B23
Not Bonded
Unconnected
D20
Unassigned
B24
Not Bonded
Unconnected
D21
Unassigned
B25
VDDP
Reserved
D22
Not Bonded
Unconnected
B26
VDDP
Reserved
D23
VDDP
Reserved
VDDP
Reserved
D24
Fixed
D25
Not Bonded
Unconnected
Reserved
D26
Not Bonded
Unconnected
C1 C2 C3
row3_row[1] VDDP
rst_row[4]
Fixed
Page 18/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Nber
Port
Function
State
Nber
Fixed
H4
Port
Function
E1
dr_row1[1]
E2
dr_row1[0]
Fixed
H5
VDD
Reserved
E3
en_n_row[1]
Fixed
H22
VDD
Reserved
Unassigned
H23
E4
sel_row[1]
State Fixed
Unassigned
E5
VDD
Reserved
H24
en_n_row[4]
Fixed
E6
VDD
Reserved
H25
dr_row4[3]
Fixed
E7
VDD
Reserved
H26
dr_row4[2]
Fixed
E8
VDD
Reserved
J1
dr_row1[9]
Fixed
E9
Unassigned
J2
dr_row1[8]
Fixed
E10
Unassigned
J3
Unassigned
E11
Unassigned
J4
Unassigned
E12
Unassigned
J5
Unassigned
E13
Unassigned
J22
E14
Unassigned
J23
sel_row[4]
E15
Unassigned
J24
row3_row[4]
Fixed
E16
Unassigned
J25
dr_row4[1]
Fixed
E17
Unassigned
J26
dr_row4[0]
Fixed
E18
Unassigned
K1
Unassigned
E19
Unassigned
K2
Unassigned
Unassigned Fixed
E20
VDD
Reserved
K3
Unassigned
E21
VDD
Reserved
K4
Unassigned
E22
VDD
Reserved
K5
Unassigned
E23
Unassigned
K22
Unassigned
E24
pw_row[4]
Fixed
K23
Unassigned
E25
dr_row4[9]
Fixed
K24
PD_N
Fixed
E26
dr_row4[8]
Fixed
K25
CK_SERDES
Fixed
F1
dr_row1[3]
Fixed
K26
DAT[20]
Fixed
F2
dr_row1[2]
Fixed
L1
Unassigned
F3
rst_row[1]
F4
Fixed
L2
Unassigned
Unassigned
L3
Unassigned
F5
VDD
Reserved
L4
Unassigned
F22
VDD
Reserved
L5
Unassigned
Unassigned
L11
GND
Reserved
F23 F24
endr_row[4]
Fixed
L12
GND
Reserved
F25
dr_row4[7]
Fixed
L13
GND
Reserved
F26
dr_row4[6]
Fixed
L14
GND
Reserved
G1
dr_row1[5]
Fixed
L15
GND
Reserved
G2
dr_row1[4]
Fixed
L16
GND
Reserved
G3
dout_row[1]
G4 G5
VDD
G22
VDD
G23
Fixed
L22
Unassigned
Unassigned
L23
Unassigned
Reserved
L24
Unassigned
Reserved
L25
DAT[1]
Fixed
Unassigned
L26
DAT[0]
Fixed
CLK
G24
dout_row[4]
Fixed
M1
GL1
G25
dr_row4[5]
Fixed
M2
G26
dr_row4[4]
Fixed
M3
Unassigned
H1
dr_row1[7]
Fixed
M4
Unassigned
H2
dr_row1[6]
Fixed
M5
Unassigned
H3
endr_row[1]
Fixed
M11
GL2
GND
Special Special
Reserved
Page 19/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Nber
Port
Function
State
Nber
M12
GND
Reserved
M13
GND
M14
GND
M15 M16
Port
Function
State
R13
GND
Reserved
Reserved
R14
GND
Reserved
Reserved
R15
GND
Reserved
GND
Reserved
R16
GND
Reserved
GND
Reserved
R22
Unassigned
GL4
Special
R23
Unassigned
M22
POR_RESET_G
M23
DAC_DIN
Fixed
R24
LED_CMD
Fixed
M24
SPARE
Fixed
R25
DAT[6]
Fixed
M25
DAT[3]
Fixed
R26
DAT[5]
Fixed
M26
DAT[2]
Fixed
T1
dr_row0[3]
Fixed
Unassigned
T2
dr_row0[2]
Fixed
I/O(GLMX1)
Unassigned
T3
row3_row[0]
Fixed
N3
AGND
Reserved
T4
Unassigned
N4
PPECL1(I/P)
Special
T5
Unassigned
N1 N2
N5
AVDD
Reserved
T11
GND
Reserved
N11
GND
Reserved
T12
GND
Reserved
N12
GND
Reserved
T13
GND
Reserved
N13
GND
Reserved
T14
GND
Reserved
N14
GND
Reserved
T15
GND
Reserved
N15
GND
Reserved
T16
GND
Reserved
N16
GND
Reserved
T22
Unassigned
N22
NPECL2
Special
T23
Unassigned
N23
GL3
Special
T24
N24
RSTIN_N_G
AVDD
Reserved
T25
DAT[8]
Unassigned Fixed
N25
I/O(GLMX2)
Unassigned
T26
DAT[7]
Fixed
N26
AGND
Reserved
U1
dr_row0[5]
Fixed
P1
Unassigned
U2
dr_row0[4]
Fixed
P2
Unassigned
U3
sel_row[0]
Fixed
P3
dout_row[0]
P4
Fixed
U4
Unassigned
Unassigned
U5
Unassigned
P5
NPECL1
Special
U22
Unassigned
P11
GND
Reserved
U23
Unassigned
P12
GND
Reserved
U24
Unassigned
P13
GND
Reserved
U25
DAT[10]
Fixed
P14
GND
Reserved
U26
DAT[9]
Fixed
P15
GND
Reserved
V1
dr_row0[7]
Fixed
GND
Reserved
V2
dr_row0[6]
Fixed
Fixed
V3
endr_row[0]
Fixed
P16 P22
DAC_CLK
P23
DAC_SYNC_N
P24 P25
DAT[4]
P26
PPECL2(I/P)
Fixed
V4
Unassigned
Unassigned
V5
Unassigned
Fixed
V22
Unassigned
Special
V23
Unassigned
R1
dr_row0[1]
Fixed
V24
Unassigned
R2
dr_row0[0]
Fixed
V25
DAT[12]
Fixed
R3
en_n_row[0]
R4 R5
Fixed
V26
DAT[11]
Fixed
Unassigned
W1
dr_row0[9]
Fixed
dr_row0[8]
Unassigned
W2
R11
GND
Reserved
W3
Unassigned
Fixed
R12
GND
Reserved
W4
Unassigned
Page 20/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Nber
Port
Function
State
Nber
W5
VDD
Reserved
Y3
W22
VDD
Port
Function
State Unassigned
Reserved
Y4
W23
Unassigned
Y5
VDD
Unassigned Reserved
W24
Unassigned
Y22
VDD
Reserved
W25
DAT[14]
Fixed
Y23
Unassigned
W26
DAT[13]
Fixed
Y24
Unassigned
Y1
rst_row[0]
Fixed
Y25
DAT[16]
Fixed
Y2
pw_row[0]
Fixed
Y26
DAT[15]
Fixed
7.2.4. FPGA consumption Power Report for design merger with the following settings : Vendor Program Date Version
= = = =
Actel Corporation Actel Designer Software, Release v7.0, Copyright © 1989-2005 Sat Feb 11 20:20:25 2006 01.01.01
Family Die Package Temperature Voltage Speed Conditions
= = = = = = =
PA APA300 456 BGA IND IND STD Typical
Exploration Max Depth Exploration Min Ratio Exploration Min Value Report Static Power Report Dynamic Power Report Power Breakdown Flattened Power Report
= = = = = = =
None None None Yes Yes No No
Section Static Power Summary Block merger, 11.000000 mW End Section Section Dynamic Power Summary Block merger, 223.727904 mW End Section 8. Reference documentation
CHER_DAQ : interface document, O. BOURRION CHERCAM : SPARSIFICATION box, O. BOURRION DAQ_FEE, front end electronics for CHERCAM detector, B. BOYER MAX9173 : Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe, MAXIM MAX9123 : Quad LVDS Line Driver with Flow-Through Pinout, MAXIM
Page 21/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 1 : Logical parts block diagram with 21 bits SERDES FPGA ACTEL APA300-BG456I BSN20
ROW_1 CONNECTOR
POWER MODULE
RST[0] PW_ROW[4..0] POR_RESET
90LV047
CLK
PW_ROW[4..0] POR_RESET
ROW[3] ROW[2] ROW[1] DOUT ROW[0] /EN 3V3
ROW[0]
1 KΩ
ENDR[0]
EN
10 12
LED INTERFACE
BSN20
RST1]
LED_VAL LED_DAC_D LED_DAC_CK LED_DAC_EN
LED_VAL LED_DAC_D LED_DAC_CK LED_DAC_EN SPARE
LED_OUT
1 KΩ
CHER_DAQ MERGER board
1 KΩ
90LV047
CLK[1]
ROW[3]
DATA Acquisition Laboratoire de Physique Subatomique et de Cosmologie Grenoble, FRANCE rev.: 6, July 9 2006
ROW[1]
ROW[2] ROW[1] DOUT ROW[0] /EN 3V3
DOUT[1]
/EN EN 100 Ω
SEL[1] ENDR[1]
EN
10 12
DAT[20..0]
IN[20..0]
20
DR[1][9..0]
/EN DS90LV047 10KΩ
PD_N
ROW_3 CONNECTOR
TX1
TX1
TX2
TX2
TX3
TX3
CK
CK
/PD
CK_SERDES BSN20
SPARSIFICATION CONNECTOR
SERDES DS90CR215
EN_N[1]
RST[2] 1 KΩ
/RST
100 Ω
RSTin_N
/RST
90LV048
CLK
3V3_2 2V5_2 3V3A_2 -2VA_2
ROW[3] ROW[2] ROW[1] DOUT ROW[0] /EN 3V3 2V5 3V3A -2VA GND
Din
DATA 100 Ω
ROW[2] ENin_N
ENABLE
DOUT[2] 100 Ω
EN_N[2] /EN EN 100 Ω
D[9..0]
100 Ω
74LVC245
CLK[2]
All signals are LVDS level
CLK
D[9..0]
2V5_[4..0] 3V3_[4..0] 3V3A_[4..0] -2VA_[4..0]
DR[0][9..0]
/RST
2V5 3V3A -2VA GND
S_3V3_I S_2V5[4..0] S_3V3[4..0] S_3V3A[4..0] S_2VA[4..0]
SEL[0]
/EN DS90LV048 10KΩ
3V3_1 2V5_1 3V3A_1 -2VA_1
3V3_I
NO_ME
ROW_2 CONNECTOR
HSK[4..0]
S_2V5_I
1 KΩ
EN_N[0]
100 Ω
D[9..0]
3V3
DOUT[0]
/EN EN
HSK CONNECTOR
HSK[4..0]
CLK[0] 2V5
2V5 3V3A -2VA GND
5V_pow M3V3_pow
1 KΩ
/RST
3V3_0 2V5_0 3V3A_0 -2VA_0
POWER CONNECTOR
5V_pow M3V3_pow
CKin
CLK
SEL[2] 90LV048
ENDR[2]
EN
10 12
LVDS to LVTTL translator
DR[2][9..0] /EN
DS90LV048 10KΩ
CLK[4..0]
ROW_4 CONNECTOR
BSN20
RST[3]
/RST
1 KΩ
3V3_3 2V5_3 3V3A_3 -2VA_3
CLK[3]
ROW[3] ROW[2] ROW[1] DOUT ROW[0] /EN 3V3 2V5 3V3A -2VA GND
/EN EN 100 Ω
D[9..0]
EN
10 12 DS90LV048 10KΩ
CLK
CLK[4] ROW[3]
ROW[4]
DOUT[3]
DOUT[4]
EN_N[3]
EN_N[4]
SEL[3] ENDR[3] DR[3][9..0]
/EN
/RST 90LV047
90LV047
CLK
ROW_5 CONNECTOR
BSN20
RST[4]
1 KΩ
SEL[4] ENDR[4]
ROW[3] ROW[2] DOUT ROW[1] ROW[0] /EN 3V3 EN /EN EN
100 Ω
12 10
DR[4][9..0]
D[9..0]
2V5 3V3A -2VA GND
3V3_4 2V5_4 3V3A_4 -2VA_4
/EN 10KΩ DS90LV048
Page 22/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 2 : Power parts block diagram 5V_pow I_5V
I_measurement
CHER_DAQ MERGER board
HSK[0]
DATA Acquisition Laboratoire de Physique Subatomique et de Cosmologie Grenoble, FRANCE rev.: 1, May 8 2006
ROW_POWER ( x 5 )
3V3 Linear regulator ( 3V3 row power )
3V3A_[x]
I_2V5
3V3A_[4..0] HSK[2] 2V5_[4..0]
5V 1N4148 I_measurement
I_3V3 I_2V5
3V3_[4..0] HSK[3] -2VA_[4..0]
PW_ROW[4..0] En
2V5 regulator
2V5_[x]
3V3 regulator
3V3_[x]
PW_ROW[x] En
I_3V3
I_measurement 1N4148
5V
-2V Linear regulator ( -2V row power )
-2VA_[x]
I_M3V5
I_measurement
HSK[1]
M3V3_pow
MERGER BOARD POWER 5V 1N4148 I_measurement
I_2V5
2V5 regulator
En
3V3 regulator
2V5_I 3V3_I POR_RESET
RST
I_3V3
I_measurement 1N4148
5V Temperature sensor
HSK[4]
Page 23/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 3 : LED interface diagram
CHER_DAQ LED INTERFACE DATA Acquisition Laboratoire de Physique Subatomique et de Cosmologie Grenoble, FRANCE rev.: 2, July 9 2006 Scheme : G. BOSSON
Analog Switch ADG713BRZ
LED_VAL 1 KΩ LED_DAC_D
Data
LED_DAC_CK
Clock
LED_DAC_EN
Enable
0
Ω
Vout
AD5320BRM 12 bit DAC +V
0Ω
Pulse Transformer
LED_OUT
10 nF
-V
3V3
Annex 4 : LED command sequence
LED OFF/ON 16 CLK CLOCK
Command IN Command LED
10 CLK
Cpmmand OUT
TRIGGER with LED ON 8 CLK CLOCK
Command IN
TRIGGER command LED_ENABLE_TIME ( one basis Clock )
Command LED Command OUT
TRIGGER command
TRIGGER with LED OFF 8 CLK CLOCK
Command IN
TRIGGER command
Command LED Command OUT
TRIGGER command
Page 24/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 5 : boards implantation on the detector
Cable between the HOUSE KEEPING board an d the MERGER board ( 2 flat cable of 14 conductors ) Cable between theSPARFISICATION board and the MERGER board ( 4 cables ethernet type )
Connector FLEX ( 5) 4 wire power cable come from the primary power module
Connector FLEX ( 5) Board to board Power cable ( 4 wire ) connect power from MERGER1 to MERGER2
Page 25/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 6 : Row Data Acquisition Sequence SELECTED ROW
Acquisition Time for one word : 144 CLK
Twac 6 CLK
8 CLK
4 CLK
8 CLK
16 x 8 CLK
8 CLK
Acquisition time for one row minus one word (15 words): 15 x 18 x 8 CLK
CLOCK
ENDR[x] /EN DOUT
Enable To Transmit Data command
D[0]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[1]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[2]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[3]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[4]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[5]
Value_ 0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[6]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[7]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[8]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
D[9]
Value_0[0]
Value_0[17]
Value_1[0]
Value_15[17]
DISABLED ROW CLOCK
/EN DOUT D[9..0]
Page 26/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
5 CLK
MERGER Board, Version 8 ,May 2007 Annex 7 : “MERGER” FPGA synoptic with 21 bits SERDES
Gnd
RSTin_N
NO_ME
RST
PD_N
RST[4..0]
NO_ME
ROW[4..0]
COMMAND Module RST
RST
CLK
CLK
Din
Din
ENin_N
DOUT
DOUT[4..0]
ENout
EN_N[4..0]
Ein LD_CMD
LD_CMD
DATin ENin
IDLE
IDLE
RST
RST
SEL[4..0]
CLK
LD_CMD
DATin ENin
CORE Module CKin
CLK DATin ENin BUSY
DATin
IDLE
SEL[4..0]
SEL[4..0]
LD_CMD IDLE
ENin BUSY
ENDR[4..0] DAC_CMD DAC_DAT[15..0]
ENDR[4..0]
ENDR[4..0]
DAC_CMD DAC_DAT[15..0]
MERGER_DATA_IO Sub-Module RST
RST
CLK
CLK
LD_CMD DR[4..0][9..0]
ENDR[4..0]
ENout
BUSY
BUSY
DAT[20..0]
DAT[20..0]
ENDR[4..0] DR[4..0][9..0]
IDLE NO_ME
IDLE NO_ME
MERGER_DAC Sub-Module RST
RST
CLK
CLK
DAC_CMD DAC_DAT[15..0]
DAC_CMD DAC_DAT[15..0]
DAC_SYNC_N DAC_SCLK DAC_DIN
DAC_SYNC_N DAC_SCLK DAC_DIN
"MERGER" FPGA August 10 2006 Data Acquisition Laboaratoire de Physique Subatomique et de Cosmologie Grenoble, FRANCE
Page 27/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
Annex 8 : MAIN and SLAVE MERGER_CORE sub-module architecture begin
INDIC_CMD = '0' CPT_DELAY = "000"
RESET
FSM_BAS0
ENABLE = '1'
INDIC_CMD = '1' CPT_DELAY = "000"
FSM_BAS1 CPT_DELAY = 7
CPT_DELAY = CPT_DELAY + 1
INDIC_CMD = '0'
FSM_BAS2 ENABLE = '0'
Figure 5 : MAIN MERGER_CORE sub module begin
sel_int = "00000" endr_int = "00000" cpt_cmd_ack = x'0' cmd_int = 0 cpt_wconvert = 0 LD_CMD = 0 LED_CMD = '0' DAC_CMD = '0' dac_dat = x"000"
INDIC_CMD_INT = '1'
CMD_WAT0
NOP
CMD_WAT1
NOP
RESET
IDDLE
cpt_cmd_ack = 0
CMD_WAT2
datin(3..0) = ID_CD_MERGER
sel_int = "11111"
CMD_ACK0
cpt_cmd_ack = 7
cpt_cmd_ack = cpt_cmd_ack + 1
cmd_int = dat_in
CMD_ACK1
cmd_int = "TRIGGER"
cpt_cmd_ack = 0
To CMD_ACK2 state
LED_CMD = DAC_VAL
To CMD_LEC0 state
Figure 6 : SLAVE MERGER_CORE sub module (1/3) Page 28/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 From CMD_ACK1 state
cpt_wconvert = 0 LED_CMD = '0'
CMD_LEC0
convert_temp = 47,6 µs cpt_wconvert = convert_temp
CMD_LEC1
convert_temp = Analog to Digital conversion time duration for all the channel
CMD_LEC2 sel_int ="00001" endr_int = "00001"
cpt_wconvert = cpt_wconvert + 1
CMD_LEC4
NO_ME = 0
CMD_LEC3
cpt_cmd_ack = 0 CMD_LEC11 cpt_cmd_ack = cpt_cmd_ack + 1
cpt_cmd_ack = 7
CMD_LEC5
LD_CMD = 1
CMD_LEC6
LD_CMD = 0
CMD_LEC7
BUSY = '1'
CMD_LEC8
BUSY = '0'
CMD_DELA0
cpt_cmd_ack = 0
CMD_DELA1
cpt_cmd_ack = CK_ATCMD
CMD_LEC9
ASL(sel_int) ASL(endr_int)
cpt_cmd_ack = cpt_cmd_ack + 1
CMD_DELA2
sel_int = "00000"
NOP
CMD_DELA3
the number of row clock generated after the command is equal to : ( CK_ATCMD x 3 ) + 2
CMD_LEC10
To IDDLE state
Figure 7 : SLAVE MERGER_CORE sub module (2/3)
Page 29/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 To IDDLE state From CMD_ACK1 state CMD_ACK3 CMD_ACK2
cpt_cmd_ack = 3
cpt_cmd_ack = cpt_cmd_ack + 1
cmd_int = "D0"
dac_dat(7..0) = datin
"D1"
dac_dat(15..8) = datin DAC_CMD = '1'
"D2"
DAC_VAL = '1'
"D3"
DAC_VAL = '0'
others
CMD_ACK4
cpt_cmd_ack = 0
the number of row clock generated after the command is equal to : ( CK_ANCMD x 4 ) + 2 CMD_ACK5
CMD_ACK9
cpt_cmd_ack = CK_ANCMD
sel_int ="00000"
cpt_cmd_ack = cpt_cmd_ack + 1
CMD_ACK6
NOP
CMD_ACK7
NOP
CMD_ACK8
Figure 8 : SLAVE MERGER_CORE sub module (3/3)
Page 30/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
Annex 9 : MERGER_DATA_IO sub-module architecture
MERGER_DATA_IO Module MERGER_SHIFT_IO RST CLK ENDR[4..0] NO_ME MERGER_FSM_IO RST CLK IDLE
RST CLK IDLE ENOUT
ENDR[4..0]
RST CLK IDLE
IDLE
NO_ME IDLE
OUT[9..0] MDAT CDAT
LD_BIT[9..0] MDAT CDAT DAT[21]
VALID_DATA OUT_DATA_GENE
LOAD_BIT LOAD_WORD ROW_AD[3..0] COLUMN_AD[3..0]
LOAD_BIT LOAD_WORD
ENOUT ENDR[4..0]
RST CLK ENDR[4..0]
VALID_DATA ROW_AD[3..0] COLUMN_AD[3..0] RST CLK
BUSY
RST DAT[15..12] CLK DATOUT[17..0]
ENDR[4..0] BUSY
MERGER_DIN_IO
RST CLK LD_BIT[9..0] DR[4..0][9..0]
DAT[15..12]
ENDR[4..0] RST CLK LD_BIT[9..0] DR[4..0][9..0]
MERGER_DOUT_IO DATin[0] DATin[1] DATin[2] DATin[3] DATin[4] DATin[5] DATin[6] DATin[7] DATin[8] DATin[9] RST CLK MDAT CDAT
DATin[0] DATin[1] DATin[2] DATin[3] DATin[4] DATin[5] DATin[6] DATin[7] DATin[8] DATin[9] RST CLK MDAT CDAT
DOUT
LPSC AKIDO Fevruary 3 2006
Figure 9 : IO_data module architecture The following scheme show a part of the MERGER_DIN_IO module. This one contains 10 element of the following picture. ENDR[4..0] DR[0][x] DR[1][x] DR[2][x]
18 bits Shift Register D
DR[3][x] DR[4][x] LD_BIT[x]
Q
18
DATin[x]
CE
CLK RST
AR
with x = 0 to 9
Figure 10 : MERGER_DIN_IO elementary sub module
Page 31/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
begin
RESET
IDLE
cpt_bit = "00000" cpt_word = "0000" cpt_twac = "0000" load_bit = '0' load_word = '0' busy = '0'
ENout = 1 and ENDR = 1
ENDR = OR ( ENDR[4..0] )
busy = '1'
ACK_CMD
ENout = 0
WAIT_TWAC
wait for Twac
DAQ_BIT0
NOP
DAQ_BIT1
NOP
DAQ_BIT2
load_bit = 1
DAQ_BIT3
load_bit = 0
DAQ_BIT4
cpt_bit = 0x11
DAQ_WORD0
cpt_bit = 0
cpt_bit = cpt_bit + 1
DAQ_BIT5
DAQ_WORD1
load_word = 1
NOP
DAQ_BIT6
DAQ_WORD2
load_word = 0
NOP
DAQ_BIT7
cpt_word = 0xF
DAQ_WORD4
cpt_word = cpt_word + 1
cpt_word = 0 busy = '0'
DAQ_WORD3
DAQ_END
Figure 11 : Merger_FSM_IO module architecture Page 32/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 LOW_HIGH MDAT CLK RST AR
Q
AR
D
Q
Gnd
D
Q
MDAT[8]
MDAT[9] DATin[0] DATin[1] DATin[2] DATin[3] DATin[4] DATin[5] DATin[6] DATin[7] DATin[8] DATin[9]
AR
AR
D
Q
MDAT[7]
AR
D
Q
MDAT[6]
AR
D
Q
MDAT[5]
AR
D
Q
MDAT[4]
AR
D
Q
MDAT[3]
AR
D
Q
MDAT[2]
AR
D
Q
MDAT[1]
AR
D
B
D D
B
D
B
D
B
D
B
D
B
D
B
D
B
D
Q
Q
Q
Q
CE CE
7 8
9
Q
A
D
Q
DATout[18..0]
CE 0 AR
1 2
3 4
5
Q
CE
CE
CE 6
A
DATout[19]
B
D
A
A
CE
CE
CE CE
Q
A
A
A
A
A
A
A
Q
Q
Q
Q
MDAT[0]
B B
D
AR
AR
AR
AR
AR
AR
AR
AR
AR
AR CLK RST CDAT[9] Q
D
CDAT[8]
CDAT[7]
CDAT[6]
CDAT[5]
CDAT[4]
CDAT[3]
CDAT[2]
CDAT[1]
CDAT[0]
Q
Q
Q
Q
Q
Q
Q
Q
Q
AR
D
AR
D
AR
D
AR
AR
D
AR
D
AR
D
D
AR
AR
D
D
AR
RST CLK CDAT V_DAT_INT AR AR D ENDR[4..0]
Q
CE D
Q
Figure 12 : MERGER_DOUT_IO Module architecture
Page 33/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
D
Q
AR
DATout[20]
MERGER Board, Version 8 ,May 2007 CLK DATin[0]
value[0,0]
DATin[1]
value[1,0]
DATin[2]
value[2,0]
DATin[3]
value[3,0]
DATin[4]
value[4,0]
DATin[5]
value[5,0]
DATin[6]
value[6,0]
DATin[7]
value[7,0]
DATin[8]
value[8,0]
DATin[9]
value[9,0]
MDAT[0] CDAT[0] Q[0]
value[0,0]
value[1,0]
value[2,0]
value[3,0]
value[4,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[1,0]
value[2,0]
value[3,0]
value[4,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[2,0]
value[3,0]
value[4,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[3,0]
value[4,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[4,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[5,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[6,0]
value[7,0]
value[8,0]
value[9,0]
value[7,0]
value[8,0]
value[9,0]
value[8,0]
value[9,0]
MDAT[1] CDAT[1] Q[1] MDAT[2] CDAT[2] Q[2] MDAT[3] CDAT[3] Q[3] MDAT[4] CDAT[4] Q[4] MDAT[5] CDAT[5] Q[5] MDAT[6] CDAT[6] Q[6] MDAT[7] CDAT[7] Q[7] MDAT[8] CDAT[8] Q[8] MDAT[9] CDAT[9] Q[9]
value[9,0]
Figure 13 : MERGER_DOUT_IO Module timing diagram
Page 34/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
value[9,0]
MERGER Board, Version 8 ,May 2007 begin
STATE AT POWER UP
Shift_IO_begin
CDAT = '0' CPT_CDAT = "0000" VALID_DATA ='1'
Shift_IO_ack
LOAD_W ORD = 1 ?
CDAT = '0' CPT_CDAT = "0000" COLUMN_AD = "0000" ROW _AD = "000" LOW _HIGH ='1'
CDAT = '1'
Shift_IO_init
Shift_IO_init0
CDAT = '0' COLUMN_AD = CPT_MDAT ROW _AD = ROW _AD_INT VALID_DATA = '0'
NOP
ENDR[4..0]
ROW _AD_INT
00001 00010 00100 01000 10000
000 001 010 011 100
V_DAT_INT = '1'
Shift_IO_init1
CPT_CDAT = x"4" ?
Shift_IO_init2
CPT_CDAT = x"7"
Shift_IO_init4
V_DAT_INT = '0'
Shift_IO_init5
NOP
Shift_IO_init6
NOP
Shift_IO_init7
LOW _HIGH = '1'
IDDLE = '0' ?
NOP
Shift_IO_init3
Shift_IO_init8
V_DAT_INT = '1'
NOP
CPT_CDAT = CPT_CDAT + 1 V_DAT_INT = '0'
Shift_IO_init9
Shift_IO_init10
CDAT = '1'
Shift_IO_init11
CPT_CDAT = x"C" ?
Figure 14 : Merger_Shift_IO FSM module architecture Page 35/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
Annex 10 : SPARSIFICATION up LINK connector pin out
Pin Number
Name signal
1
LVDS_DATA_RX+
2
LVDS_DATA_RX-
3
LVDS_EN_RX+
4
LVDS_NRST_RX-
5
LVDS_NRST_RX+
6
LVDS_EN_RX-
7
LVDS_CLK_RX+
8
LVDS_CLK_RX+
Annex 11 : SPARSIFICATION down LINK connector pin out
Pin Number
Name signal
1
LVDS_TX0-
2
LVDS_ TX0+
3
LVDS_ TX1-
4
LVDS_ TX2+
5
LVDS_ TX2-
6
LVDS_ TX1+
7
LVDS_TXCLK-
8
LVDS_ TXCLK+
Page 36/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 12 : Board scheme 8
7
ENDR RST SEL
ENDR RST SEL GND NO_ME PW_ROW0
3V3 GND GND NO_ME PW_ROW1
CLK_ROW DOUT EN_N ENDR RST SEL GND 3V3 GND NO_ME PW_ROW2 5V 3V3 GND -3V5 CLK_ROW DOUT EN_N
B
ENDR RST SEL 3V3 3V3 GND NO_ME PW_ROW3 5V 3V3 GND -3V5 CLK_ROW DOUT EN_N
A
ENDR RST SEL GND GND 3V3 NO_ME PW_ROW4 5V 3V3 GND -3V5
8
ROW0 ROW1 ROW2 ROW3 PW_ROW
ENDR RST SEL
ENDR RST SEL
C
4
3
I_2V5
I_2V5
I_3V3
I_3V3
0
5v 3v3 GND -3v5
E
MERGER_FPGA DOUT EN_N PW_ROW0 ENDR RST SEL
DOUT_ROW0 EN_N_ROW0 PW_ROW0 ENDR_ROW0 RST_ROW0 SEL_ROW0
NO_ME DR_ROW0
ROW3_ROW0 DR_ROW0
DOUT EN_N PW_ROW1 ENDR RST SEL NO_ME DR_ROW1
DOUT_ROW1 EN_N_ROW1 PW_ROW1 ENDR_ROW1 RST_ROW1 SEL_ROW1 ROW3_ROW1 DR_ROW1
DR_ROW1
I_2V5
I_2V5
I_3V3
I_3V3
DOUT EN_N PW_ROW2 ENDR RST SEL NO_ME DR_ROW2
DOUT_ROW2 EN_N_ROW2 PW_ROW2 ENDR_ROW2 RST_ROW2 SEL_ROW2 ROW3_ROW2 DR_ROW2
1
DOUT EN_N PW_ROW3 ENDR RST SEL NO_ME DR_ROW3
DOUT_ROW3 EN_N_ROW3 PW_ROW3 ENDR_ROW3 RST_ROW3 SEL_ROW3 ROW3_ROW3 DR_ROW3
DOUT EN_N PW_ROW4 ENDR RST SEL NO_ME DR_ROW4
DOUT_ROW4 EN_N_ROW4 PW_ROW4 ENDR_ROW4 RST_ROW4 SEL_ROW4 ROW3_ROW4 DR_ROW4
D SPARSIFICATION_INTERFACE DAT CK_SERDES POWERDOWN
DAT CK_SERDES POWERDOWN CLK DIN ENIN_N RSTIN_N
CLK ROW_INTERFACE DOUT EN_N DR
ROW0 ROW1 ROW2 ROW3 PW_ROW 5v 3v3 GND -3v5
DR_ROW2
I_2V5
I_2V5
I_3V3
I_3V3
2
3V3 2V5 GND
DR
ROW0 ROW1 ROW2 ROW3 PW_ROW 5v 3v3 GND -3v5
I_2V5
I_2V5 I_3V3
5v 3v3 GND -3v5
7
I_2V5
I_3V3
I_3V3
HOLE
I4
I22
1
U3 I21 1
I24
U4 I20 HOLE 1 TROU320_600
I25
U5 I19 1
I26
DR_ROW4 I_2V5 I_3V3
TROU320_600
-3V5 2V5
3v3
3V3
GND
GND
B
POR_RESET 5V
U6
I23
1
HOLE
TROU320_600 U7
1
HOLE
TROU320_600 U8
1
HOLE
I_2V5
2v5
5v U2
HOLE
I_3V3
4
I_2V5
POR_RESET
TROU320_600
DR
ROW0 ROW1 ROW2 ROW3 PW_ROW
C
SUPPLY_HSK I9 -3v5
3v3 2v5 GND
TROU320_600
CLK ROW_INTERFACE DOUT EN_N ENDR RST SEL
POR_RESET
3V3 GND
DR_ROW3
I_3V3
3
CLK_ROW 3v3 GND
CLK_ROW POR_RESET
I18
CLK_FPGA DIN_FPGA ENIN_N_FPGA RST_IN_N
I3
CLK ROW_INTERFACE DOUT EN_N ENDR RST SEL
DAT CK_SERDES POWERDOWN
RSTIN_N
I2
ENDR RST SEL
1
I1
DR
ROW0 ROW1 ROW2 ROW3 PW_ROW
2
I27 DR_ROW0
CLK ROW_INTERFACE DOUT EN_N
CLK_ROW DOUT EN_N
5V 3V3 GND -3V5
DR
5v 3v3 GND -3v5
5V 3V3 GND -3V5 D
5
CLK ROW_INTERFACE DOUT EN_N
CLK_ROW DOUT EN_N
E
6
HOLE
TROU320_600 U9
1
A
HOLE
TROU320_600
GND MODIFIE LE 7/7/06 MODIFIE LE 5/4/06
PAR JB PAR JB
REF: I5
merger 6
5
4
3
ETUDE:
PAGE: 1/15
DESSIN:
DATE:
2
Page 37/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
1
MERGER Board, Version 8 ,May 2007 7
3
*
COUT
11
2
AIN
BOUT
14
DATA_OUT-
1
AIN*
AOUT
15
A0 AIN
13 15 16
4
3V3 GND
R4_1 S125MW5%
I60 100
S125MW5%
I61 100
R6_1 S125MW5%
I62 100
S125MW5%
ENABLE* DIN DIN*
DATA_OUT+
6
CIN
DATA_OUT-
5
CIN*
DATA_OUT-
3
DOUT
10
DR
OUT
COUT
11
DR
OUT
BOUT
14
DR
AOUT
15
DR
C BIN
4
BIN*
DATA_OUT+
2
AIN
DATA_OUT-
1
AIN*
3V3
GND 12
3V3 13
I79 10K S125MW5%
I78 10K S125MW5%
I81 10K S125MW5%
OUT
OUT
I80 10K S125MW5%
I34
100N C805S50V10%
GND
GND
U4_1
DS90LV048ATM I15 DS90LV048A
6
CIN
DATA_OUT-
5
CIN*
DATA_OUT-
3
DATA_OUT+
4
BIN*
DATA_OUT+
2
AIN
DATA_OUT-
1
AIN*
R10_1
I66 100
R11_1 S125MW5%
I67 100
3V3
C2 _ 1
S125MW5%
GND
10
DR
OUT
COUT
11
DR
OUT
BOUT
14
DR
OUT
AOUT
15
DR
BIN
GND 12
3V3 13
I85 10K S125MW5%
I84 10K S125MW5%
R2 4 _ 1
DATA_OUT+
DOUT
I83 10K S125MW5%
*
DIN*
R2 2 _ 1
I65 100
*
DIN
R1 9 _ 1
7 8
DATA_OUT-
R9_1 DATA_OUT+ S125MW5%
ENABLE*
*
I64 100
B
ENABLE
R1 6 _ 1
S125MW5%
ENDR 16 GND 9
*
R8_1
*
TYPE=S FMH- 14 0- 0 2- D- L C
D
ENABLE
8
100N C805S50V10%
*
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
DR
DS90LV048ATM DS90LV048A I14
7
DATA_OUT-
R7_1 DATA_OUT+
I63 100
*
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
OUT
I77 10K S125MW5%
GND
C805S50V10% U3_1
ENDR 16 GND 9
R5_1 DATA_OUT+
*
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
100N
GND
I88 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
13
I76 10K S125MW5%
I35
3V3
C1 _ 1
5
14
12
3V3
R2 3 _ 1
12
BIN
GND
3V3
GND
OUT DR
R2 0 _ 1
BIN*
DATA_OUT+
*
BIN
4
R1 7 _ 1
100
*
3
DATA_OUT+
R13_1 DATA_OUT-
J1_1
8
CIN*
10
*
R2 _ 1 *
I59
I32
A
5
DOUT
R2 1 _ 1
C0* B0
ROW+ ROWEN+ ENCOM_DATA+ COM_DATACLK+ CLK-
9 11
B0*
S125MW5% I87 200
10
C0
A0*
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
CIN
*
3 2
GND 41 CLK- 43 CLK+ 45 COM_DATA+ 47 49 COM_DATA- 51 ENEN+ 53 55 ROW+ ROW- 57 ROW0 59 RESET 61 GND 63 65 3V3_ROW 67 69 3V3A_ROW 71 -2VA_ROW 73 75 77 2V5_ROW 79
DIN*
6
R1 8 _ 1
IN
GND
B
8
E
*
D0*
200
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DIN
R1 5 _ 1
CIN
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
7
*
6
S125MW5%
DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT- DATA_OUT+ DATA_OUT-
ENABLE*
C3 _ 1
EN_N IN
DOUT
IN
DS90LV048ATM I13
ENABLE
C4 _ 1
R3 _ 1
*
D0 DIN
*
CLK
S125MW5%
100
*
ENABLE
7
R1_1
C
I58
I12 DS90LV047ATM
ENABLE*
IN
ROW3
I86
GND R12_1 S125MW5%
U1_1 DS90LV047A
GND 8 1
SEL IN
3V3
DS90LV048A
16 9
GND
S125MW5% 10K I30
D
1
2
2
GND
*
IN
3
U5_1
10K I31 S125MW5%
*
IN
ENDR IN
SOT I74
1G
RST IN
U2_1
*
IN
D
*
IN
4
*
IN
BSN20
S
IN
5 RESET
ROW0 ROW1 ROW2 5V 3V3 GND -3V5
IN
E
6
R1 4 _ 1
8
OUT
A
I82 10K S125MW5%
I33
GND
ROW2 ROW1 GND
100N C805S50V10%
GND
MODIFIE LE 7/7/06 MODIFIE LE 5/4/06
PAR JB PAR JB
3V3_ROW
REF:
3V3A_ROW -2VA_ROW
ETUDE:
2V5_ROW
7
row_interface 6
5
4
DESSIN:
3
2
Page 38/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
PAGE: 2/15 DATE:
1
MERGER Board, Version 8 ,May 2007 8
7
6
5
4
3
2
1
E
E RIIPLE
CURRENT
ESR=0.01R
POUR
@ 1MHZ
L=1.5U
-->
ET F=1.4M-->
0.534A
VRIPPLE=0.534*0.01=6
MV
3V3_ROW RIIPLE CURRENT POUR L=1.5U ET F=1.4M--> ESR=0.01R @ 1MHZ --> VRIPPLE=0.534*0.01=6
5V
*
D1_1 V+
OUT
GND
L1_1
2
1.5U
LX
EN
VDD
RSI
2
OUT
GND VIN-
C14_1 10U
C10_1 100N C805S50V10%
GND
EL7536
GND
C15_1 10U
2
*
1 3
Q2_1
R28_1
SOT23 GSD
POR
VIN
EN
VDD
RSI
R40_1
10 9 8 7 6
FB VO
LX
D
GND
IY
100
C17_1
100N 5V
R37_1
R41_1
20.5K
24.9K
PW_ROW
1
2V5_ROW
Q4_1 Q3_1 2N2222A SOT
2
20.5K
SOT23 GSD
C
R38_1
*
1
3
Q1_1 2N2222A SOT
2
20.5K
SGND PGND
G 1 _ S 2 _ D 3B S H 2 0 5
24.9K
G 1 _ S 2 _ D 3B S H 2 0 5
R31_1
1 2 3 4 5
WE-PD4
VOUT=I_MEAS*R_SHUNT*R_LOAD/1000 5V
IN
U11_1
L2_1 I12 1.5U
GND
100
VOUT=I_MEAS*R_SHUNT*R_LOAD/1000
PW_ROW
I_3V3
1N4148_S
IY
R30_1 *
9 8 7 6
POR
VIN
4
10
FB VO
11
C121 0S10V1 5%_X5R
10U
SGND PGND
OUT
C121 0S10V1 5%_X5R
GND
C9_1
GND
WE-PD4
C121 0S10V1 5%_X5R
C12 10S10V15 %_X5R
10U
EL7536
1 2 3 4 5
V+ VIN+
2
*
1N4148_S
GND
D2_1
3
*
VIN-
R36_1 0.1 MSP1
U8_1
I_2V5
3
2
*
3
4
11
150K
*
1
OUT
2
VIN+
*
3
GND 10U C1210S10V15%_X5R
*
5
R35_1 100K
47K *
C16_1
5
10U
C7_1
C
47K
U10_1 SOT23-5
*
D
R33_1
C11_1 C1210S10V15%_X5R
R45_1
R43_1 2V5_ROW
5V
R25_1 0.1 MSP1
MV
*
U6_1 SOT23-5
0.534A
24.9K
R44_1 24.9K
*
*
1.05K
R42_1 1.05K *
10K
R39_1 10K *
R34_1
*
R32_1
*
R29_1
GND
B
B
GND
GND *
R26_1 10K
U9_1 I24 D2PAK LD1086D2T33
UCC284 *
+
VOUTS
R27_1 6.2K
1
VIN VIN VIN
VOUT
5
LD1086
-2VA_ROW
3
5V C12_1 10U
C8_1 4.7U
I23 MSB
OUTPUT
3V3A_ROW
LSB
A
ADJ/GND
VIN
C5_1 4.7U
INPUT
+
-3V5
SD_CT
+
A
2 3 6 7
+
8
GND
1
U7_1 ADJ
C6_1 15N
C13_1 10U
GND GND REF: ETUDE: DESSIN:
row_interface
8
7
6
5
4
3
PAGE: DATE:
2
Page 39/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
3/15
1
MERGER Board, Version 8 ,May 2007
V+
S125MW1%
3
VOUT
I21
C129
C132
100N
100N
NFE61PT472C1H9
1
3
BP3
*
R255 I8 C135 100N
I_5V
0.1 MSP1
C138
47U I13 MV16V_20%
C140
C143
100N
100N
B4 I51
I50
2BORNES
1
2
47K S125MW5%
I_3V3
*
B
GND
C131
10U
I44
C1 2 1 0 S 1 0 V 1 5 %_ X5 R
I47
C1 2 1 0 S 1 0 V 1 5 %_ X5 R
C130
10U
3V3
*
GND
1 2 3 4 5
SGND
FB
PGND
VO
LX
10 9 8 7 6
POR
VIN
EN
VDD
RSI
R245
OUT -3V5
I31 OUT POR_RESET
B
0.47 MSP1
4 *
2
*
3
OUT GND
2
1 D12 1N4148_S I79
I_2V5
*
I40
*
*
C136 I73
1.05K S125MW1%
I37
10U
63.4
R248
24.9K S125MW1%
I34
GND
TRANSISTOR 2369 : A MONTERSMBT2222A
C137 I72 10U
2V5
*
GND
SGND
FB
PGND
VO
LX
*
10K S125MW5%
*
R247
R243
47K S125MW5%
I74 100K S125MW5%
EL7536
WE-PD4 1.5U
R253
I39
R259
U73 I66 IY
L12 I69
C1 2 1 0 S1 0 V 1 5 %_ X 5 R
S125MW1%
A
R256 I65 *
SOT23-5 V+
VIN+ VIN-
10U C1210S10V15%_X5R
U72 I9
5
R251 I11
C141 I68
C1 2 1 0 S1 0 V 1 5 %_ X 5 R
3
SOT23 GSD
G1 _ S 2 _ D3B S H2 0 5
Q22 I33
1
R242
VOUT = ( I_MEAS * R_SHUNT * R_LOAD ) / 5000
IN
R246 I35
20.5K
POR
VIN
EN
VDD
R254 I70
RSI
100K S125MW5% I75
100 S125MW5%
A
*
R257 C139 100N C805S50V10% I71
VOUT=I_MEAS*R_SHUNT*R_LOAD/1000
MODIFIE LE 5/4/06
PAR JB
REF:
supply_hsk
8
7
6
C
63.4
GND
5V
2V5
I_M3V5 R261 I82
GND
10K S125MW5%
C133 100N I43 C805S50V10%
I88 SOT SO2369 Q10
VIN-
OUT
RIIPLE CURRENT POUR L=1.5U ET F=1.4M--> 0.534A ESR=0.01R @ 1MHZ --> VRIPPLE=0.534*0.01=6 MV
100 S125MW5% I41
24.9K S125MW1%
C144 I85
V+
100N
R252
EL7536
WE-PD4 1.5U
R241
I52
MV16V_20%
U71 I38 IY
L11 I42
SOT23-5
VIN+
47U
150K S125MW5%
*
D11 I78 1N4148_S
63.4
R250 I22
( TEXAS )
U75 I83
0.1 MSP1
+
R249 I23
10U C1210S10V15%_X5R
1
63.4
5V
R258 I84
*
*
OUT GND
R260
3
BP4
C142
*
V+
*
VIN-
IN
*
VIN+
C134 I27
SOT23-5
5
3
D
I_5V
VIN-
REF; AMPLI : INA193
NFE61PT472C1H9
1
4
1
OUT GND
I_M3V5
*
R239 I12
V+
BOARD_TEMP
VOUT=I_MEAS*R_SHUNT*R_LOAD/1000
0.1 MSP1
VIN+
VOUT=I_MEAS*R_SHUNT*R_LOAD/1000
2
U69 I10
5V
SOT23-5
3 4
I_2V5
2BORNES
5V
OUT
U74 I7
GND
I_3V3
B3 I76
C
E
OUT
OUT
+
GND
J7 I18 DROIT-2X7 2 1 2 4 3 4 6 5 6 8 7 8 10 9 10 12 11 12 14 13 14
1 3 5 7 9 11 13
*
C805S50V10% I20
GND
D
2 5V_INPUT 1
S125MW1%
RCAMC
I26
B2
3V3 2V5 GND
OUT
I14
2BORNES
BOARD_TEMP
*
1
*
4
*
2
*
5V
2BORNES
1.05K
3
VERS 2EME MERGER I15
DE B1 ALIM I55
R244
LM20B
1.05K
4
*
I24 U70
R240
E
5
5
6
2
7
*
8
5
4
3
ETUDE:
PAGE: 12/15
DESSIN:
DATE:
2
Page 40/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
1
MERGER Board, Version 8 ,May 2007 8
7
6
5
4
3
TSSOP48 DS90CR215
E
D BP1 I18
NFE61PT472C1H9 3V3
T35X28S16V 4.7U
3
DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT
25 23 22 20 19 18 16 15 13 12 10 9 7 6 4 3 1 48 47 45 44
IN
CK_SERDES
26
TXCLKIN
IN
POWERDOWN
27
PWRDWN*
29
PLL_3V3
3V3_PLL C4 I17
C9 I15
C7 I16
1N C805S50V10%
+
C2 I19
1
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
10N C805S50V10%
TXOUT0*
TXIN20 TXIN19
TXOUT0
TXIN18 TXIN17
TXOUT1*
TXIN16 TXIN15
TXOUT1
TXIN14 TXIN13
TXOUT2*
TXIN12 TXIN11
TXOUT2
TXIN10 TXIN9
TXCLKOUT*
TXIN8 TXIN7
TXCLKOUT
TXIN6
1
2
U12 I4 I9
41 LVDS_TX0-
U13
E
VERTICAL_SHIELDED
40 LVDS_TX0+
RJ45
ISO11801 EIA/TIA 568A
1 2 3 4 5 6 7 8
39 LVDS_TX138 LVDS_TX1+ 35 LVDS_TX234 LVDS_TX2+ 33 LVDS_TXCLK-
1
GRE-
2
GRE+
3 ORA4
BLU+
5
BLU-
6
ORA+
7
BRO-
8
BRO+
32 LVDS_TXCLK+
TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0
GND
3V3
5,11 17,24 28,30 31,36 42,46
2,8 14,21 29,37
3V3
C13 I35
1N C805S50V10% GND 3V3
100N C805S50V10%
10N C805S50V10%
10N C805S50V10%
1N C805S50V10%
GND
100N C805S50V10%
C20 I32
C17 I34
C14 I36
D
C19 I31
C16 I33
100N C805S50V10%
GND C
3V3
IN
C1 I26
C3 I25
1N C805S50V10%
3V3
C5 I20
100N C805S50V10%
10N C805S50V10%
GND
IN
*
VERTI CAL _ SHI EL DED
100
RJ45
ORA-
3
BLU+
4
BLU-
5
ORA+ 6 BRO-
7
BRO+ 8
1 2 3 4 5 6 7 8
7
DIN DIN*
LVDS_NRST_RX+
6
CIN
5 4
LVDS_DATA_RX+ 2 LVDS_DATA_RX-
R4
100
1
DOUT
19
10N C805S50V10%
COUT
11
BOUT
14
BIN
CLK OUT RST_IN_N
ENIN_N
BIN*
AIN AOUT
15
*
*
3V3 GND
B
CLK_FPGA OUT CLK_ROW CLK_ROW CLK_ROW CLK_ROW CLK_ROW DIN_FPGA OUT ENIN_N_FPGA OUT
2 3 4 5 6 7 8 9
3V3
20
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
VCC
1V2->3V6
18 17 16 15 14 13 12 11
CLK
DIN ENIN_N
GND 10
DIN
AIN*
12
SOIC
OE*
B TO A A TO B
GND 1
10
CIN*
GND
100
1N C805S50V10%
C
100N C805S50V10%
( LA PLUS FAIBLE VALEUR AU PLUS PRES DE LA PIN )
74LVC245A
GND
ENABLE*
8
LVDS_EN_RX-
R2
FAUT UN GROUPEDE 3 CAPACITéS POUR CHQUE POINT D'ALIMENTATION
ENABLE
LVDS_CLK_RX-
LVDS_EN_RX+ 3
C21 I22
C18 I24
I68 M1
LVDS_CLK_RX+
LVDS_NRST_RX-
C15 I28
GND
DS90LV048A
3V3 16 GND 9
ISO11801 EIA/TIA 568A
GRE+ 2
10N C805S50V10%
DS90LV048ATM
*
A
100
U10 I59 1
3V3 100N C805S50V10%
U11 I1
R3
R1
GRE-
1N C805S50V10%
C10 I23
GND IL
B
C8 I27
C11 I21
OUT
CLK_ROW
A
3V3 13
3V3 C6 I3
GND
100N C805S50V10%
I69 C12
100N C805S50V10%
MODIFIE LE 7/7/06 MODIFIE LE 5/4/06
PAR JB PAR JB
REF:
sparsification_interface
8
7
6
5
4
3
ETUDE:
PAGE: 13/15
DESSIN:
DATE:
2
Page 41/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
1
MERGER Board, Version 8 ,May 2007 8
7
6
5
4 I23
U1 E
U1 I134
IND
D
APA300BG456
WEST STD
OUT
RST_ROW1
OUT
ROW3_ROW1
OUT OUT OUT OUT
DOUT_ROW1 EN_N_ROW1 SEL_ROW1 ENDR_ROW1
IN IN IN IN IN IN IN IN IN IN
C
DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1 DR_ROW1
PW_ROW1OUT I258
I259 I260
B
P1 TEST
P2
TEST P3 TEST
1
1 1
F3 K1 C2 N1 G3 E3 H4 H3 F4 J1 J2 H1 H2 G1 G2 F1 F2 E1 E2 G4 J3 J4 J5 D3 K2 K3 K4 K5 AB1 L2 L3 L4 L5 M3 M4 M5 AB2 AB3 P2 L1 P4
IO_0_WE
IO_41_WE
IO_1_WE
IO_42_WE
IO_2_WE
IO_43_WE
IO_3_WE
IO_44_WE
IO_4_WE
IO_45_WE
IO_5_WE
IO_46_WE
IO_6_WE
IO_47_WE
IO_7_WE
IO_48_WE
IO_8_WE
IO_49_WE
IO_9_WE
IO_50_WE
IO_10_WE
IO_51_WE
IO_11_WE
IO_52_WE
IO_12_WE
IO_53_WE
IO_13_WE
IO_54_WE
IO_14_WE
IO_55_WE
IO_15_WE
IO_56_WE
IO_16_WE
IO_57_WE
IO_17_WE
IO_58_WE
IO_18_WE
IO_59_WE
IO_19_WE
IO_60_WE
IO_20_WE
IO_61_WE
IO_21_WE
IO_62_WE
IO_22_WE
IO_63_WE
IO_23_WE
IO_64_WE
IO_24_WE
IO_65_WE
IO_25_WE
IO_66_WE
IO_26_WE
IO_67_WE
IO_27_WE
IO_68_WE
IO_28_WE
IO_69_WE
IO_29_WE
IO_70_WE
IO_30_WE
IO_71_WE
IO_31_WE
IO_72_WE
IO_32_WE
IO_73_WE
IO_33_WE
IO_74_WE
IO_34_WE
IO_75_WE
IO_35_WE
IO_76_WE
IO_36_WE
IO_77_WE
IO_37_WE
IO_78_WE
IO_38_WE
IO_79_WE
IO_39_WE
IO_80_WE
Y1 P1 T3 R4 P3 R3 U3 V3 T4 W1 W2 V1 V2 U1 U2 T1 T2 R1 R2 V5 AC1 R5 W3 W4 Y2 T5 Y3 Y4 AC3 AA2 AA3 AA4 AC2 U4 U5 AB4 AD2 V4 E4 AA1
RST_ROW0
OUT
ROW3_ROW0
OUT
DOUT_ROW0 EN_N_ROW0 SEL_ROW0 ENDR_ROW0
OUT OUT OUT OUT
DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 DR_ROW0 P4 1 TEST I264
C12 A18 B14 B17 B13 A14 C11 C10 A17 A8 B9 A9 B10 A10 B11 A11 A12 B12 A13 B16 A16 B15 A15 C13 C16 C18 C19 C17 B18 C20 A19 B19
IN IN IN IN IN IN IN IN IN IN
IO_0_NO
IO_32_NO
IO_1_NO
IO_33_NO
IO_2_NO
IO_34_NO
IO_3_NO
IO_35_NO
IO_4_NO
IO_36_NO
IO_5_NO
IO_37_NO
IO_6_NO
IO_38_NO
IO_7_NO
IO_39_NO
IO_8_NO
IO_40_NO
IO_9_NO
IO_41_NO
IO_10_NO
IO_42_NO
IO_11_NO
IO_43_NO
IO_12_NO
IO_44_NO
IO_13_NO
IO_45_NO
IO_14_NO
IO_46_NO
IO_15_NO
IO_47_NO
IO_16_NO
IO_48_NO
IO_17_NO
IO_49_NO
IO_18_NO
IO_50_NO
IO_19_NO
IO_51_NO
IO_20_NO
IO_52_NO
IO_21_NO
IO_53_NO
IO_22_NO
IO_54_NO
IO_23_NO
IO_55_NO
IO_24_NO
IO_56_NO
IO_25_NO
IO_57_NO
IO_26_NO
IO_58_NO
IO_27_NO
IO_59_NO
IO_28_NO
IO_60_NO
IO_29_NO
IO_61_NO
IO_30_NO
IO_62_NO
IO_31_NO
IO_63_NO
TEST
1
TEST
I261 I262
X S23X15_0805
I313
X S23X15_0805
I314
X S23X15_0805
I315
X S23X15_0805
I316
TEST
IN IN
IO_40_WE
ENIN_N
TRIG_RECEIVED
1
R50 I251 10K S125MW5%
*
3V3
R51 I252 10K S125MW5%
*
NO_ME
POR_RESET RSTIN_N
X S23X15_0805
U1 I133
APA300BG456
EAST K26 AB25 AA25 AA26 Y25 Y26 W25 W26 V25 V26 U25 U26 T25 T26 R25 R26 P25 M25 M26 L25 L26 H23 K25 CK_SERDES OUT K23 K24 POWERDOWNOUT J22 1 L22 TEST E23 P9 K22 I265 L24 P24 L23 R22 M24 R24 M23 P22 P23 DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT
R5 R6
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
IO_0_ES
IO_38_ES
IO_1_ES
IO_39_ES
IO_2_ES
IO_40_ES
IO_3_ES
IO_41_ES
IO_4_ES
IO_42_ES
IO_5_ES
IO_43_ES
IO_6_ES
IO_44_ES
IO_7_ES
IO_45_ES
IO_8_ES
IO_46_ES
IO_9_ES
IO_47_ES
IO_10_ES
IO_48_ES
IO_11_ES
IO_49_ES
IO_12_ES
IO_50_ES
IO_13_ES
IO_51_ES
IO_14_ES
IO_52_ES
IO_15_ES
IO_53_ES
IO_16_ES
IO_54_ES
IO_17_ES
IO_55_ES
IO_18_ES
IO_56_ES
IO_19_ES
IO_57_ES
IO_20_ES
IO_58_ES
IO_21_ES
IO_59_ES
IO_22_ES
IO_60_ES
IO_23_ES
IO_61_ES
IO_24_ES
IO_62_ES
IO_25_ES
IO_63_ES
IO_26_ES
IO_64_ES
IO_27_ES
IO_65_ES
IO_28_ES
IO_66_ES
IO_29_ES
IO_67_ES
IO_30_ES
IO_68_ES
IO_31_ES
IO_69_ES
IO_32_ES
IO_70_ES
IO_33_ES
IO_71_ES
IO_34_ES
IO_72_ES
IO_35_ES
IO_73_ES
IO_36_ES
IO_74_ES
IO_37_ES
IO_75_ES
D24 T22 J24 R23 G24 H24 J23 F24 T23 E25 E26 F25 F26 G25 G26 H25 H26 J25 J26 V24 T24 E24 W23 W24 U22 AB23 Y23 Y24 U23 AA23 U24 AA24 V22 AC26 V23 F23 G23 AB24
OUT
RST_ROW4
OUT ROW3_ROW4 OUT OUT OUT OUT
DOUT_ROW4 EN_N_ROW4 SEL_ROW4 ENDR_ROW4
IN IN IN IN IN IN IN IN IN IN
DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4 DR_ROW4
D
OUT PW_ROW4
1 1 1 1
I268
P12
TEST
P13 I269
TEST
P14 I270
TEST
C
P15 I271
TEST
R7 R8 GND U17 CMS MSOP8 I331
IND STD
AD5320
SOUTH AB10 AB8 AB9 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AD7 AD8 AD9 AD10
R9
I317 *
IO_0_SO
IO_31_SO
IO_1_SO
IO_32_SO
IO_2_SO
IO_33_SO
IO_3_SO
IO_34_SO
IO_4_SO
IO_35_SO
IO_5_SO
IO_36_SO
IO_6_SO
IO_37_SO
IO_7_SO
IO_38_SO
IO_8_SO
IO_39_SO
IO_9_SO
IO_40_SO
IO_10_SO
IO_41_SO
IO_11_SO
IO_42_SO
IO_12_SO
IO_43_SO
IO_13_SO
IO_44_SO
IO_14_SO
IO_45_SO
IO_15_SO
IO_46_SO
IO_16_SO
IO_47_SO
IO_17_SO
IO_48_SO
IO_18_SO
IO_49_SO
IO_19_SO
IO_50_SO
IO_20_SO
IO_51_SO
IO_21_SO
IO_52_SO
IO_22_SO
IO_53_SO
IO_23_SO
IO_54_SO
IO_24_SO
IO_55_SO
IO_25_SO
IO_56_SO
IO_26_SO
IO_57_SO
IO_27_SO
IO_58_SO
IO_28_SO
IO_59_SO
IO_29_SO
IO_60_SO
3V3
GND AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17
GND
1 5 6 7 8
VDD SYNC* SCLK DIN GND
VOUT
U16 CMS SOIC16 I319 ADG713
1
3
R10 1K S125MW5% I321 *
*
15 11
9
4
*
I324 S23X15_0805 0 R12
10 6
8
7
3V3 13 GND 5
3V3 GND
C22 C805S50V10% I322 10N
R11 0 S23X15_0805 I325
2 GND 14
16
U18 I327 TROU320_600 U19 I328 TROU320_600 U20 I329 TROU320_600 U15 I330 TROU320_600
HOLE
HOLE
HOLE
U14 DIP 246 I332
GND
TI_BOURNS
6 4
3 2 1 D1 I326 ROUGE
GND
A
MODIFIE LE 7/7/06 MODIFIE LE 5/4/06
PAR JB PAR JB
IO_30_SO
REF:
ONLY ONE RESISTOR SHOULDBE MOUNTED 6
merger_fpga
5
4
3
B
HOLE
GND
EXTENSION FUTURE POUR LA COMMANDEDE LED
GND
7
E
IND STD
*
P6
P7 I263 DIN
U1 I115
OUT PW_ROW3
*
APA300BG456
1
1
OUT RST_ROW3
*
P5
TEST
8
C14 B8 C15 C7 C8 C9 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19
OUT PW_ROW0
1
2
IND
STD
*
P8 I135
A
RST_ROW2 OUT DR_ROW3 IN ROW3_ROW2 OUT DR_ROW3 IN DOUT_ROW2 OUT EN_N_ROW2 OUT SEL_ROW2 OUT ENDR_ROW2 OUT DR_ROW3 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW2 IN DR_ROW3 IN DR_ROW3 IN DR_ROW3 IN DR_ROW3 IN OUT PW_ROW2 ENDR_ROW3 OUT OUT SEL_ROW3 EN_N_ROW3 OUT DOUT_ROW3 OUT DR_ROW3 IN ROW3_ROW3 OUT DR_ROW3 IN DR_ROW3 IN
3
APA300BG456
NORTH SIDE
ETUDE:
PAGE: 14/15
DESSIN:
DATE:
2
Page 42/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
1
MERGER Board, Version 8 ,May 2007 8
7
6
5
4
3
1
2
E
E
3V3 *
U1
*
3V3
*
R56 200
3V3
GND
GND
N4 P5 P26 N22
R57
20.5K
R54 R = 1K
TRST
I/O/GL2_CO
2V5A_1
I/O/GL4_CO
2V5A_2
NFE61PT472C1H9 1 BP2 3 2V5
N5 N24
I/O/GL3_CO I/O/GLMX1_CO I/O/GLMX2_CO
3V3
PPECL1/INPUT_CO
0 R52
C
C48
4.7U
100N
+
C45
C49
+
VPP VPN
4.7U
C50 100N
GND
CAPAS PROCHESDU FPGA
C58
10N
10N
R58
NPECL2_CO TRST_CO TCK_CO
D
GND
PPECL2/INPUT_CO
TDO_CO
AC22
TMS_CO
20.5K TDO
TDI_CO
AC24
RCK_CO
AD22 AE23
VPP_CO
A1 A2 A25 A26 B1 B2 B25 B26 C1 C3 C24 D4 D23
C55
NPECL1_CO
*
AE24 AD21 AC21 AF23
TRST TCK TMS TDI RCK
2V5
*
N2 N25
*
VPP VPN TCK TDI TDO TMS RCK
X
2 4 6 8 10 12 14 16 18 20 22 24 26
2 4 6 8 10 12 14 16 18 20 22 24 26
POR_RESET IN RSTIN_N IN
I/O/GL1_CO
*
GND
D
APA300BG456
M1 M2 M22 N23
CLK IN
R53 0
FSTH-113-XX-L-DV-A 1 3 5 7 9 11 13 15 17 19 21 23 25
IND STD
I7
CORE
J2 I8
1 3 5 7 9 11 13 15 17 19 21 23 25
R55 200
VPN_CO VDDP_1_CO
VDDP_14_CO
VDDP_2_CO
VDDP_15_CO
VDDP_3_CO
VDDP_16_CO
VDDP_4_CO
VDDP_17_CO
VDDP_5_CO
VDDP_18_CO
VDDP_6_CO
VDDP_19_CO
VDDP_7_CO
VDDP_20_CO
VDDP_8_CO VDDP_9_CO
VDDP_21_CO VDDP_22_CO
VDDP_10_CO
VDDP_23_CO
VDDP_11_CO
VDDP_24_CO
VDDP_12_CO
VDDP_25_CO
AC4 AC23 AD3 AD24 AE1 AE2 AE25 AE26 AF1 AF2 AF25 AF26
C
VDDP_13_CO
3V3
B
B
IN
IN
3V3
GND
IN
C39
C41
C43
C46
100N
100N
100N
100N
GND
C53
C56
C59
100N
C51
100N
100N
100N
GND
3V3 A
2V5
2V5 C40
C42
C44
C47
C52
C54
C57
C60
10N
10N
10N
10N
10N
10N
10N
10N
A
GND 2 DANS CHAQUECOIN 1 INTERIEURE + 1 EXTERIEURE
2 DANS CHAQUECOIN 1 INTERIEURE + 1 EXTERIEURE REF: ETUDE: DESSIN:
merger_fpga 8
7
6
5
4
3
2
Page 43/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
PAGE: DATE:
15/15
1
MERGER Board, Version 8 ,May 2007 Annex 13 : Board implantation components ( top side )
J7 C49
C4 5
C5 0 C4 8
1
25
B2 B4 R2 50 R24 9 R2 52 C1 34 R2 41 D11 U69
R 25 9
R23 9
L1 2
U 72
R2 53 D12
R 53
R5 4 R5 2
C1 3 8 C1 44
U 9_1
R2 46
R2 47
C1 4 2
R25 8
Q 21
U7 1
R 248 Q 22
L1 1
C1 33 R2 45
C1 31 C1 30
C13 6
C13 7
R25 7
C13 9 R25 4
R25 6 U7 3
R25 1
C1 2 R5 6 R5 5
R 17_1
R 14_1
R 20_1
R 23_1 R 21_1
R 15_1
R 18_1
R 24_1 R 22_1 R 19_1 R 16_1 R 3_1 R 2_1
R 1_1
D 2_1
U 10_ 1
D 1_1
U 6_1
R 17_2
R 14_2
R 20_2
R 23_2 R 21_2
R 15_2
R 18_2
R 24_2 R 22_2 R 19_2 R 16_2
R 2_2
R 3_2 R 1_2
D 2_2
U 10_ 2
D 1_2 U 6_2
R 17_3 R 20_3 R 14_3 R 23_3 R 21_3 R 18_3 R 15_3 R 24_3 R 22_3
R 16_3
R 19_3
R 3_3 R 1_3 R 2_3
D 2_3
U 10_ 3
D 1_3
U 6_3
L2_1
R27 _1
C 8_1
R8 _1
R1 0_1
R9_ 1
2
C 5_1
U 7_1
C6_ 1
R4 _1
R13 _1
R5_ 1 R6 _1 R7_ 1
C 8_2
C11 _2
79
2
C 5_2
U 7_2
R8 _2
R27 _3
C 6_3
C 12_ 3
C 5_3
U 7_3
C 8_3
R 35_2
R11 _2
R1 0_2
R9_ 2
79
C11 _1
C 6_2
C 12_ 2
R27 _2
R1 2_2
R4 _2
R13 _2
R5_ 2 R6 _2 R7_ 2
U8 _2
C 17 _2 L 1_2
C 13_3
2
79
C11 _3
2
C 5_4
U 7_4
C 8_4
R 35_3
R11 _3
R1 0_3
R9_ 3
R8 _3
R7_ 3
R6 _3
R5_ 3
R4 _3
R13 _3
R1 2_3
R 26_ 3
L2_3
U8 _3
C 17 _3 L 1_3
R 35_1
R11 _1
U8 _1
C 17 _1 L 1_1
L2_2
R 26_ 2
C 13_2
R1 2_1
R 26_ 1
C 13_1
C12 _1
C15 _1
C14 _1
C 7_1
C 9_1
R 36_1
R2 5_1
C15 _2
C14 _2 R 36_2 C 9_2
C 7_2 R2 5_2
C15 _3
C14 _3 R 36_3 C 9_3
C 7_3 R2 5_3
C 6_4
C 12_ 4
R27 _4
R 26_ 4
R8 _4 R9_ 4
R17_5 R20_5 R14_5 R23_5 R21_5 R18_5 R15_5 R24_5 R22_5 R19_5 R16_5 R3_5 R1_5 R2_5
D2_5 U10_5
D1_5 U6_5
C15_5
C14_5 R36_5 C9_5
C7_5 R25_5
C12_5
C6_5 R27_5
C8_5
C5_5
U7_5
2
79 C11_5 R35_5
R11_5
R10_5
R9_5
R8_5
R7_5
R6_5
R5_5
R4_5
R13_5
R12_5
R26_5
C13_5
L2_5
U8_5
C17_5 L1_5
Page 44/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
U 5_1 U 3_1 C 13_4
R1 2_4
R4 _4
R13 _4
R5_ 4 R6 _4 R7_ 4
R1 0_4 R11 _4
79
C11 _4
R 35_4
C 8_5
2
U9_5
C1 3 5 R2 6 0 R 24 4 R2 40
2
26
R 17_4 R 20_4 R 14_4 R 23_4 R 21_4
L2_4
U8 _4
C 17 _4 L 1_4
C 6_5
C 12_ 5
R27 _5
R8 _5
R1 0_5
R9_ 5
C 5_5
U 7_5
R1 2_5
R4 _5
R13 _5
R6 _5
R5_ 5
R7_ 5
R11 _5
79
J1_5
R2 4 2
U 4_1 C 13_5
R 26_ 5
L2_5
C11 _5
R 35_5
C16_5
R 44_1 U8 _5
C 17 _5 L 1_5
R43_5 R45_5
U5_5 U3_5 U4_5 U1_5 U11_5 R40_5 R30_5
R 18_4 R 15_4 R 24_4 R 22_4 R 19_4 R 16_4
C15 _4
C14 _4
C 7_4
C 9_4
R 36_4
R2 5_4
C15 _5
C14 _5 R 36_5 C 9_5
C 7_5 R2 5_5
R44_5 R34_5 R33_5
R 3_4 R 1_4 R 2_4
D 2_4
U 10_ 4
D 1_4
U 6_4
R 17_5 R 20_5
R 23_5
R 14_5
R 21_5 R 18_5 R 15_5 R 24_5 R 22_5
R 16_5
R 19_5
R 3_5 R 1_5 R 2_5
D 2_5
U 10_ 5
D 1_5 U 6_5
C10_5
B3 B1
R 45_1 R 43_1
U 1_1 U 11_1 R 40_1 R 30_1
U7 4 U7 5
J1_1 J1_2 J1_3 J1_4 J1_5
C 16_1 R 33_1 C 16_2
U 5_2
R 34_1 R 44_2
U 3_2 U 4_2 U 1_2 U 11_2 R 40_2 R 30_2
R 45_2
C 10_1 C 10_2
R 43_2 R 45_3
U 5_3
R 34_2 R 44_3
U 3_3 U 4_3 U 1_3 U 11_3 R 40_3 R 30_3
R 33_2 C 16_3 R 33_3 C 16_4
C 10_3
R 43_3 R 45_4
U 5_4
R 34_3 R 44_4
U 3_4 U 4_4 U 1_4 U 11_4 R 40_4 R 30_4 U 5_5 U 3_5 U 4_5
R 43_4 R 45_5 R 43_5
U 1_5 U 11_5
R 34_4 R 44_5 R 34_5
R 40_5 R 30_5
R 33_4 C 16_5 R 33_5
C 10_4 C 10_5
C1 4 0 C1 4 3 R1 R4
R2 6 1 C1 2 9 C1 4 1
U 9_2 U 9_3 U 9_4 U 9_5
R2 M1
C1 3 2 P5 P6
R2 5 5 R3 P1 1 P1 0
U1 0 P4
R 243
P9
P3 P1 P2
U12 U12 U13
BP3
B3
P1 5 P1 2
V7 0 BP4 P1 4 P1 3
B1
P7 BP2 P8 J2
U1 1
MERGER Board, Version 8 ,May 2007
J7 C49
C4 5
C5 0 C4 8
1
25
R5 2
R5 4
R 53
U 72
R2 53 D12
L12
R 25 9
R239
U69
R2 41 D11
C1 34
R2 52
R249
R250
R 24 4 R2 40
2
26
C144
U 9_1
R2 46
R247
C14 2
R258
Q 21
U7 1
R 248 Q 22
L1 1
C1 33 R2 45
C1 31 C1 30
R256
C137
C139 R254 R257
C136
R 17_1 R 20_1 R 14_1 R 23_1 R 21_1 R 18_1 R 15_1 R 24_1 R 22_1 R 19_1 R 16_1 R 3_1 R 1_1 R 2_1
D 2_1
U 10_ 1
D 1_1
U 6_1
R 17_2 R 20_2 R 14_2 R 23_2 R 21_2
R 15_2
R 18_2
R 24_2 R 22_2 R 19_2 R 16_2 R 3_2 R 1_2 R 2_2
D 2_2
D 1_2
U 10_ 2
U 6_2
R 17_3 R 20_3 R 14_3
R 21_3
R 23_3
C 9_2
L2_1
R27 _1
C 8_1
C 17 _2 L 1_2
R6 _1
R8 _1
R1 0_1
2
C 5_1
U 7_1
C6_ 1
R4 _1
R13 _1
R5_ 1
R7_ 1
R9_ 1
79
C11 _1
C 6_2
C 12_ 2
R27 _2
C 8_2
2
C 5_2
U 7_2
R1 2_2 R13 _2 R4 _2
R6 _2
R5_ 2
R7_ 2 R8 _2
R1 0_2
R9_ 2
79
C11 _2
C11 _3
79
2
C 5_3
U 7_3
C 8_3
R 35_2
R11 _2
U8 _2
C 6_3
C 12_ 3
R27 _3
R 26 _4
R27 _4
C 6_4
C 12_ 4
R6 _4
R8 _4
R1 0_4
2
C 5_4
U 7_4
C 8_4
R 35_3
R11 _3
R1 0_3
R9_ 3
R8 _3
R7_ 3
R6 _3
R5_ 3
R4 _3
R13 _3
R1 2_3
R 26 _3
C 13_3
L2_3
U8 _3
C 17 _3 L 1_3
R 35_1
R11 _1
U8 _1
C 17 _1 L 1_1
L2_2
R 26 _2
C 13_2
R1 2_1
R 26 _1
C 13_1
C12 _1
C15 _1
C14 _1 R 36_1 C 9_1
C 7_1 R2 5_1
C15 _2
C14 _2 R 36_2
C 7_2 R2 5_2
C14 _3
C15 _3
R 36_3 C 9_3
C 7_3 R2 5_3
U 5_1 C 13_4
R1 2_4
R4 _4
R13 _4
R5_ 4
R7_ 4
R9_ 4
R11 _4
79
C11 _4
R 35_4
C 8_5
2
C 5_5
U 7_5
R6 _5
R8 _5
R1 0_5
R17 _4 R20 _4 R14 _4 R23 _4 R21 _4 R18 _4 R15 _4 R24 _4 R22 _4 R19 _4 R16 _4 R3_ 4 R1_ 4 R2_ 4
D2_ 4 U10 _4
D1_ 4 U6_ 4
C15_ 4
C14_ 4 R36_ 4 C9_ 4
C7_ 4 R25_ 4
C12_4
C6_4 R 27_4
C8 _4
C5 _4
U7 _4
2
79 C11_4 R35 _4
R 11 _4
R10_ 4
R 9_4
R8_4
R 7_4
R6_4
R 5_4
R4_4
R 13_4
R12_ 4
R2 6_4
C13_4
L2_4
C17_ 4 L1_4
U 8_4
Page 45/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
C13 8 U73
R251
C12 R56 R55 R 18_3 R 15_3
R 24_3 R 22_3 R 19_3 R 16_3
R 1_3
R 3_3
R 2_3
D 2_3
U 10_ 3
D 1_3 U 6_3
R 14_4
L2_4
U8 _4
C 17 _4 L 1_4
C 6_5
C 12_ 5
R27 _5
R1 2_5
R4 _5
R13 _5
R5_ 5
R7_ 5
R9_ 5
R11 _5
79
J1_4
C 16_1
U 3_1 U 4_1 C 13_5
R 26 _5
L2_5
C11 _5
R45_4 R43_4
U5_4 U3_4 U4_4 U1_4 U11_4
U9_4
R 45_1 R 35_5
R40_4 R30_4
R 44_1 U8 _5
C 17 _5 L 1_5
C16_4 R33_4
R 17_4 R 20_4
C15 _4
C14 _4 R 36_4 C 9_4
C 7_4 R2 5_4
C15 _5
C14 _5 R 36_5 C 9_5
C 7_5 R2 5_5
R44_4 R34_4
R 23_4 R 21_4 R 18_4 R 15_4
R 24_4 R 22_4
R 16_4
R 19_4
R 3_4 R 1_4 R 2_4
D 2_4
U 10_ 4
D 1_4 U 6_4
R 14_5
R 17_5 R 20_5
R 23_5 R 21_5 R 18_5 R 15_5
R 22_5
R 24_5
R 19_5 R 16_5 R 3_5 R 1_5 R 2_5
D 2_5
U 10_ 5
D 1_5 U 6_5
C10_4
U12 U13
R24 2
J1_1 J1_2 J1_3 J1_4 J1_5
C 10_1
U 1_1 U 11_1 R 40_1 R 30_1 U 5_2
R 34_1 R 33_1 C 16_2
U7 5 R 243
R 43_1 R 43_2 R 45_2
U 3_2 U 4_2 U 1_2 U 11_2 R 40_2 R 30_2 U 5_3
R 44_2 R 44_3
U 3_3 U 4_3
R 34_2 R 33_2 C 16_3
C 10_2 C 10_3
U 1_3 U 11_3 R 40_3 U 5_4
R 34_3 R 33_3 R 44_4
U 3_4 U 4_4 U 1_4 U 11_4
R 43_3 R 45_3 R 45_4 R 43_4
R 30_3 R 40_4 R 30_4 U 5_5
C 16_4 C 16_5
U 3_5 U 4_5 U 1_5 U 11_5 R 40_5 R 30_5
R 34_4 R 33_4 R 44_5 R 34_5 R 33_5
R 43_5 R 45_5
C 10_4 C 10_5
C1 40 C1 43 R1 R4
U 9_2 U 9_3 U 9_4 U 9_5
R2 M1
U7 4 P9
B2 B4 BP3 V7 0 BP4
C13 5 R26 0 C1 29 C1 41 P3
C1 32 P5 P6
R25 5 R3 P1 1 P10
U10 P4
R2 61
U13
P1 5 P12
P2 P1
U12 U12
P1 4 P1 3
B3 B1
P7 BP2 P8 J2
U11
MERGER Board, Version 8 ,May 2007
C 49
C4 5
C5 0 C4 8
R2 6 1 R5 2
R5 4
R 53
U7 2
R25 3 D 12
L12
R2 59
R23 9
U 69
R2 41 D11
C1 34
R25 2
R 24 9
R2 50
R2 44 R2 40
2
26
C1 44
U 9_1
R24 6
R2 47
C1 42
R25 8
Q 21
U7 1
R2 48 Q 22
L1 1
C13 3 R24 5
C13 1 C13 0
R2 5 6
C13 9 R25 4 R25 7 C1 3 7 C1 3 6
R1 7_1 R2 0_1
R2 3_1
R1 4_1
R2 1_1
R1 5_1
R1 8_1
R2 2_1
R2 4_1
C 12 _1
C1 3_1
R 27 _1
C 8_1
R4_ 1
R6_ 1
R8_ 1
R10 _1
2
C5 _1
U 7_1
C 6_ 1
R12 _1
R 26_ 1
R 13 _1
R 5_ 1
R 7_ 1
R 9_ 1
R 11_ 1
R17_3 R20_3 R14_3 R23_3 R21_3 R18_3 R15_3 R24_3 R22_3 R19_3 R16_3 R3_3 R1_3 R2_3
D2_3 U10_3
D1_3 U6_3
C15_3
C14_3 R36_3 C9_3
C7_3 R25_3
C13_3
C12_3
C6_3 R27_3
C8_3
2
C5_3
U7_3
R12_3
79 C11_3 R35_3
R11_3
R10_3
R9_3
R8_3
R7_3
R6_3
R5_3
R4_3
R13_3
R26_3
L2_3
C17_3 L1_3
U8_3
Page 46/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
R1 9_1
79
C11 _1
U 7_2
C8 _2
R3 5_1
C 12_ 2
C6 _2 R 27 _2
2
C5 _2
79
C12 R56 R55
U9_3
R1 6_1
C 15 _1 L 2_1
U8_ 1
C 17_ 1 L1 _1
C1 3_2
C 17_ 2
R 11_ 2
R10 _2
R 9_ 2
R8_ 2
R 7_ 2
R6_ 2
R 5_ 2
R4_ 2
R 13 _2
R12 _2
R 26_ 2
L 2_2
C11 _2
R3 5_2
C8 _3
C5 _3
U 7_3
M1
R2 _1
C 9_2 L1 _2
U8_ 2
C 12_ 3
C6 _3 R 27 _3
C49
R53
R54 R52
P1 P2 P3
R3 _1 R1 _1
C 14 _1 R3 6_1 C 9_1
C 7_1 R2 5_1
C 15 _2
C 14 _2 R3 6_2
C 7_2 R2 5_2
C1 3_3
2
79
C11 _3
R3 5_3
R 11_ 3
R10 _3
R 9_ 3
R8_ 3
R 7_ 3
R6_ 3
R 5_ 3
R4_ 3
R 13 _3
R12 _3
R 26_ 3
L 2_3
U8_ 3
C 17_ 3 L1 _3
C50 C48 C45
2
26
P14 P13
D2 _1
U 10_1
D1 _1
U6 _1
R1 7_2 R2 0_2
R2 3_2
R1 4_2
R2 1_2 R1 8_2 R1 5_2
R2 4_2 R2 2_2
R1 6_2
R1 9_2
R3 _2 R1 _2 R2 _2
D2 _2
U 10_2
D1 _2 U6 _2
R2 0_3
R1 7_3
R1 4_3
R1 8_3
R2 3_3 R2 1_3
R1 5_3
C 15 _3
C 14 _3 R3 6_3 C 9_3
C 7_3 R2 5_3
C8 _4
C5 _4
U 7_4
2
1
25
P6 P5
C1 3 8 U7 3
R25 1
C1 2 R5 6 R5 5
R2 4_3 R2 2_3 R1 9_3 R1 6_3 R3 _3 R1 _3 R2 _3
D2 _3
U 10_3
D1 _3 U6 _3
C6 _4
C 12_ 4
R 27 _4
R 26_ 4 R12 _4
R4_ 4
R 13 _4
R 5_ 4 R6_ 4 R 7_ 4 R8_ 4
R10 _4
R 9_ 4
R 11_ 4
79
C11 _4
R3 5_4
C8 _5
U 7_5
P4
U 5_1 U 3_1 C1 3_4
L 2_4
C 17_ 4 L1 _4
U8_ 4
C6 _5
C 12_ 5
R 27 _5
2
C5 _5
79
J1_3
U7 5
U 4_1 U 1_1 U 11_1 C1 3_5
R 11_ 5
R10 _5
R 9_ 5
R8_ 5
R 7_ 5
R6_ 5
R 5_ 5
R4_ 5
R 13 _5
R12 _5
R 26_ 5
L 2_5
C11 _5
C16_3
R 45_1 R 43_1 R3 5_5
R43_3 R45_3
U5_3 U3_3 U4_3 U1_3 U11_3 R40_3 R30_3
C 16_1 U8_ 5
C 17_ 5
P9
R 40_1 R 30_1 L1 _5
P15 P12
1
25
R1 4_4
R1 7_4 R2 0_4
R2 3_4 R2 1_4
R1 5_4
R1 8_4
R2 2_4
C 15 _4
C 14 _4 R3 6_4 C 9_4
C 7_4 R2 5_4
C 15 _5
C 14 _5
C 7_5
C 9_5
R3 6_5
R2 5_5
C10_3
R2 4_4
R1 9_4 R1 6_4 R3 _4
R2 _4
R1 _4
D2 _4
U 10_4
D1 _4 U6 _4
R1 7_5 R2 0_5 R1 4_5 R2 3_5 R2 1_5
R1 5_5
R1 8_5
R2 4_5 R2 2_5 R1 9_5 R1 6_5
R1 _5
R3 _5 R2 _5
D2 _5
U 10_5
D1 _5 U6 _5
R44_3 R34_3 R33_3
P11 P10
P7 BP2 P8 J2
U 9_2
R 44_1 R 34_1 R 33_1 R 44_2
R2 4 2
B2 B4 BP3 BP4
C1 3 5 R2 6 0 C1 2 9
J1_1 J1_2 J1_3 J1_4 J1_5
C 10_1 C 10_2
R 43_2 R 45_2 R 43_3 R 45_3 R 45_4 R 43_4
C 10_3
C 16_2 C 16_3 C 16_4 C 16_5
C 10_4 C 10_5
R 43_5 R 45_5
U 5_2 U 3_2 U 4_2
C1 4 0 C1 4 3 R1 R4
U 1_2 U 11_2 U 5_3 U 3_3 U 4_3
R 34_2 R 33_2 R 44_3 R 34_3 R 33_3 R 44_4 R 34_4 R 33_4 R 44_5 R 34_5 R 33_5
R 40_2 R 30_2 R 40_3 R 30_3
U 9_3 U 9_4
U 1_3 U 11_3 U 5_4 U 3_4 U 4_4 U 1_4 U 11_4 U 5_5 U 3_5 U 4_5 U 1_5 U 11_5
U 9_5
R 40_4 R 30_4 R 40_5 R 30_5
R2 M1
U7 4 R 243
P9
C1 3 2 P5 P6
R2 5 5 R3 P1 1 P1 0
U1 0 P4
C1 4 1 P3 P2 P1
U12 U12 U13
P1 4 P1 3
B3
P7 BP2 P8 P1 5 P1 2
V7 0
B1
J7 J2
U1 1
MERGER Board, Version 8 ,May 2007
J7 C49
C4 5
C5 0 C4 8
1
25
R2 5 0 R24 9 R2 52 C13 4
U69
R24 1 D1 1
R25 9
R2 39
C1 4 4 R2 58
U 9_1
R2 46
R2 4 7
C14 2
Q2 1
U 71
R 248 Q2 2
L 11
C1 33 R2 45
C1 31 C1 30
C13 6
C13 7
R2 57
C1 39 R2 54
R25 6 U73
R2 51
C12 R56 R55
R 20_ 1
R 17_ 1
R 14_ 1
R 21_ 1
R 23_ 1
R 18_ 1 R 15_ 1
R 24_ 1 R 22_ 1 R 19_ 1 R 16_ 1
L2_1
C 13_1
C1 2_1
C1 5_1
C 9_1
C 9_3
R2 7_1
C 8_1
U 7_1
C6 _1
2
C 5_1
79
C 11_1
C 5_2
U 7_ 2
C 8_2
R 35_1
R11 _1
R 10_1
R9 _1
R 8_1
R7 _1
R 6_1
R5 _1
R 4_1
R1 3_1
R 12_1
R26 _1
C17 _1
U 8_1
C12 _2
C 6_2 R2 7_2
2
79
C 11_2
C 8_3
R 35_2
R11 _2
R 10_2
R9 _2
R 8_2
R7 _2
R 6_2
R5 _2
R 4_2
R1 3_2
R 12_2
R26 _2
L1_1
C 13_2
L2_2
U 8_2
C17 _2
C 6_3
C12 _3
R2 7_3
2
C 5_3
U 7_ 3
R 12_3
R 4_3
R1 3_3
R5 _3 R 6_3
79
C 11_3
C 8_4
R 35_3
R11 _3
R 10_3
R9 _3
R 8_3
R7 _3
U 8_3
C17 _3
R26 _3
L1_2
C 13_3
L2_3
L1_3
C 6_4
C12 _4
R2 7_4
2
C 5_4
U 7_ 4
R 12_4
R26 _4
R 4_4
R1 3_4
R 6_4
R5 _4
R7 _4 R 8_4
R 10_4
R9 _4
R11 _4
79
C 11_4
R2 44 R240 R250 R249 R252 C134
U69
R241 D11
R239
R259
L12 R253 D12 U72
C144 R258
R24 6
R247
C14 2
Q 21
U 71
R2 48 Q 22
L11
C1 33 R2 45
C1 31 C1 30
C136
C137
R257
C139 R254
R256 U7 3
R2 51
R17 _1 R20 _1 R14 _1 R23 _1 R21 _1 R18 _1 R15 _1 R24 _1 R22 _1 R19 _1 R16 _1 R3_ 1 R1_ 1 R2_ 1
D2_ 1
U1 0_ 1
D1_ 1 U6_ 1
R17 _2 R20 _2 R14 _2 R23 _2 R21 _2 R18 _2 R15 _2 R24 _2 R22 _2 R19 _2 R16 _2 R3_ 2 R1_ 2 R2_ 2
D2_ 2
U1 0_ 2
D1_ 2 U6_ 2
L2 _1
C8 _1
R27 _1
2
C5 _1
U7_ 1
C 6_ 1
R4 _1
R13 _1
R6 _1
R5_ 1
R8 _1
R7_ 1
R1 0_ 1
R9_ 1
79
C11 _1
C 6_ 2
C1 2_ 2
R27 _2
C8 _2
2
C5 _2
U7 _2
R1 2_ 2
R4 _2
R13 _2
R6 _2
R5_ 2
R8 _2
R7_ 2
R1 0_ 2
R9_ 2
79 C11 _2
R3 5_ 2
R11_ 2
U8 _2
C17 _2 L1_ 2
R3 5_ 1
R11_ 1
U8 _1
C17 _1 L1_ 1
L2 _2
R 26 _2
C13 _2
R1 2_ 1
R 26 _1
C13 _1
C1 2_ 1
C 15_ 1
C 14_ 1 R3 6_ 1 C9_ 1
C7_ 1 R25 _1
C 15_ 2
C 14_ 2
C9_ 2
R3 6_ 2
C7_ 2 R25 _2
Page 47/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
R 1_1
C1 4_1 R 36_1
C 7_1 R 25_1
C1 5_2
C1 4_2 R 36_2 C 9_2
C 7_2 R 25_2
C1 5_3
C1 4_3 R 36_3
C 7_3 R 25_3
C 13_4
L2_4
C17 _4 L1_4 R 35_4
C 8_5
2
J7
R 3_1
R 2_1
D 2_1
U 10_ 1
D 1_1 U 6_1
R 17_ 2 R 20_ 2
R 23_ 2
R 14_ 2
R 21_ 2 R 18_ 2 R 15_ 2 R 24_ 2 R 22_ 2 R 19_ 2 R 16_ 2 R 3_2 R 1_2 R 2_2
D 2_2
U 10_ 2
D 1_2
U 6_2
R 17_ 3 R 20_ 3
R 23_ 3
R 14_ 3
R 21_ 3 R 18_ 3 R 15_ 3
R 24_ 3 R 22_ 3 R 19_ 3 R 16_ 3 R 3_3 R 1_3 R 2_3
D 2_3
U 10_ 3
D 1_3 U 6_3
C 9_4
U 8_4
C 6_5
C12 _5
R2 7_5
R 8_5
R 10_5
R9 _5
R11 _5
C 5_5
U 7_ 5
R 4_5
R1 3_5
R 12_5
R26 _5
R5 _5 R 6_5 R7 _5
79 C 11_5
R 35_5
C132
B2 B4 L1 2 R2 53 D12 U72
R53
R 54 R 52
C1 5_4
C1 4_4 R 36_4
R 45_1
C1 3 8 R2 5 5
U 5_1 U 3_1 U 4_1 U 1_1 U 11_1 C 13_5
L2_5
R 44_1 U 8_5
C17 _5
R45_1
R 40_1 L1_5
R44_1
U7 4 U75
C1 35 R2 6 0 R24 4 R24 0
2
26
R 17_ 4 R 20_ 4 R 14_ 4 R 23_ 4 R 21_ 4
R 15_ 4
R 18_ 4
R 24_ 4 R 22_ 4 R 19_ 4 R 16_ 4 R 3_4 R 1_4 R 2_4
D 2_4
D 1_4
U 10_ 4
C 7_4 R 25_4
C1 5_5
C1 4_5
C 7_5
C 9_5
R 36_5
R 25_5
J1_1 J1_2
C16_1 C16_2
U5_1 U3_1 U4_1 U1_1 U11_1 U5_2 U3_2 U4_2 U1_2 U11_2
R43_1 R45_2
C10_1 C10_2
R43_2
R40_1 R30_1 R40_2 R30_2
R34_1 R33_1 R44_2 R34_2 R33_2
U 6_4
R 17_ 5 R 20_ 5 R 14_ 5 R 23_ 5 R 21_ 5 R 18_ 5 R 15_ 5 R 24_ 5
R 19_ 5
R 22_ 5
R 16_ 5 R 3_5 R 1_5 R 2_5
D 2_5
U 10_ 5
D 1_5 U 6_5
R2
U9_2
C138 R255
R1 R3
U9_1
U11
C140 C143 R242
R4
R261 C129
U74 U75 R243
B2 B4 BP3 V70 BP4
C135 R260
C141
C 10_1
R 43_1 R 45_2 R 43_2 R 45_3 R 43_3 R 45_4 R 43_4 R 43_5 R 45_5
U10
J1_1 J1_2 J1_3 J1_4 J1_5
C 16_1 R 33_1 C 16_2
R 30_1 R 40_2
R 34_1 R 44_2 R 34_2 R 44_3
C 10_2 C 10_3
R 33_2 C 16_3 R 33_3 C 16_4
R 40_3 R 40_4
R 34_3 R 44_4 R 34_4 R 44_5 R 34_5
C 10_4 C 10_5
R 33_4 C 16_5 R 33_5
U 5_2 U 3_2 U 4_2 U 1_2
C1 4 0 C1 4 3 R2 4 2 R4
R26 1 C1 2 9 C1 4 1
U 9_2 U 9_3
U 11_2 R 30_2 U 5_3 U 3_3 U 4_3 U 1_3 U 11_3 R 30_3 U 5_4 U 3_4 U 4_4 U 1_4
U 9_4 U 9_5
U 11_4 R 30_4 U 5_5 U 3_5 U 4_5 U 1_5 U 11_5 R 40_5 R 30_5
R2 M1
C1 3 2 P5 P6
R1 R3 P1 1 P1 0
U10 P4
R 243
P9
P3 P1 P2
U12 U12 U13
BP3
B3
P15 P12
V7 0 BP4 P14 P1 3
B1
P7 BP2 P8 J2
U11
MERGER Board, Version 8 ,May 2007 Annex 14 : Board implantation components ( bottom side )
C4_1C4_1
C3_1 C3_1
C2_1 C2_1
C1_1 C1_1 R28_1 R29_1 R37_1
R37_1
R28_1 R29_1
Q3_1 R32_1
Q1_1
R32_1 R38_1
R31_1
U2_1
Q4_ 1
R39 _1
R39_1
R38 _1
Q4_1
R41_1 U2_ 1
R42_ 1 R4 1_1
R42_1
Q3_1
Q1_1
Q2_1
Q2_1 R31_1
Page 48/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
C6
C4_2
C3_2
C2_2
C1_2 R32_2
R29_2
Q1_2
Q2_2
R31_2
R39_2
R38_2
U2_2
Q4_2
R42_2 R41_2
Q3_2
R28_2
R37_2
Page 49/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
C46 C47
C44 C43
C57 C56
R57 R58 C54 C51
R50 R51
C58 C55 C59 C52 C41
C4_3
C53 C60
C42
C3_3
C40
C2_3
C39
C1_3 R 32_3
R29_3
Q1_3
Q2_3
R 31_3
R39_3
U2_3
Q4_3
R38_3
R42_3 R41_3
Q3_3
R28_3
R37_3
Page 50/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
C13 C16 C19
C5 C3 C1
C21 C18 C15
C11
C10
C8
C9 C7
C4
C2
C17
C17
C20
C4_4
BP1
C3_4
C2_4
C1_4 R28_4 R29_4 R32_4
Q1_4
Q2_4
R3 1_4
R39 _4
U2 _4
Q4_4
R38_4
R 42_4 R 41_4
Q3 _4
R37_4
Page 51/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007
C4_5
C3_5
C2_5
C1_5 R28_5 R29_5 R32_5
Q1_5
Q2_5
R31_5
R39_5 R38_5
U2_5
Q4_5
R42_5 R41_5
Q3_5
R37_5
Page 52/74, Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 Annex 15 : FPGA VHDL file description 1 / FPGA VHDL file description : MERGER Function --======================================================================== --- Design Units : MERGER board, CREAM experiment --- File name : MERGER.vhd --- Purpose : --- Notes : MERGER FPGA Top level VHDL file --- Limitations : --- Errors : --- Library : --- Dependencies : --- Author : Joel BOUVIER -Laboratoire de physique Subatomique et de cosmologie -53 Avenue des Martyrs -38026 Grenoble Cedex, FRANCE ---============================================================================ Revision List -- Version Author Date Change -- 0.0 JB 27/01/06 Initial version -- 0.1 JB 06/02/06 Initialiaze twac constant to 10 -- 0.2 JB 08/02/06 Change TWAC constant in std_logic_vector instead -of integer -17/02/06 change size of constant convert_temp ( 12 bits -instead of 16 ) -add APA library ( for GLINT component ) -change value of convert_temp constant ( 334 -instead of 668 because the decrease loop in core -•dle•wled is made in 2 state ) -20/02/06 Change the value of convert_temp constant to -45 µs ( time adjusted before DAQ_FEE board -simulation ) old value : 334h new value : 384h -21/02/06 Change Convert_temp constant after CHERCAM DAQ -global simulation to 3A0h
-- 0.3 JB 06/08/06 Modification in MERGER_COMMAND.vhd -Modification in MERGER_CORE.vhd -Add interface with the DAC and the LED -Add MERGER_DAC.vhd --============================================================================ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library APA;
entity merger is port ( POR_RESET_G low RSTIN_N_G CLK POR_RESET RSTIN_N NO_ME ENIN_N DIN TRIG_RECEIVED DAT_IN_ACK
: in
std_logic ;
-- Power on Reset, Global in, active
: in : in
std_logic ; std_logic ;
-- hard Reset, Global In, active low -- Basis clock, Global Input
: : : : : : :
std_logic std_logic std_logic std_logic std_logic std_logic std_logic
-------
in in in in in out out
; ; ; ; ; ; ;
Power on Reset signal Power on Reset signal Merger number ( 0 or 1 ) Enable from SPARSIFICATION board data from SPARSIFICATION board view signal
SERDES link PD_N CK_SERDES DAT
: out std_logic ; -- SERDES power down ( low active ) : out std_logic ; -- SERDES transmission clock : out std_logic_vector(20 downto 0); -- SERDES data
DAQ_FEE link pw_row rst_row row3_row dout_row en_n_row sel_row
: : : : : :
out out out out out out
std_logic_vector(4 std_logic_vector(4 std_logic_vector(4 std_logic_vector(4 std_logic_vector(4 std_logic_vector(4
downto downto downto downto downto downto
Page 53/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
0); 0); 0); 0); 0); 0);
-------
command power for FLEX RST signal to FLEX Row3 signal to FLEX data signal to DAQ_FEE Enable signal to FLEX Output buffer selection
MERGER Board, Version 8 ,May 2007 endr_row dr_row0 dr_row1 dr_row2 dr_row3 dr_row4
: : : : : :
out in in in in in
std_logic_vector(4 std_logic_vector(9 std_logic_vector(9 std_logic_vector(9 std_logic_vector(9 std_logic_vector(9
LED interface LED_CMD DAC_SYNC_N DAC_SCLK DAC_DIN
: : : :
out out out out
std_logic std_logic std_logic std_logic
downto downto downto downto downto downto
0); 0); 0); 0); 0); 0);
-------
Input Input Input Input Input Input
buffer selection data from FLEX data from FLEX data from FLEX data from FLEX data from FLEX
; ; ; );
end merger ; architecture behave of merger is component merger_command port ( talk_frame : in std_logic_vector(7 downto 0); RST : in std_logic ; -- Asynchronous Reset CLK : in std_logic ; -- Basis clock LD_CMD : in std_logic ; -- Enable to Transmit command enable IDDLE : in std_logic ; -- Initial state DIN : in std_logic ; -- Data input from SPARSIFICATION EIN : in std_logic ; -- ENABLE input from SPARSIFICATION DOUT : out std_logic ; -- DATA signal to ROW ENOUT : out std_logic ; -- Enable data signal to ROW ENIN : out std_logic ; -- ENABLE ddata signal to MERGER_CORE module datin : out std_logic_vector(15 downto 0) – Data to MERGER_CORE module ); end component ; component merger_core port ( convert_temp : in trigger_frame : in ID_CD_MERGER : in RST : in CLK : in ENIN : in module datin : in module BUSY : in NO_ME : in
std_logic_vector(11 downto 0); std_logic_vector(7 downto 0); std_logic_vector(3 downto 0); std_logic ; -- Asynchronous Reset std_logic ; -- Basis clock std_logic ; -- ENABLE data signal 2 MERGER_CORE
switch LD_CMD INDIC_CMD IDDLE endr sel dac_dat DAC_CMD LED_CMD end component ;
: : : : : : : :
out out out out out out out out
std_logic ; -- Enable to Transmit command enable std_logic ; -- Command •dle•wledgement std_logic ; -- Initial state std_logic_vector(4 downto 0); std_logic_vector(4 downto 0); std_logic_vector(15 downto 0); std_logic ; std_logic );
component merger_data_io port ( twac : in std_logic_vector(3 downto 0) ; RST : in std_logic ; -- Asynchronous Reset CLK : in std_logic ; -- Basis clock NO_ME : in std_logic ; -- Merger number ( 0 or 1 ) ENOUT : in std_logic ; -- Enable data signal to ROW IDDLE : in std_logic ; -- Reset STATE command endr : in std_logic_vector(4 downto 0);-- row validation dr_0 : in std_logic_vector(9 downto 0);-- Data in row 0 dr_1 : in std_logic_vector(9 downto 0);-- Data in row 1 dr_2 : in std_logic_vector(9 downto 0);-- Data in row 2 dr_3 : in std_logic_vector(9 downto 0);-- Data in row 3 dr_4 : in std_logic_vector(9 downto 0);-- Data in row 4 BUSY : out std_logic ; DAT_IN_ACK : out std_logic ; out_data : out std_logic_vector(20 downto 0));-- Output data end component ; component merger_power port ( max_cpt_power : in std_logic_vector(15 downto 0); RST_N : in std_logic ; -CLK : in std_logic ; -NO_ME : in std_logic ; -pw_row : out std_logic_vector(4 downto 0));-end component ;
Asynchronous Reset Basis clock Merger number (0 or 1) command power for FLEX
component GLINT port( A : in std_logic ; GL : out std_logic ); end component;
std_logic_vector(7 downto 0); -- Data to MERGER_CORE std_logic ; std_logic ;
-- Merger •dle• number, assigned by
component merger_dac port ( RST : in
std_logic ;
-- Asynchronous Reset
Page 54/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 CLK DAC_CMD dac_dat DAC_SYNC_N DAC_SCLK DAC_DIN end component ; signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal
: in : in : in
std_logic ; -- Basis clock std_logic ; std_logic_vector(15 downto 0);
: : : : : : : : : : : : : : : : :
constant talk_frame constant trigger_frame constant ID_CD_MERGER command identifier constant convert_temp constant twac constant max_cpt_power
std_logic ; std_logic ; std_logic_vector(15 downto 0); std_logic ; std_logic ; std_logic ; std_logic ; std_logic ; std_logic_vector(4 downto 0); std_logic_vector(9 downto 0); std_logic_vector(9 downto 0); std_logic_vector(9 downto 0); std_logic_vector(9 downto 0); std_logic_vector(9 downto 0); std_logic ; std_logic_vector(15 downto 0); std_logic ; : std_logic_vector(7 downto 0) : std_logic_vector(7 downto 0) : std_logic_vector(3 downto 0)
M_CMD0 : merger_command port map ( talk_frame RST CLK LD_CMD IDDLE DIN EIN DOUT ENOUT
dac_dat DAC_CMD LED_CMD
:= X”54”; := x”50”; := “1101”;-- MERGER board
: std_logic_vector(11 downto 0) := x”3A0”;-- T = 46,4 µs : std_logic_vector(3 downto 0) := “0001”; : std_logic_vector(15 downto 0) := x”FFFE”;-- T = 1,6ms
Begin
=> => => => => => => => =>
talk_frame, RST_INT, CLK, LD_CMD, IDDLE, DIN, ENIN_N, DOUT_INT, ENOUT_INT,
=> EIN_INT, => din_int);
M_COR0 : merger_core port map ( convert_temp trigger_frame ID_CD_MERGER RST CLK ENIN datin BUSY NO_ME LD_CMD INDIC_CMD IDDLE endr sel
: out std_logic ; : out std_logic ; : out std_logic );
RST_INT EIN_INT din_int LD_CMD IDDLE BUSY DOUT_INT ENOUT_INT endr_row_int dr_row0_int dr_row1_int dr_row2_int dr_row3_int dr_row4_int GENE_RST_INT dac_dat DAC_CMD
ENIN datin
M_IO0 : merger_data_io port map ( twac RST CLK NO_ME ENOUT IDDLE endr dr_0 dr_1 dr_2 dr_3 dr_4 BUSY DAT_IN_ACK out_data
=> => => => => => => => => => => => => =>
convert_temp, trigger_frame, ID_CD_MERGER, RST_INT, CLK, EIN_INT, din_int(7 downto 0), BUSY, NO_ME, LD_CMD, TRIG_RECEIVED, IDDLE, endr_row_int, sel_row ,
=> dac_dat, => DAC_CMD, => LED_CMD );
=> => => => => => => => => => => => => => =>
M_pow : merger_power port map ( max_cpt_power RST_N CLK NO_ME pw_row
twac, RST_INT, CLK, NO_ME, ENOUT_INT ,--LD_CMD, IDDLE, endr_row_int, dr_row0_int, dr_row1_int, dr_row2_int, dr_row3_int, dr_row4_int, BUSY, DAT_IN_ACK, DAT);
=> => => => =>
max_cpt_power, POR_RESET_G, CLK, NO_ME, pw_row);
Page 55/74 Data Acquisition Team, Laboratoire de Physique Subatomique et de Cosmologie, Grenoble, FRANCE
MERGER Board, Version 8 ,May 2007 & & dr_row4_int GENE_RST_INT , GL => RST_INT); M_dac : merger_dac port map ( RST CLK DAC_CMD dac_dat
=> => => =>
DAC_SYNC_N DAC_SCLK DAC_DIN
RST_INT, CLK, DAC_CMD, dac_dat,
(not (not (not (not (not
dr_row3(7)) dr_row3(3)) dr_row4(9)) dr_row4(7)) dr_row4(3))
& & & & &
dr_row3(6) dr_row3(2) dr_row4(8) dr_row4(6) dr_row4(2)
& (not dr_row3(5)) & dr_row3(4) & (not dr_row3(1)) & dr_row3(0); & (not dr_row4(5)) & dr_row4(4) & (not dr_row4(1)) & dr_row4(0);
end behave; ;
=> DAC_SYNC_N, => DAC_SCLK, => DAC_DIN );
Internal link GENE_RST_INT
