MEMS and Thermal Management

SEPTEMBER/OCTOBER 2013 Vol. 40 No. 5 MEMS and Thermal Management A Design Tool Fully Adapted... Fast Growing Market for MEMS... WWW.IMAPS.ORG IM P...
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SEPTEMBER/OCTOBER 2013 Vol. 40 No. 5

MEMS and Thermal Management

A Design Tool Fully Adapted... Fast Growing Market for MEMS...


IM Pr AP og S ra 20 m 1 Pa -at 3 T ge -a ec 23 -G hn la ic nc a e l

TSV and Chip I/O...


Features TSV and Chip I/O Compatible Embedded Microfluidic Cooling Technology for 3D ICs Muhannad S. Bakir, Yue Zhang, Li Zheng A Design Tool Fully Adapted to Develop a Thin Film Packaging Process Used for MEMS Devices F. Souchon, A.C. Gervais, L. Thouy, D. Saint-Patrice, J.L. Pornin Fast Growing Market for MEMS Packaging Moves Towards 3D WLP, Multi-Sensor Combos, and Common Platforms Eric Mounier and Rozalia Beica

6 s 10 s

16 s

On the Cover: Illustration of a 3D IC system enabled using TSV - a within-tier microfluidic cooling technology. Courtesy of Georgia Institute of Technology.






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MEMS Packaging and Thermal Management Phil Garrou Microelectronic Consultants of NC, Editor-in-Chief

This issue of Advancing Microelectronics is focused on two topics: MEMS Packaging and Thermal Management. As a follow up to our last issue on 2.5 & 3DIC, in this issue Professor Bakir and his students from GaTech take a look at the use of embedded microfluidic cooling to control heat removal in these stacked chip constructions. They adopt a micropin-fin based heat sink design with integrated TSVs. This technology is not destined for your next smart phone, but is surely something like what we will be seeing in future high performance computing and server storage. Dr. Souchon and co-workers from LETI share with us their design tool to develop thin film wafer level encapsulation of MEMS devices. The MEMS market is expanding rapidly and part of the reason is the ability to lower prices due to the advances in wafer level MEMS processing. Leti shares with us their process flows and “tricks of the trade.”

Last, our friends at Yole Développement continue our look at MEMS, which they see as surpassing 9 billion units this year with a 20% compound average growth. Mounier and Beica make a case for MEMS moving away from wire bonding to more direct bonding such as bumping or TSV interconnection. They see multisensory “combos” as a significant growth area for the future...

46th International Symposium on Microelectronics September 29-October 3, 2013 Photos courtesy of Rosen Centre Hotel

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SV and Chip I/O Compatible Embedded Microfluidic Cooling Technology for 3D ICs Muhannad S. Bakir, Yue Zhang, and Li Zheng, Georgia Institute of Technology

With continued aggressive CMOS scaling, interconnect performance and power dissipation have become a limiting factor for high-performance integrated circuits [1][2][3]. Three-dimensional ICs offer new opportunities for improving chip performance and reducing power dissipation by enabling shorter interconnection length (both on- and off-chip) as well as the possibility of heterogeneous integration. However, a number of challenges must be overcome before 3D ICs can be adopted for high-performance and high-power applications [4][5][6]. Cooling is a key issue for 3D ICs since both the power dissipation per unit area and the thermal resistance for the dice within the stack increase with the number of tiers. To address the challenges in heat removal, innovative cooling solutions have been proposed, including single-phase forced microfluidic cooling [7][8][9][10], two-phase microfluidic cooling and active thermoelectric coolers to address hotspots. Fig. 1 illustrates our vision for the implementation of a within-tier microfluidic heat sink (MFHS) in a heterogeneous high-performance 3D IC system [11-16]. The proposed 3D IC system features a silicon interposer with embedded fluidic delivery microchannels and an array of 3D stacked processor and memory tiers. The

processor tiers each contain an embedded MFHS; TSVs are routed through the integrated MFHS. Each tier has dedicated solder-based microfluidic chip I/Os [11] (to be discussed later) for fluid delivery from the interposer. This approach allows targeted coolant delivery and helps minimize the vertical thermal gradient across the stack when power dissipation varies in the stack. The flow rate may be increased or decreased to meet different heat removal targets while minimizing pumping power. The proposed local coolant delivery mechanism may minimize the lateral thermal gradient within a single tier as well . Moreover, since the MFHS is equal in size to the die, this approach allows high lateral scalability of the electronic components, i.e., placing an array of 3D ICs in very close proximity, which greatly enhances off-chip bandwidth and reduces energy-per-bit. We adopt a micropin-fin based heat sink (MPFHS) design with integrated TSVs [13]. A summary of the fabrication process flow of MPFHS with TSVs is shown in Fig. 2. High AR TSVs (18:1) are etched using a standard Bosch process in step 1. A thermal oxide liner is then grown to isolate the TSVs from the substrate in step 2. In step 3, bottom-up pulsed electroplating with Enthone DVF plating solution is used to fill the vias with copper.

Fig. 1. Illustration of a 3D IC system enabled using TSV - a within-tier microfluidic cooling technology.

Fig. 2. Process flow of high aspect ratio TSV integration into the MPFHS.



Following electroplating, the sample is polished using iCue 5001 provided by Cabot Microelectronics Corp. (step 4 in Fig. 2). The 200 μm tall MPFHS is patterned and etched from the top side in steps 5 and 6, respectively. The fabricated TSVs are ~10 μm in diameter and 178 μm deep (18:1) [16]. The TSVs are electroplated with no voids. SEM and optical images of the fabricated MPFHS with integrated copper TSVs (3x3 TSV array per micropin-fin) are shown in Fig. 3 [13]. The fabricated die spans 1 cm x 1 cm and has 1,936 silicon micropin-fins. Each silicon micropin-fin has 9 electrical TSVs, providing a total of 17,424 electrical TSVs that can be used for vertical connectivity while consuming only 1.36% of the die area. Four-point resistance measurements are performed on the high AR TSVs. The average measured TSV resistance is 36.5 ± 1.5 mΩ, which is close to the theoretical value of 38 mΩ. The performance of the microfluidic cooled heat sink is evaluated experimentally using the simplified testbed shown in Fig. 4 [15]. Each tier has its own set of inlet and outlet ports allowing independent control of the flow rate in each tier. Moreover, each tier has a Pt thin film heater to emulate the heating of a microprocessor; the heating area is formed by a single Pt heater with dimension of 1 cm × 1 cm. As a benchmark, a 3D aircooled heat sink (ACHS) chip testbed was also made. In the ACHS experiment, a high-performance ACHS containing 3 copper heat pipes and 45 aluminum fins designed for the Intel i5/i7 CPU is attached to the back side of the ACHS 3D chip stack through a thermal interface material (TIM). The ACHS chip stack is tested while the fan rotates at its maximum speed (2500 rpm ±15﹪). The corresponding air flow is 54.8 CFM. In the microfluidic experimental setup (Fig. 4), two pumps are connected to the two inlets in the stack (i.e., each tier has its own inlet and pump). De-ionized (DI) water is pumped from a nearby reservoir. Polyester based filters are connected to the outlet of the pump to eliminate any particles (>20 μm) that may potentially block the MPFHS. An acrylic block flow meter that measures up to 100 mL/min is connected to each inlet serially to measure the flow rate. For the sake of simplified port access, the two tiers are stacked orthogonally such that the inlets and outlets are easily accessible (Fig. 4). An Agilent N6705B power analyzer with 4 outputs is used to source current to the thin-film Pt heaters on the chip surfaces to emulate chip power dissipation. The heater resistance in each tier is measured and tracked using an Agilent 34970A data logger at 1 Hz. In both testbeds, the measured resistance, and thus junction temperature, represents the average junction temperature in each tier since we use a single heater per tier. The junction temperature increase of each layer of the MPFHS and ACHS stacks are shown in Fig. 5. The ITRS projection for maximum junction temperature rise is also plotted as a reference. As seen from the plots, when the power density in each tier is 100 W/cm2, the junction temperature rise in either microfluidic cooled tier is 30°C, resulting in an absolute junction temperature of 50°C. In contrast, the testbed under ACHS has a temperature rise of more than 54°C at 50 W/ cm2 [1416]. The processor-on-processor stack cooled using MPFHS dissipates more than 100 W/cm2 in each tier without reaching the ITRS projected maximum junction temperature. Improving the thermal interface material in both stacks could improve performance further.

Fig. 3. SEM (left) & optical images (right) of high aspect ratio TSVs integrated in micropin-fins (10 μm diameter, 35 μm pitch and 178 μm tall).

Fig. 4. Schematic of the microfluidic test setup for testbed 1.

Fig. 5. Junction temperature rise in a processor-on-processor stack under MFHS and ACHS.

Power delivery is another challenge for 3D ICs. Power supply noise (PSN) results from current flowing across the parasitic resistance and inductance of the power delivery network [11][17]. Multi-die stacks require high currents, and TSVs introduce higher resistance and inductance to the power delivery network. Thus, power delivery becomes more difficult for 3D ICs.

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Fig. 6. Electrical microbumps, fluidic microbumps, fluidic vias and fine-pitch wires.

We propose novel electrical and fluidic microbumps to simultaneously enable high-bandwidth die-to-die signaling, embedded microfluidic cooling and power delivery for silicon interposer- and 3D-based integrated systems [11]. Fig. 6 illustrates the fabrication results of high-density electrical microbump array (150 × 150 = 22,500 microbumps), two rows of fluidic microbumps (21 fluidic microbumps per row), and fine-pitch wires (8 μm width). The diameter of the electrical microbumps is 50 µm, and the inner diameter of the fluidic microbumps is 100 µm. Chips and interposers with electrical and microfluidic I/Os have been successfully assembled using a conventional flip-chip bonder. Following bonding, the resistance of a single electrical microbump was measured; the average resistance is 13.5 mΩ, which is consistent with expected results and thus indicating good bonding. Fluidic testing was conducted by pumping DI water into the bonded dice at a flow rate of up to 50 mL continuously for 4 hours. No leakage or pressure drop change occurred during testing, and thus, demonstrating the feasibility of the novel fluidic I/O interconnections.


[1] M. T. Bohr, “Interconnect scaling-the real limiter to high performance ULSI,” in Proc. of Int. Electron Devices Meeting, 1995, pp. 241-244. [2] J. D. Meindl, “Interconnect opportunities for gigascale integration,” IEEE Micro, vol. 23, pp. 28-35, 2003. [3] S. Borkar, “Thousand core chips: a technology perspective,” in Proc. of 44th Annual Design Automation Conference, San Diego, California, 2007, pp. 746-749. [4] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: the pros and cons of going vertical,” IEEE Des. Test Comput., vol. 22, no. 6, pp. 498-510, 2005. [5] P. G. Emma and E. Kursun, “Is 3D chip technology the next growth engine for performance improvement?” IBM J. of Research and Development, vol. 52, pp. 541-552, 2008. [6] S. M. Sri-Jayantha, G. McVicker, K. Bernstein, and J. U. Knickerbocker, “Thermomechanical modeling of 3D electronic packages,” IBM J. of Research and Development, vol. 52, pp. 623-634, 2008. [7] T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, W. Cesar, G. Toral, Y. Temiz, and Y. Leblebici, “Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks,” in Proc. of 3D System Integration, 2009, pp. 1-10. [8] D. B. Tuckerman and R. F. W. Pease, “High-performance heat sinking for VLSI,” IEEE Electron Device Lett., vol. 2, pp. 126-129, 1981. [9] N. Khan, Y. Hong, P. Tan Siow, H. Soon Wee, S. Nandar, H. Wai Yin, V. Kripesh, Pinjala, J. H. Lau, and C. Toh Kok, “3D packaging with through silicon via (TSV) for electrical and fluidic interconnections,” in Proc. of Electronic Components and Technology Conference, 2009, pp. 1153-1158. [10] Y. Peles, A. Kosar, C. Mishra, C.-J. Kuo, and B. Schneider, “Forced convective heat transfer across a pin fin micro heat sink,” Int. J. of Heat and Mass Transfer, vol. 48, pp. 3615-3627, 2005. [11] L. Zheng and M. S. Bakir, “Design, Fabrication and Assembly of a Novel Electrical and Microfluidic I/O Technology for 3-D Chip Stack and Silicon Interposer,” in Proc. of Electronic Components and Technology Conference, 2013 [12] Y. Zhang, A. Dembla, and M. S. Bakir, “A Silicon Micropin-fin Heat Sink with Integrated TSVs for 3D ICs: Trade-off Analysis and Experimental Testing,” in IEEE Transactions on Components, Packaging, and Manufacturing Technology, in-press. [13] A. Dembla, Y. Zhang, and M. S. Bakir, “Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs,” in Proc. of IEEE Int. Interconnect Technology Conf., 2012, pp. 1-3. [14] Y. Zhang, A. Dembla, Y. Joshi, M. S. Bakir, “3D stacked microfluidic cooling for high-performance 3D ICs,” in Proc. of Electronic Components and Technology Conf., 2012, pp.1644-1650. [15] Y. Zhang, L. Zheng, and M. S. Bakir, “3D Stacked Tier-independent Microfluidic Cooling for Heterogeneous 3D ICs,” in IEEE Transactions on Components, Packaging, and Manufacturing Technology, in-press. [16] Y. Zhang, L. Zheng, and M. S. Bakir, “Tier-Independent Microfluidic Cooling for Heterogeneous 3D ICs with Nonuniform Power Dissipation,” in Proc. of IEEE International Interconnect Technology Conference, 2013. [17] G. Huang and M. Bakir, “Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852–859, 2012.



Design Tool Fully Adapted to Develop a Thin Film Packaging Process Used for MEMS Devices


This paper deals with the development of thin film encapsulation for MEMS devices. A simulation-based methodology is reported to study the mechanical response of cap membrane. For the first time, both deflection and stiffness measurements are considered to build the finite element model that simulates a thin film packaging. The cap release operation is used as a study case to illustrate this methodology. Promising results are reported as numerical and experimental data remarkably fit, and residual stresses inside cap material can be accurately estimated. Then, design investigations are discussed and confirm the relevance of the finite element model. Keywords: thin film packaging, deflection, stiffness, nanoindentation, simulation, design.

F. Souchon, A.C. Gervais, L. Thouy, D. Saint-Patrice, J.L. Pornin, CEA, LETI, MINATEC Campus, Grenoble, France, [email protected]

I. Introduction

MEMS Wafer Level Packaging is required for mass production of MEMS devices: wafer to wafer bonding is the usual solution, however thin film encapsulation becomes a promising alternative method [1]. A sealed cavity is formed above the MEMS devices by surface micromachining techniques: the cavity is made by etching a sacrificial layer covered with a thin cap package. Holes are previously drilled through the cap in order to enable efficient etching of the sacrificial layer. Finally, a film is deposited on the cap to seal these holes [2]. Nevertheless, major challenges should be overcome to develop a robust thin film encapsulation, namely a process flow fully compatible with the MEMS release, a hermetic sealing process, a cap strong enough to withstand high molding pressures, especially for large MEMS area [3-5]. Consequently, design tools are required to successfully develop thin film encapsulation. For that, finite element simulations are commonly used to study the mechanical behavior of the cap, and this paper proposes an original approach to make finite element results fit with experimental data. This approach guarantees reliable predictive results because simulations are double checked with experimental characterizations including cap deflection and cap stiffness measurements. A study case which shows how to manage the cap deflection during the release operation is used to illustrate our approach and the relevance of our methodology. The paper starts with the description of the thin film packaging process developed by CEA-LETI [2] and the introduction of the study case used to illustrate our approach. Then, the principles of our approach are briefly reported, and experimental details are described. To finish with, the results related to the study case are discussed: starting with the experimental and numerical results comparison, and following by using simulations to lead design investigations for cap release management.

II. Thin Film Packaging Process

As mentioned above, thin film encapsulation is made with surface micromachining techniques and the main operations of the process flow are listed below (see also Fig.1 and Fig.2): 10

• a thick sacrificial layer is deposited and patterned above the MEMS (a). A polymer is used as sacrificial layer; • the cap is made of a silicon oxide deposit (b); • holes are opened through the cap layer by a standard photolithography/dry etching process (c); • the sacrificial layer is etched by a dry process (d). High density plasma etching is used to remove the polymer through the very small apertures (holes). As a dry process is used, problems such as sticking or pollution generally induced by wet etching can be avoided. An example of cap release operation is shown in Fig.3, the etching being made through lateral apertures only; • the sealing of the cap is performed by a silicon oxide deposit (e). A PECVD process is usually used, and the deposition pressure defines the residual pressure inside the cavities. Practically, the etching of the sacrificial layer is one of the major issues of the thin film packaging process because it can impact the performances of the MEMS device. Indeed, the shape of the cap after sacrificial layer etching is mainly tuned by the cap material residual stresses and the sacrificial layer geometry. Compressive residual stresses are usually mandatory in order to get a buckling effect during the cap release, which is required to avoid any damage of the MEMS device by the cap, the buckling effect direction being managed by the geometry of the sacrificial layer. Moreover, reinforcement operations are also important, because making a cap sufficiently robust to withstand high molding pressures is often required. For information, the usual techniques used to mechanically reinforce the cap are cap thickness optimization, cap shape design, reinforcement layer, support addition [4-7]. The study case reported in this paper is focused on these different aspects related to the mechanical response of the cap. More precisely, the cap release operation is used to successfully build our finite element model, and parameters contributions are analyzed thanks to this numerical design tool.


Figure 4. Scheme of the convergence loop

Figure 1. Thin film packaging process flow

Figure 2. Optical picture of thin film encapsulation

Figure 3. Scanning electron microscope picture of thin film packaging

III. Approach to Validate Finite Element Model A. Convergence loop principle The key point for a design tool is to achieve reliable results. To deal with it, the approach proposed in this paper uses a convergence loop based on experimental data to build the finite element model (see Fig. 4). Experimental characterizations include not only the cap profile evolution during the process (common approach reported in the literature as in [4]), but also the mechanical properties of the cap and especially its stiffness (reported for the first time in this paper). This original approach allows estimating accurately the residual stresses of the cap materials by the convergence of numerical and experimental data.

Practically, it is the first time that a mechanical finite element model adapted to thin film encapsulation is double checked by both deflection and stiffness measurements, which allow guaranteeing the robustness of the finite element simulations. B. Experimental details This section briefly describes the technical tools used for deflection/stiffness measurements and finite element simulations. Deflection measurements are performed by means of a stylus profilometer. A stylus profilometer is preferred to optical techniques because cap materials can be optically transparent. The stylus profilometer is used to determine midline profiles of the cap, and these profiles are used to extract the cap deflection. For example, the cap deflection during the release operation is determined by the profile difference between midline profiles before and after cap release. Practically, the model used for this study is a P16 stylus profiler made by KLA-Tencor. The load applied to the tip was adjusted to 1µN in order to guarantee repeatable measurements without cap deformation during the measurement. About 5 to 10 samples at least were measured to determine a representative cap profile. Stiffness measurements are performed by means of Nano indentation measurements. The nanoindenter tip is approaching the sample and when in contact, it exerts a quasi-static load on its surface while constructing the force-displacement curve. The stiffness can be extracted from the slope of this force-displacement curve as function of applied load or tip displacement. Practically, the model used for this study is a XP-MTS Nanoindenter. A conospheric tip with a 5µm radius was selected to apply a local load at the geometrical center of the cap membrane (cap center stiffness). The maximum load (~1000µN) and the tip contact detection (~100N/m) were adapted to the membrane stiffness. About 5 to 10 samples at least were also measured to determine representative values of the cap center stiffness, the stiffness values being extracted for a 50µN load (same load used for simulation).

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Figure 5. Profiler data for a silicon oxide quadratic plate (smooth surface - 800µm side length - 3µm thickness)

For finite element simulations, COMSOL software is used to investigate the mechanical response of the cap membrane. The mechanical model uses static conditions including linear and non-linear elastic deformations. The membrane cap is meshed with tetrahedra elements, and only 1/8 of the membrane surface is modeled by plane of symmetry in order to reduce the number of elements. Practically, these choices allow meshing the membrane with less than 50  000 tetrahedra elements. A Young’s modulus E= 70GPa and Poisson ratio υ=0.17 for silicon oxide material are used in the simulations. The membrane stiffness is computed by applying a 50µN equivalent load at the membrane center (same load used for experimental measurements).

IV. Study Case Results

Figure 6. Nanoindentation data for a silicon oxide quadratic plate (smooth surface - 800µm side length 3µm thickness)

Figure 7. Geometry and meshing of the cap membrane (smooth surface - quadratic plate - edge rolls)

Figure 8. Numerical results: cap profile as function of residual stresses for a silicon oxide quadratic plate


Finite element model validation The cap structure used in the study case is a silicon oxide quadratic plate of 800µm side length and 3µm thickness (see Fig. 2). The square cavity dimensions are monitored by the deposition and the patterning of the polymeric sacrificial layer (3µm thick). The annealing of the sacrificial layer also adds edge rolls to the square shape. Then, a silicon oxide layer forming the capping membrane is deposited, and the membrane deflects by buckling effect during the etching of the sacrificial layer due to compressive residual stresses (50-80MPa). Practically, the measurements show that the shape of the cap looks like a quadratic plate before sacrificial layer etching: its overall sizes are 800µm side long and 3µm high, and edge roll sizes are 0.6µm high and 50µm long. After the cap release operation, the cap height becomes close to 18µm at the square center whereas the edge rolls can be still visible (see Fig.5). The cap stiffness is also measured after the cap release: the stiffness at the cap center starts to 300N/m and decreases as the tip displacement increases as shown in Fig. 6. These experimental data are used to run and validate our finite element simulations. First, the stack and the profile of the cap before release are precisely reproduced before sacrificial layer etching (see Fig. 7). Second, compressive stresses inside the cap material layer are progressively applied to deflect the cap by buckling effect. The numerical results show that the buckling effect grows with the compressive stresses of the cap material (see Fig. 8). Third, the cap stiffness is also calculated as a function of compressive stresses. As expected, the numerical results indicate that the stiffness also increases with the compressive stresses. The numerical values of deflection and stiffness as functions of compressive stresses are reported in Table 1 and compared to experimental data. The relevance of the finite element model is achieved as both membrane deflection and stiffness results fit with experimental data. Indeed, respectively, 70-80MPa of residual stresses for cap deflection against 60MPa for cap stiffness give the best fits. These fitted values of compressive stresses are very similar and in good agreement with experimental measurements that allow using this model to study how design parameters impact the mechanical response of the cap membrane: some results are discussed in the two following sections.



Sensitivity to the cap thickness Numerical simulations were computed for different cap thicknesses and show that the stiffness increases with the cap thickness whereas the deflection keeps quite steady. Indeed, the detailed results show that the cap deflection is mainly managed by the residual stresses, and the cap stiffness is both sensitive to the residual stresses and the cap thickness (see Fig. 9 and Fig. 10). B. Sensitivity to a corrugated surface Corrugated cap membranes are investigated to reinforce the cap membrane. Practically, as corrugated samples were also manufactured, both experiments and simulations are used to compare their mechanical response with smooth samples. The corrugated samples are close to the smooth samples described in section A: a silicon oxide quadratic plate of 800µm side length and 3µm thickness but with 3µm high corrugated shapes repeated all 50µm length in both directions (see Fig. 11).

Table I: Numerical results for a silicon oxide quadratic plate (smooth surface - 800µm side length - 3µm thickness)

Figure 9. Numerical results: deflection and stiffness as function of cap thicknesses (smooth surface - 800µm quadratic plate - 60MPa compressive residual stresses)

Figure 11. SEM picture of a corrugated cap after sacrificial layer etching (800µm side length - 3µm thickness)

The deflection and stiffness measurements of corrugated caps are plotted in Fig. 12 and Fig. 13. Their mechanical responses are quite similar to smooth caps: deflection and stiffness are a little bit smaller on the corrugated membrane. These experimental results seem quite surprising because the reinforcement effect of a corrugated surface is not well-confirmed. However, the numerical results reported in Table II confirm this behavior, and are also in good agreement with experimental data. Indeed, the numerical results better fit experimental data for 50MPa compressive stresses against 60MPa for smooth samples. These results confirm again the relevance of the finite element simulations.

Figure 10. Numerical results: deflection and stiffness as function of residual stresses (smooth surface - 800µm quadratic plate - 3µm thickness)

V. Conclusion

This paper proposes a design tool to study the mechanical response of thin film encapsulation. For the first time, both deflection and stiffness measurements are used to run the finite element simulations. The relevance of this approach is proved as numerical results remarkably fit experimental data. This numerical model is absolutely required to design the thin film encapsulation because it allows fast and easy parametric studies as shown in this paper. Further simulations will focus on the membrane reinforcement.


The authors would like also to acknowledge CEALETI-MINATEC staff working on the 200mm MEMS production line for wafer fabrication.

Figure 12. Profiler data for a corrugated silicon oxide quadratic plate (800µm side length - 3µm thickness)

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Figure 13. Nanoindentation data for a corrugated silicon oxide quadratic plate (800µm side length - 3µm thickness)

Table II: Numerical results for a corrugated silicon oxide quadratic plate (corrugated surface - 800µm side length - 3µm thickness)

References [1] [2] [3]






Masayoshi Esashi, “Wafer level packaging of MEMS,” Journal of Micromechanics and Microengineering, Vol. 18, 2008, 13pp. C. Gillot, J.L. Pornin, G. Parat, F. Jacquet, E. Lagoutte et al., “Wafer level Thin Film Encapsulation for RF MEMS,” IMAPS Advancing Microelectronics, 2008, 5 pp. D. Reuter, A. Bertz, T. Werner, M. Norwack and T. Gessner, “Thin film encapsulation of microstructures using sacrificial cf-polymer,” Proceedings of Transducers and Eurosensors Conference, 2007, pp. 343-346. Y. Shimooka, M. Inoue, M. Endo, S. Obata, A. Kojima, T. Miyagi et al., “Robust Hermetic Wafer Level Thin-Film Encapsulation Technology for Stacked MEMS / IC Package,” Electronic Components and Technology Conference, 2008, pp.824-828. S. Obata, M. Inoue, T. Miyagi, I. Mori, Y. Sugizaki et al., “In-Line Wafer Level Hermetic Packages for MEMS Variable Capacitor,” Electronic Components and Technology Conference, 2008, pp. 158163. P. Gonzalez, G. Claes, K. De Meyer and A. Witvrouw, “Design and characterization of thin SiGe membranes for MEMS packaging at wafer level,” Semiconductor Advances for Future Electronics Workshop – SAFE, 2008, pp.548-551. F. Santagata, J. Zaal, V. Gonzalez, H. Mele, F. Creemer, and P Sarro, “Mechanical Design and Characterization for MEMS Thin-Film Packaging,” Journal of Microelectromechanical systems, Vol. 21, 2012, pp. 100-109.


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ast Growing Market for MEMS Packaging Moves Towards 3D WLP, Multi-Sensor Combos, and Common Platforms Eric Mounier and Rozalia Beica, Yole Développement

We expect continued doubled-digit growth for the MEMS packaging business, as MEMS makers move to increased value multi-chip integration platforms for high volume consumer markets. MEMS packaging will reach a 9 billion unit volume this year, and see 20% compound average growth, to pass 23 billion units by 2018. Packaging, assembly and test accounted for 35% of the value of the roughly $10 billion packaged MEMS devices sold in 2012, for a ~$3.5 billion business. CAGR for the next five years is expected to be higher than 12%.

MEMS moves slowly away from wire bonding towards 3D WLP

The vast majority of MEMS devices today–about 75% of the total units–are wire-bonded systems in a package, the MEMS die wire bonded side by side or stacked with its controlling ASIC on a standard leadframe or BGA/LGA laminate substrate, and this will likely continue to remain a major approach for a long time. Another 20% or so of the units are straight CMOS devices, with the MEMS structures made directly in the same process flow as the ASIC on a single chip. Though many believed most MEMS would eventually go to this system-on-a-chip approach, it is now apparent that it’s best suited for particular types of devices that need very short connections, such as arrays of micromirrors or microbolometers that need direct response at each pixel unit, or for very tiny devices like oscillators. Demand for smaller devices and shorter interconnects for better signals, however, is driving MEMS packaging towards some sort of more direct bonding, bumping or 3D connections between the MEMS and the ASIC and/or the motherboard. Use of 2.5D/3D integration with TSVs is already a commercial reality for MEMS, with products on the market ranging from FBAR duplexers from Avago and oscillators from Discera, to accelerometers from STMicroelectronics and gyroscopes from Murata, and more such products will follow soon. These low density vias may run through the interposer that caps the MEMS, or through the MEMS die itself to connect to the circuit board, requiring considerably less demanding geometries and mobility than for TSVs for ICs. And with the cooler running MEMS devices, thermal management is not yet a major issue. However, by 2015, we expect to start to see closer integration with some full 3D stacks integrating not only the MEMS and the capping wafer, but also the 16

controlling ASIC and other analog or RF chips with TSVs, where thermal management, tighter pitches, and higher performance will become issues. Room temperature bonding may also become of increasing interest to MEMS makers, as an alternative for stacking the MEMS and ASIC without damaging the CMOS wafer. While the leading MEMS players are currently using a wide variety of 2.5D/3D approaches, they are all aiming at platforms that can be re-used across multiple devices, as the sector matures beyond its traditional one product, one process, one package mentality. Fabless InvenSense made its big inroads in the consumer gyroscope market due, in part, to its efficient low cost method of capping and interconnecting the MEMS to the ASIC by Al/Ge metal-to metal wafer-level bonding done at mainstream foundries TSMC and Global Foundries. Interestingly, the company is now openly licensing this technology, along with the rest of its fabqualified process, and offering multi-project wafer runs for developers, figuring the technology will have more applications than it can develop itself. Similarly, the two leading specialty MEMS foundries each target lowdensity TSV platforms for use by multiple customers. Silex Microsystems has long offered a TSV module to its customers, while Teledyne DALSA is also working on developing a low cost, wet-plated copper TSV platform, for wafer–level MEMS to ASIC connection for its MEMS foundry customers. DALSA is using a plating process technology licensed from Alchimer that integrates the via isolation and filling in the same process modules for better-cost efficiency, and working together towards production volume development. The two leading MEMS IDMs are taking quite different approaches for their own product packaging platforms. STMicroelectronics makes polysilicon vias isolated by etched-out air gaps for TSVs through its MEMS die for attachment to the motherboard, using the same MEMS process it uses to make its inertial sensors, but on about a 10X larger scale. The MEMS can then be either wire bonded or more likely flip-chipped to the ASIC. ST reports the 20%-30% reduction in die size from replacing the bond pads with these TSVs more than counters the modest added cost of the process, to reduce the total cost. Robert Bosch, in contrast, primarily uses a proprietary solder bumping approach to connect its MEMS and ASICs, and does it at outsourced suppliers.


Combination sensors move more value to the packaging

Consumer market pressure to reduce costs, as well as improve sensor performance, are also rapidly driving MEMS inertial sensors makers to combine multiple MEMS die in the same package, which makes more complex demands on the mid- and back-end processes. We expect these combo units will see 43% CAGR over the next five years to become a $2.3 billion opportunity by 2018, steadily replacing discrete sensors and accounting for most of the growth in the inertial sensor market going forward. These multi-sensor modules save on costs and space by sharing one package and reducing the number of ASICs needed. They can also improve performance by cross calibrating the data from the different sensors. But effectively managing the increasing volumes of sensor data from these combination sensors will require shorter, faster connections between the components than the current standard wire bonding, to, for example, reduce sensor drift for more accurate position sensing. This will likely drive the modules towards interposer and TSV solutions. That means the modules will need to be assembled with high yields from known good die to be economic, and then all six, nine or ten sensor axes tested and cross-calibrated. MEMS manufacturers will also need to figure out how to assure users of second sources for the complex multi component systems. This added complexity of the combo modules will likely move more of the value to the packaging and test. While these combination sensors need complex multi die integration, there are multiple different approaches for doing this packaging. STMicroelectronics’ 9-axis combo unit connects five separate die—one 6-axis MEMS gyro and accelerometer, two ASICs, and two magnetometers to cover the x, y and z directions—

in a stair-step stack with some 74 wire bonds arrayed on both faces of the stack. This complex packaging solution, done in house, means much of the cost of the device is in the packaging. InvenSense, in contrast, bonds a single ASIC to a single 6-axis MEMS die at the wafer level with an Al/Ge eutectic bond, then wire bonds this unit and a single magnetometer die to the package substrate, connecting the two die with some 30 wires, so much of the device value is in the MEMS and ASIC unit bonded with the proprietary process. However, both of these very different approaches end up with the same 4mm x 4mm LGA package, and appear to have very similar manufacturing costs .

High volume, low cost markets push MEMS towards more outsourcing, convergence on common platforms

The consumer business is driving MEMS makers towards re-usable packaging platforms and outsource suppliers. The recent growth in the MEMS market has been driven primarily by the consumer business, and, moreover, primarily by the exploding demand for the four main types of devices used in mobile phones and tablets. The consumer MEMS market reached $5 billion last year, far and away the biggest sector for MEMS, already twice the size of the automotive market, and accounting for almost 50% of the total sector of $10 billion revenues in 2012. The four main devices used in this consumer mobile gear–accelerometers, gyroscopes, magnetometers and microphones–have accounted for more than 50% of all MEMS units shipped in the past two years. These high volume and cost sensitive markets, with their relatively limited variety of devices, are pushing MEMS packaging to move from unique custom packages towards more re-usable platforms, and opening more opportunities for OSATs. Currently only about 30% of MEMS devices are packaged by outsourced sup-

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pliers, compared to about half of all ICs. While MEMS has traditionally been largely an IDM business, a few fabless MEMS suppliers have broken through to high volume with inertial sensors and microphones for the consumer market, for which they need outsource packaging suppliers. IDMs will also need to qualify more OSAT partners as second sources to diversify their supply chains for these high volume customers. We expect that as MEMS companies increasingly move beyond competing on manufacturing technology to competing on functionality, more will begin to use some common platforms for packaging, making more use of the outsourced infrastructure to bring down costs and speed development time. MEMS microphone packaging from major suppliers has all now settled around the same general platform of wirebonding the MEMS and ASIC in an SiP module on a BGA/LGA laminate PCB substrate with an air access hole, under a metal lid. We expect to see more of such general convergence around platforms for WLP and TSV interconnects, SiP modules with micro lead-frames, and chip arrays using molded or cavity packaging. This convergence will allow substrate suppliers and packaging subcontractors from the IC world to develop libraries of building blocks or common platforms to ease development of MEMS packages for common product families.


Rozalia Beica is the CTO and Business Unit Director leading Advanced/3D Packaging and Semiconductor Manufacturing activities within Yole Développement. For more than 15 years she has been involved in the research, strategic marketing and application of WLP and 3D/TSV at materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. Beica has authored over 50 papers and publications and she is actively participating in several 3D & Advanced Packaging Committees worldwide. She has a M.Sc in Chemical Engineering (Romania), a M. Sc. In Management of Technology (USA) and a GXMBA from IE University (Spain). Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked at CEA LETI R&D lab in Grenoble, France in the marketing department. Since 1998 he is a co-founder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Mounier is in charge of market analysis for MEMS, equipment & material. He is Chief Editor of Micronews, and MEMS’ Trends magazines (magazine on MEMS Technologies & Markets).





IMAPS 2013

Keynotes October 1, 2013 Opening Ceremonies: Annual Business Meeting, Awards Ceremony, Keynote 11:00 AM – 5:00 PM 11:25 AM – 11:40 AM 11:40 AM – 12:00 PM

Exhibit Hall Open Annual Business Meeting IMAPS Society Awards Ceremony

12:00 PM – 12:45 PM

TUESDAY KEYNOTE: Next Generation of Electronic Systems - Challenges and Solutions for System Integration Technologies The use of micro-level integration technologies to manufacture high-end electronic systems has increased dramatically around the world, the potential for applications being almost unlimited. To enable a smart planet, driven partly by the internet of things, next generation of electronic systems are expected to be more energy efficient, highly miniaturized and multifunctional with embedded computing, communication and sensing functionalities. In order to achieve this goal, novel heterogeneous system integration technologies and design methodologies are needed. In this talk, some of the key system integration technologies required for the development of next generation electronic systems will be discussed. The focus will be on 3D wafer level packaging, panel level packaging and on interposer technologies. An overview of innovative electrical, thermal and thermo-mechanical design approaches will also be given. Prof. Dr. -Ing. Dr. sc. techn. Klaus-Dieter Lang - Klaus-Dieter Lang is a Professor with the School of Electrical Engineering and Computer Sciences at the Technical University Berlin, Germany, where he leads research activities in the area of Nano Interconnect Technologies. He is also Director of the Fraunhofer Institute for Reliability and Microintegration, IZM, Berlin. Professor Lang began his career as a Research Engineer at Humboldt University Berlin, where he spent 10 years (1981 to 1991) working in the areas of Microelectronic Assembly, Packaging and Quality Assurance. In 1991, he moved to SLV Hannover to build up a Department for Microelectronic and Optic Components Manufacturing. He joined Fraunhofer IZM 20 years ago and was initially responsible for R&D activities in the area of Chip Interconnection Technologies. From 2001 to 2005 he coordinated Fraunhofer IZM’s Lab on Microsystem Engineering in Berlin-Adlershof, and from 2003 to 2005 he was Head of the Department of Photonic and Power System Assembly. In 2006, he was appointed as Deputy Director of Fraunhofer IZM, a position he held until 2010. Since 2011 he has been Director of the Institute. Professor Lang Chairs the German Chapter of IEEE-CPMT and he is a member of numerous scientific boards and conference committees. He is the author and co-author of 3 books and more than 130 publications in the field of Wire Bonding Technologies, Microelectronic Packaging, Microsystems Technologies and Chip-on-Board Technologies. He studied Electrical Engineering at the Humboldt University Berlin, and holds a Master’s degree and two Doctorate degrees.

12:45 PM – 2:00 PM

Lunch Break (Food not provided by IMAPS Today) Orlando, Florida 20


IMAPS 2013 October 2, 2013 9:00 AM – 7:30 PM 12:15 AM – 1:30 PM

Exhibit Hall Open Lunch in Exhibit Hall (Lunch Provided by IMAPS & Sponsors)

11:20 AM – 12:05 PM

WEDNESDAY KEYNOTE: Progress in Developing an Open Supply Chain for 2.5D/3D Market Enablement An open supply chain requires close collaboration, early investment, and focus on the ultimate goal of yield and cost to enable markets. An open supply chain is more complex to develop but will provide the end-customer with the most flexibility and transparency and enables use of expertise in each stage of the supply chain. An open supply chain also requires high levels of sharing, not typical in our industry. Significant progress has been made in test chip development, TSVs, interposers, test strategy, yield, and cost. Data and remaining challenges will be presented in each of these areas. The relationship between memory architecture and cost will also be discussed. David McCann is Vice President of Packaging at GLOBALFOUNDRIES in Malta, New York. In this role, David is responsible for Packaging R+D, interconnect development, and back-end strategy and implementation. David started at GLOBALFOUNDRIES in 2011. Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, in product group and development roles. He also led cross-functional teams including networking product strategy and mobile product development. David has supported the Electronic Component and Technology Conference for more than 10 years. He was General Chair in 2012. David McCann received his Masters in Engineering Management from Santa Clara University in 1985 and his BS in Ceramic Engineering from the University of Illinois in 1981.

October 3, 2013 THURSDAY 3D KEYNOTE PRESENTATIONS: 8:00 AM – 8:45 AM Micron’s Hybrid Memory Cube – the New Standard for Memory Performance Yole Développement research analysts project a $40B market for TSV-enabled 3D devices by 2017— nearly 10% of the global chip business. These projections rely heavily on leading technologies such as the Hybrid Memory Cube (HMC) which represents a fundamental change in memory construction and connectivity. HMC is a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. In this talk, the HMC concept is analyzed, exploring how the DRAM functions are re-architected to deliver a scalable, energy efficient system architecture, delivering extremely high performance and resiliency. The presentation will also address how innovative and disruptive solutions such as HMC require equally innovative tools, ecosystems and go-to-market strategies. Scott Graham - General Manager, Hybrid Memory Cube Technology Micron Technology, Inc. Mr. Graham joined Micron in 1994 as an applications engineer in the personal computing division. He has held various managerial positions within Micron and has spent the last 11 years in Micron’s memory products division, working on technical marketing for DRAM and NAND memory products. In recent years, Mr. Graham has represented Micron in various organizations responsible for setting industry standards, holding numerous vice-chair, chair, and board-level positions. Mr. Graham holds a Bachelor of Science in Electronic Engineering Technology from DeVry University and a micro-MBA certification from Boise State University.

8:45 AM – 9:30 AM Overview of Critical 3D Integration Challenges to Bring Products to Market The widespread adoption of 3D Integration is inevitable with many companies introducing products into manufacturing or beginning the latter stages of development [1-3]. In this talk, we will discuss three focus areas that need improvement and cost reduction in order to bring 3D integration into the mainstream. A critical issue that CNSE is currently investigating is thin-wafer handling, which presents many problems in terms of process handling of thinned wafers, debonding from carrier wafers, cleaning, dicing, and shipping. Each of these process steps pose some risk of wafer breakage or defects that decrease process yield and increase final costs. This remains as a significant challenge for the up scaling and mass production of 3D integration products. These challenges and potential solutions will be discussed in this presentation.

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IMAPS 2013 continued from page 21

Keynotes... The other area that is of high interest to the 3D community is the bonding method used to connect each layer of a 3D stack. Three types of bonding methods are examined: copper-to-copper (Cu-Cu) direct thermo-compression (TC) bonding, transient liquid phase bonding (Cu - Sn on Cu), and solder bonding. The benefits, cost, and technical obstacles of these techniques will be discussed. Finally, important challenges for Assembly and Test ( with respect to OSATs) will be discussed. There is a significant gap between semiconductor manufacturing and OSATs with regards to 3D integration. Large Fabs have solved this issue in-house with fully integrated semiconductor and packaging solutions. However, the roadmap for the rest of the industry is unclear for packaging of 3D integrated die. This item will be discussed in terms of the expanding role of OSATs that will be required in order to successfully bring 3D integration products into the marketplace. Douglas Coolbaugh - Derivatives and 3DI Manager College of Nanoscale Science and Engineering (CNSE) at Albany SUNY Nanofab Douglas Coolbaugh received his PhD in Physical Chemistry from SUNY Binghamton, NY in 1987. Doug retired from IBM in 2010 after working 30 years in microelectronics development. Presently he is Assistant VP of derivatives at the College of Nanoscale Science and Engineering.

9:30 AM – 10:15 AM Contributing to 3D Interconnect (3DIC): One Toolmaker’s Approach to Meeting the Challenge For the last five of six years, identifying the requirements and metrics to meet 3D Interconnect high volume manufacturing (HVM) readiness has been a moving target. Will 3DIC happen in the front end of the line, advanced packaging or somewhere in between? From a toolmaker’s perspective, it is easy to get confused. It is a management challenge to fund programs one year that are redefined the following year. Finding solutions that will facilitate the transition to 3DIC is our professional obligation as responsible equipment manufacturers and corporate citizens. At TEL NEXX, we see cost effective solutions as the most significant challenge to 3DIC implementation. During this talk, I will share two of the approaches we used at TEL NEXX to identify and test proposed 3DIC solutions. The first method has been to collaborate with our suppliers transparently in order to speed up development lifecycles and minimize scale up costs. The second method has been to explore alternative solutions outside of the traditional unit process flows in search of disruptive technologies. These strategies helped us offer our customers a path to progress towards 3DIC HVM readiness. Tom Walsh - President TEL NEXX at Tokyo Electron Dr. Tom Walsh is President of TEL NEXX at Tokyo Electron, a leading worldwide semiconductor equipment provider focused on building advanced packaging tools. Walsh led teams of semiconductor professionals to successfully deliver game changing technologies to the market, including the growth and eventual sale of NEXX Systems to Tokyo Electron for Advanced Packaging Deposition (2012), the development of the Novellus Sabre Plating system for Copper Interconnect (1998) and the commercialization of the IBM Atomic Force Microscope (1993). Over the past 25 years, Walsh held roles from scientist to corporate executive at IBM, Novellus and NEXX Systems. He holds a Ph.D. in analytical chemistry from Purdue University and an MBA from the Stern Business School at NYU.

46th International Symposium on Microelectronics September 29-October 3, 2013 Orlando, Florida 22


IMAPS 2013

Technical Program-at-a-Glance Tuesday, October 1, 2013 INTERPOSERS & 2.5/3D PACKAGING


TSV Materials & Processes

Design & Analysis for Reliability

Chairs: Gabriel Pares, CEA; Sesh Ramaswami, Applied Materials

Chairs: Stevan Hunter, ON Semiconductor; Gopal Jha, Avago Technologies



Advanced Materials & Novel Assembly Processes

Pb-Free Solder & ROHS

Chairs: Erica Folk, Northrop Grumman; Yoon-Chul Sohn, Samsung Advanced Institute of Technology

Chairs: John Bolger, Department of Defense; John Pan, Cal Poly State University



Medical Device Packaging

European Perspective on Packaging Trends

Chairs: Sean Ferrian, Ferrian Sales & Associates; Kedar Shah, Lawrence Livermore National Lab

Chairs: Andre Rouzaud, CEA LETI; Martin SchneiderRamelow, Fraunhofer IZM

Emerging Technologies

Asian Perspective on Electronic Packaging and System Integration

2:00 PM—6:35 PM Advanced Platform Integration

Modeling and Design for SI and Reliability

Chairs: Urmi Ray, Chairs: Chris Pan, Qualcomm; Kyu-oh Lee, Intel Qualcomm; Judy Priest, Cisco

Polymers, Underfill, Encapsulants and Adhesives Chairs: Jeff Gotro,Innocentrix; Lyndon Larson, Dow Corning

Wednesday, October 2, 2013 Packaging Transitions: 2.5D and 3D Interconnect Technologies from Wire Bond to RDL to TSV Chairs: Vivek Ramadoss, STATS ChipPAC; Cristina Chu, TEL NEXX

Thermal and ThermoMechanical Modeling Chairs: David Saums, DS&A LLC; Mary Cristina Ruales Ortega, University System Ana G. Mendez

Wirebonding & Stud Bumping Chairs: Dan Evans, Palomar Technologies; Lee Levine, Process Solutions Consulting

Chairs: Susan Bagen, Endicott Interconnect; Igor Prikhodko, Analog Devices

Chairs: Tae-Kyu Lee, Cisco; Woongsun Lee, SK Hynix

8:00 AM—11:15 AM

Substrate Materials I

Flip Chip Bumping

Chairs: Michael Folk, Northrop Grumman Corp.; Jeff Hartman, Northrop Grumman Corp.

Chairs: Andy Strandjord, Pac Tech USA; Nick RenaudBezot, AT&S

New Concepts, Interconnects & Processes for High Performance Packaging Chairs: Benson Chan, Endicott Interconnect; Ron Lasky, Indium Corporation

Power Packaging I Chairs: Mark Hoffmeyer, IBM Corporation; Doug Hopkins, North Carolina State University

2:00 PM—5:30 PM Glass Interposers Chairs: Steve Annas, Triton Micro Tech; Aric Shorey, Corning Inc.

Testing Methods and Process for Improved Reliability Chairs: Mike Ferrara, RF Micro Devices; Akhlaq Rahman, Thin Film Corp.

Substrate Materials II (Ceramic & LTCC)

MEMS & Sensor Packaging

Chairs: Dan Krueger, Honeywell FM&T; Ken Peterson, Sandia National Labs.

Chairs: Matt Apanius, SMART Commercialization Center for Microsystems; Ron Jensen, Honeywell

Thursday, October 3, 2013 Technologies and Methods for 2.5/3D Packaging and Integration Chairs: Anwar Mohammed, John Hunt, ASE US

Think Thin: Thin IC Packaging For Mobile Devices Chairs: Rich Rice, ASE; Jason Cho, ASE; Milind Shah, Qualcomm

Bonding Materials and Processes

LED and Optoelectronics Printed Electronics & Packaging Additive Manufacturing

Chairs: Xiaoguang “Leo” Liu, University of California, Davis; Fred Barlow, University of Idaho

Chairs: Maria Durham, Indium Corporation; KlausDieter Lang, Fraunhofer IZM

Chairs: Tolga Tekin, Fraunhofer IZM; Luu Nguyen, Texas Instruments

Tuesday • 12:00 PM – 12:45 PM

KEYNOTE: Next Generation of Electronic Systems - Challenges and Solutions for System Integration Technologies

Prof. Dr. -Ing. Dr. sc. techn. Klaus-Dieter Lang - Klaus-Dieter Lang, Professor, School of Electrical Engineering and Computer Sciences at the Technical University Berlin, Germany

Wednesday • 11:20 AM – 12:05 PM

KEYNOTE: Progress in Developing an Open Supply Chain for 2.5D/3D Market Enablement

David McCann, Vice President of Packaging, GLOBALFOUNDRIES, Malta, New York

Chairs: Julie Adams, UBOTIC Company Ltd.; Mark Hoffmeyer, IBM Corporation

1:00 PM—5:00 PM

RF and Microwave Packaging

Keynotes and Panel Discussion

Power Packaging II

Chairs: Mike Newton, Newton Cyberfacturing; Yiliang Wu, Xerox Research Centre of Canada

Electronic Packaging for Harsh Environment Applications Chairs: Aicha Elshabini, University of Idaho; Tom Buschor, Harris Corporation

Wednesday • 12:30 PM – 1:00 PM

GLOBAL BUSINESS COUNCIL (GBC) Keynote Luncheon & Market Forecasting Analyst Session - The Microelectronics Industry in Brazil

Claudius Feger, IBM Research – Brazil, [email protected]

Thursday • 8:00 AM –10:15 PM

8:00 AM – 8:45 AM Micron’s Hybrid Memory Cube – the New Standard for Memory Performance 8:45 AM – 9:30 AM Overview of Critical 3D Integration Challenges to Bring Products to Market 9:30 AM – 10:15 AM Contributing to 3D Interconnect (3DIC): One Toolmaker’s Approach to Meeting the Challenge




IMAPS 2013

Natel’s First Annual Supplier of the Year Awards NATEL EMS will recognize 13 of its best suppliers Monday evening, September 30, 2013, with its First Annual Supplier of the Year awards during IMAPS’ 46th annual International Symposium Welcome Reception. The awards presentation will be held at the Rosen Centre Hotel in Orlando, FL. “The Supplier of the Year award winners represents a partnership, dedication and commitment to consistently perform above expectations. This has played an important role in Natel’s success,” said Sudesh Arora, President of Natel EMS. “We appreciate the efforts of these suppliers and look forward to a mutually-beneficial continued relationship in the future.” The awards recognize the significant contributions of Natel suppliers as part of the company’s product and performance achievement. The winners represent Natel’s view as the best the microelectronics/electronics industry

has to offer in innovative technology, superior quality, outstanding launch support, crisis management and competitive total enterprise cost solutions. The Supplier of the Year winners are chosen by the Natel team of purchasing, engineering, quality, manufacturing and logistics executives. Contact: Jim Angelonu [email protected] 818-27401908

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IMAPS 2013

2013 Symposium Student Programs Please consider participating in the IMAPS 2013 Student Programs. IMAPS leaders have designed the programs listed below to provide students with technical information, industry insight, and valuable connections. Please see more conference information at or contact Brianne Lamm at [email protected] for further benefits of participating.

2013 Student Activities Chairs: Venky Sundaram Georgia Tech University PRC [email protected]

Mike Newton

Newton Cyberfacturing [email protected]

Professional Development Course (PDC) Monitor:

Students have the opportunity to serve as a PDC Monitor and attend the course free of charge. Monitor must be a full time student and are assigned on a first-come basis. Sign up early by e-mailing Brian Schieman (bschieman@ with your top three choices no later than September 6.

Plant Tour — Micross Components:

Micross Components will provide a valuable industry tour that will highlight two of its facilities in Orlando. Micross Components is a leading global provider of distributed and specialty electronic components for military, space, medical, and demanding industrial applications. Operating as a single source for high reliability and state of the art electronics, Micross™ solutions range from bare die and wafer processing to advanced and custom packaging to component modifications and related interconnect offerings. With a 35+ year heritage, Micross possesses the design, manufacturing and logistics expertise needed to support an application from start to finish. The plant tour is set for Wednesday, October 2: bus leaving Rosen Centre at 11:30am and returning by 2:00pm (subject to change).

The Micross Tour is open to US Citizens ONLY. Students and industry professionals are welcome to participate. Micross will manage the approved attendee list and communicate with registrants as the tour approaches. Welcome Reception:

The reception offers a good opportunity for students and advisors to talk with industry professionals in a relaxed setting to build relationships and gain valuable information.

Ege Engin

San Diego State University [email protected]

Student Poster Competition:

Student authors can deliver poster presentations in the University Poster Session that will be evaluated on technical content, and presentation skills. Winning students will receive cash prizes that total $500 and recognition in IMAPS publications.

Student Chapter Booth Competition:

Highlight your academic research and programs at your student booth. Gain advice and recognition from industry leaders. Student booths will be evaluated by a panel of judges on various criteria. Booth space is complimentary for IMAPS student members. Winning student booths will receive cash prizes that total $750 and recognition in IMAPS publications. Please contact Brianne Lamm ([email protected]) for more information or to reserve your complimentary booth. Booth judging will be on Tuesday, October 1, 1:30 pm to 2:30 pm (Tentative).

Student Chapter Meeting:

Gain more insight and share your success on increasing membership and producing better programs with other student chapter leaders. Learn ways to gain more chapter funding. Join in on Tuesday, October 1, 2:30 pm - 3:30 pm (Tentative).

Student Industry Panel/Reception:

The student-industry panel will provide good advice to students on job hunting, career development, and market insight. Industry leaders and professional engineers will describe and discuss how their education, expectations, and early career experiences led to their mid-level successful careers. A reception will immediately follow when students can talk directly with the industry panelists. Join us on Tuesday, October 1, 3:30 pm to 5:30 pm (Tentative).

Employment Center:

IMAPS offer an online JOBS Marketplace for posting resumes, searching job openings, and more: http://jobs.

Student Paper Competition:

Selected student authors can deliver paper presentations that will be evaluated on technical content, presentation skills, and the written manuscript. Winning students will receive cash prizes that total $3000 and recognition in IMAPS publications.




IMAPS 2013

GBC Keynote Lunch Sponsored by Sikama:

GLOBAL BUSINESS COUNCIL (GBC) Keynote Luncheon & Market Forecasting Analyst Session Wednesday, October 2, 2013 - in the Junior Ballroom 12:30 PM: Welcome Message, GBC Objectives and Agenda Review - Lee Smith, Plexus Corp. GBC Lunch Sponsored by: Sikama - GBC Sponsor

12:40 PM - 1:00 PM: GBC Luncheon & Keynote Speaker: The Microelectronics Industry in Brazil Claudius Feger, IBM Research - Brazil [email protected] As Brazil’s middle class has increased by 35 million people, electronics imports have skyrocketed - resulting in a narrowing of Brazil’s trade balance, which in January 2013 turned negative. To address this trend, the Brazilian government made the development of a local microelectronics industry an economic priority. Previously, the government focused on developing IC design skills and the creation of design houses, of which 22 were established to-date. However, the success of these has been limited, mostly because of difficulties in attracting industrial projects and thus over half of the existing design houses are not for profit. With the announcement in late 2012 of the creation of SIX Semicondutores, an IDM which once completed, will be the most advanced, commercial chip manufacturer in Latin America, the Brazilian microelectronics industry started a new chapter. SIX Semi will be using IBM 130 and 90 nm technology to provide advanced mixed signal / hybrid semiconductor devices and products for the medical devices, smart card, sensor, energy management and similar markets. In doing so, Brazil hopes to start making a dent in the import of about US$4 - 5 billion annual imports of ICs. Another focus area is electronic packaging. But even after the announcement in 2012 of HT Micron (a joint venture between the Brazilian Altus and the Korean Hana Micron), this area will remain poorly served in Brazil, because HT Micron will focus exclusively on the highly competitive memory packaging segment. Over the years the Brazilian government has instituted several laws and regulations to support the formation of an electronics industry with Brazilian content. This spans efforts from creating academic programs and research institutions to laws requiring industrial research investments to direct investments by the Brazilian development bank in industries. However many hurdles remain. 26

This talk will describe successes and hurdles in the development of a successful microelectronics ecosystem in Brazil and will provide an up-to-date picture of this important emerging market.

1:00 PM - 2:00 PM: Industry Analyst & Panel Discussion “Addressing Major Changes in the Supply and Demand for Advanced Packaging Technologies” 1:00 PM - 1:20PM: “Demand Outlook for 2.5 / 3D and Wafer Level Packaging” Yole Développement - Christophe Fitamant, Sales & Marketing Director mm Technical trends for 2.5 / 3D, Wafer level packaging (fan in and fan out) and embedded chip in substrate; mm Associated driving applications and demand outlook over the next 5 years.

1:20 PM - 1:40 PM: “Supply Chain Implications for Advanced Packaging” Gartner Dataquest - Mark Stromberg, Senior Director mm Impact on supply chain associated with these trend to new technologies with high wafer level process content; mm Equipment trends to service these technologies and economic impact on OSATs as these wafer level processes have high capex $, with long lead times and major step function in capacity to manage; mm (Tentative) SWOT or comparison between tier 1 OSATs and Foundries that will both collaborate and compete in this space.

1:40 PM - 2:00 PM: Panel Format with Audience Questions & Answers Moderator - Lee Smith


IMAPS 2013

IMAPS 2013 Professional Development Courses (PDCs) NEW PDC Format This Year! PDCs will no longer be held on Sunday Now Offering PDCs on Monday, September 30 and Thursday, October 3 Monday, September 30 - PDCs run 9:00 am - 5:00 pm Thursday, October 3 (half-day ONLY) – PDCs run 8:00 am - 12:00 pm 3D Power Electronics...(NEW); Sensor Products Packaging...(NEW); Flexible Optical Media...(NEW); Reliability Data Analysis...(NEW); MEMS & Microsystem Packaging...(NEW); 2013 Packaging Advances, Updates & Trends...(NEW); Embedded Chip Packaging; Polymers in Electronic Packaging; Signal/Power Integrity; Screen Printing; High-Temperature Electronics; Wire Bonding; Package on Package (PoP)…; and many more. Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today’s competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provides detailed information on topics of immediate interest to the Microelectronics and Packaging community. So please be sure to choose from the menu of in-depth Professional Development Courses taught by recognized industry experts. You will discover the following key ways that will benefit you:

• Better understand the skills and knowledge necessary in today’s industry. • Be exposed to the rapidly expanding developments in new materials and technologies. • Consult with renowned authorities about your current R&D or manufacturing problems and challenges. • Learn new ways to identify, think about, and address your problems and opportunities. • Great opportunities to interact with industry experts and other course attendees. • Certificate of Attendance and much more!

Your PDC Registration Fee Includes: • • • •

Lunch on the day of your course (MONDAY ONLY) Refreshment breaks All course materials Certificate of Attendance

PDC Lunch sponsored by:

PDC Program and Registration On-Line at PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.




IMAPS 2013

19th Annual IMAPS Golf Classic to benefit the Microelectronics Foundation Monday, September 30, 2013 Shingle Creek Golf Course

8:00am Shotgun Start - “Best Ball” Scramble Shingle Creek Golf Club 9939 Universal Blvd | Orlando, Florida 32819 407-996-9933 | The IMAPS Microelectronics Foundation Fall Golf invitational will be held at the Shingle Creek Golf Club. Experience this remarkable new Orlando golf course, which takes its name from the pristine creek, that traverses the property. Early Central Florida settlers, circa 1800, were drawn to the area by the abundance of game, fishing, ancient cypress trees, and of course, the beautiful creek.

Cost is $125 per person.

• $450 for a team of four; $750 for a team of four including a hole sponsorship. • $500 for one individual golfer and 1 hole sponsorship. The cost includes: Transportation to and from the course, greens/cart fees, shotgun start, and a breakfast/lunch — TBD.

All proceeds from this event will benefit the IMAPS Microelectronics Foundation.

Special Awards and Activities tentatively planned: Closest to the Pin • Longest Drive • Mulligans for sale! Golfers will tee off shortly after arriving at the course. Times are tentative and will be confirmed before the outing. Callaway rental clubs are available for $50 plus tax.

Sponsors receive signage, on-line recognition, and other benefits as defined on the sponsorship page. Contact David Virissimo, IMAPS 2013 Foundation Chair, with questions - David.Virissimo@ Or contact Brian Schieman, IMAPS, at [email protected].

Sponsorship Opportunities: Eagle Sponsor - $3,000 • • • •

Golf “Birdie” Sponsor:

Entrance of two four-somes. Includes three hole sponsorships with signage. Company logo/name on all event promotional signs, materials and website. Company may provide take-away products to be handed to all golfers. Golf-related items usually most appropriate (e.g., golf towels, balls, tees, etc.). At expense of sponsor.

Birdie Sponsor - $1,500 — 1 SOLD

Hole Sponsor:

• • • •

Entrance of one four-some. Includes one hole sponsorship with signage. Company logo/name on all event promotional signs, materials and website. Company may provide take-away products to be handed to all golfers. Golf-related items usually most appropriate (e.g., golf towels, balls, tees, etc.). At expense of sponsor.

Hole Sponsor - $500 ($750 w/ four-some) — 17 Holes Remain


• Sponsorship of one hole with signage. • Entrance of one golfer ($500) or one four-some ($750). • Company logo/name on promotional materials and website.






iKnow Micro iKnow Micro is the IMAPS on-line library that provides a centralized, searchable database of the papers, publications, and presentations that IMAPS produces. This is a great benefit for IMAPS members as it is a valuable tool to get information fast. Expand your knowledge and research abilities today by logging-in at iKnow Micro currently contains more than 2,700 articles and publications from symposia, conferences, workshops, web meetings, and other publications from 2003 through 2010. IMAPS will continue to incrementally load additional historical publications. iKnow Micro contains the following publications in a downloadable, cd-rom, and/or printed format: • Journal of Microelectronics & Electronic Packaging – Individual papers and full issues • Advancing Microelectronics – Full issues • IMAPS Symposium Proceedings – Individual papers and full proceedings • IMAPS Conference Proceedings – Individual papers (or slides) and full proceedings • IMAPS Workshop Presentation Slides – Individual slides (or papers) and full publications • Global Business Council Presentations – Individual slides and full publications • Podcasts – Downloadable files from past IMAPS webcasts • Reference Textbooks – Print editions of several industry reference books All of the publications contained within iKnow Micro can be found using two search tools. All publications will have abstracts and/or descriptions viewable. Download prices are: • IMAPS Members: $ 0 per article/download. • Non-Members: $ 10 per article/download. Full manuscripts, proceedings, presentation slides, cd-roms, magazines, journals, and/ or books will be available for purchase only. IMAPS members will receive discounted pricing on all the products in the on-line library. The Journal of Microelectronics and Electronic Packaging and Advancing Microelectronics magazine publications will remain complimentary to IMAPS members only. iKnow Micro is just one of many benefits that provide great value to members. Please visit for a full list of member benefits.




Individual Member Benefits Discounts on events, webcasts, publications, and iKnow Micro downloads • Take discounts on the Annual Symposium and many technical workshops. • Take discounts on convenient, informative IMAPS webinars; • Complimentary on-line library downloads,

Advancing Microelectronics Magazine •

Enjoy a one-year subscription to Advancing Microelectronics.

IMAPS Chapter Membership • Learn from technical and management presentations by local and national experts. • Create and build relationships with industry peers through regional programs.

Access the Journal of Microelectronics and Electronic Packaging • View the Journal of Microelectronics and Electronic Packaging on-line.

Access to JOBS Marketplace Post resumes and search for current job openings. • Keep records easily - results and actions are conveniently recorded. • Enjoy helpful features of many expensive job search engines.

Access to “Members-Only” sections on • Find individuals and companies that provide products and services. • Enter your own professional listing.

Visit or call 919-293-5000 31




IMAPS Premier Membership for Microelectronics Companies Many companies active in IMAPS programs and events now enjoy considerable savings on promotional offerings and technical information offered under the new IMAPS Premier Membership. Companies can take advantage of up to $8,300 in member discounts. Please review the table below for a benefits comparison of the two corporate membership types.

Corporate Membership Type:


Premier Corporate

Full Corporate

Exhibit Discount

Member Discount


Member Discount


IMAPS Individual Memberships with Print Magazine





IMAPS Individual Membership Benefits without Print Magazine


$375 Assuming at least 5

Not included


Use of the IMAPS membership mailing list

3 times per membership year


Once per membership year


One quarter-page magazine advertisement



Not Included


Additional advertisement in magazines

15% Discount


15% Discount


Advertisement on IMAPS website

12 Months Complimentary


Member Discount


Email Advertisement in the Weekly Bulletin

3 Continuous Months


Member Discount


Press Releases in the Corporate Bulletin

Up to 1 PR in each Corp Bulletin (twice monthly)


Up to 1 PR in each Corp Bulletin (twice monthly)


Downloads from iKnow Micro, on-line technical library

IP recognition allows unlimited downloads for all computers at one network or office


2 members may download at no cost.


Global Business Council Membership





Webinar Sponsorship

30% discount


10% discount


JOBS Marketplace

Complimentary Job postings


Complimentary Job postings


On-line Industry Guide

Includes company listing, link to website, product & service categories.


Includes company listing, link to website, product & service categories.


Access to Information

Includes iKnow Micro, Advancing Microelectronics, on-line Journal, “Members Only” section


Includes iKnow Micro, Advancing Microelectronics, on-line Journal, “Members Only” section


Total value of full use



Annual Dues:




Savings $8,300

Savings $3,625



Premier Corporate Members IMAPS has introduced a new level of support for corporate members. These companies have decided to participate in our Society at the Premier Corporate Member level. We are extremely grateful for their dedication to the furtherance of our educational opportunities and technological goals.





Your IMAPS Member Benefits at Your Chapter Level Your participation in these IMAPS chapter events greatly increases the value of your member benefits by providing industry insight, technical information, and networking opportunities. See more event information at

Chesapeake Chapter The IMAPS Chesapeake Chapter held its Summer Technical Symposium on August 7th at the Johns Hopkins Applied Physics Labs. There were three technical presentations followed by dinner. The presentations included the following: “Thin Wiring Substrate with Integrated Inductor for Ultra-Compact Power Management” by Dr. Christopher Meyer of the Army Research Laboratory; “High Temperature Joining for High Reliability Power Modules” by Dr. F. P. McCluskey of the University of Maryland CALCE Labs; and “Wedge Bonding RF and Microwave Devices” by Mr. Lee Levine of Process Solutions Consulting, Inc. The event was well attended and included a number of student attendees from the IMAPS Student Chapter at the University of Maryland.

Cleveland-Pittsburgh Chapter On June 25, the Cleveland-Pittsburgh Chapter met at the Advantech US facility in Pittsburgh. We are settling into our routine of two or three action-packed meetings per year. We had four technical presentations: Scott Lauer talked about Advantech US’ capability in additive manufacturing of electronics; Don Styblo of Valtronic covered the next generation of smart implants, and also Valtronic work in glass encapsulation of electronics / optics for medical devices. Tim Schmitt of Compunetics showed results of his testing of additive layers mixed with etched layers in a multilayer PWB directed at high reliability applications. Jason Steele, who teaches technology education at Oblock Junior High, covered how his students are using 3D printing. He is using his classroom 3D printer to make parts for more printers—he is now up to five printers!


We enjoyed a wonderful dinner that concluded with a tour of Advantech US. We saw the world’s first LCD television, originally made at Westinghouse, using additive layers for the display. Advantech US has a process with the capability to deposit conductors, insulators, embedded passives, and embedded active devices. It is also able to provide hybrids on which surface mounted devices can be assembled.

Northern California Chapter The Northern California Chapter had the pleasure of hosting a presentation on Diagnosis of Advanced Packaging by Ted Lunquist, PhD, CTO DCG Systems. This talk centered on the blurred boundary between die and package in advanced packaging. In complex packaging systems, a completed IC extracted from its packaging cannot be expected to function to specification. Test is essential for the completed IC but test only looks at output versus input as per plan and what happens in between is a “black box.” Challenges to the analysis of advanced packaging, as well as methods to extract information beyond test were reviewed. Localization within the stack is most challenging, but also most important; thus emphasis was given to detailing the localization methodology in Z as well as X & Y. In particular the presentation reviewed solutions offered by lock-in thermography (LIT), including case studies on several different types of stacked die including: stacked wafer chip-scale package (WCSP); system in package (SIP); and TSV. Present stacked die Z-resolution is < 25 mm. The presentation was well received and drew attendance from new companies. As advanced packaging continues to migrate to meet complex system performance requirements of “More than Moore,” debug and other diagnostic technologies will become more significant to innovation in packaging development.





STUDENT CHAPTER NEWS Binghamton University, Binghamton, NY

North Dakota State University

2013 Electronics Packaging Symposium Technology Advances in Small Scale Systems and Microelectronic Packaging

First IMAPS NDSU Microelectronics Summit on October 18, 2013

The iMAPS Student Chapter at Binghamton University will be participating at the 2013 Electronics Packaging Symposium to be held October 15-16, 2013 at Binghamton University in Binghamton, NY. The symposium is sponsored by the Integrated Electronics Engineering Center, a New York State Center for Advanced Technology at Binghamton University, General Electric Global Research, and IEEE CPMT. There will be four keynote speakers and a dinner speaker. Technical session topics include Medical Electronics, Thermal Challenges, 3D Packaging, Sensors/MEMS, Power Electronics, High Temperature Electronics, Miniaturization, and Flexible/ Printed Electronics. More information is available at:


The summit will be held at the Research 1 building on NDSU Research Park Drive in North Dakota State University (NDSU) at Fargo ND. There will be a student poster contest sponsored by IMAPS. A technical meeting will include presentations from electronics industry leaders in the Red River Valley Research Corridor. A tour of the Center for Nanoscale Science and Engineering (CNSE) will be offered. CNSE houses design, modeling, manufacture, testing and characterization facilities for thin film, thick film, semiconductor packaging and surface mount technology. Lunch and refreshments are included in registration For additional information concerning the summit, please contact Syed Ahmad ([email protected]).



Welcome New IMAPS Members! May-June 2013

Organizational Members Colorado Microcircuits, Inc. ENrG, Inc. Woodward Individual Members Anderson, Nash Antczak, John J. Arkin, Michael Armendariz, Carol Beckwith, Robin Bennett, Paul Bowden, Neil Kevin Buchan, Kevin Caliari, Luca Chailloux, Thibaut Chaves Cleverson, Souza Cilip, Claire DeWaters, Steve DiMarino, Christina Marie Dinning, Scott Dreiner, Stefan Eberl, Ronald Elyasi, Mehrdad Fujishima, Naoto Gade, Samyukta Ghandi, Reza Gibson-Ford, Matthew Gore Jonathan

Gouin, Sebastien Habenicht, Soenke Henriksen, Sigurd Horvath, Stephen I Made, Riko Johnson, Dorian Johnson, Richard J. Kane, Michael Kaplar, Robert Kato, Fumiki Kern, Richard A. Khanna, Ramesh Kneedler, Blake Ko, Wen H. Kolberg, Sigbjorn Lamm, Brianne Lamprell, Ian Lanni, Luigia Laurent, Lengignon Li, Liang Mason, Bryon Masyukov, Alexey Matsubara, Norie McNutt, Ty Menon, Kalyani Milton, Christopher Myall, Rod Nagatomo, Hiroyuki Newton, John Noergaard, Anders Just

Ocana, Ibon Olejniczak, Kraig Joseph Paknejad, Seyed Amir Peddireddy, Durga Perry, Anthony Pihl, Joachim Pike, Christopher Prince, James Roberts, Donald Roberts, John Rudd, Jonathan Brian Sandy-Smith, Brook Sather, Jeff Schmidt, Alexander Sharma, Shashi Kumar Skarda, Lou

Staubli, Paul Steen, Hector Stribley, Paul Symons, Pete Tachibana, Ichiro Tolla, Bruno Trinh, Hung Turovskiy, Michael Vane, Mark Viswanathan, Ram Wilkinson, Brian Wille, Christian Wilson, David Zhang, Qiao

High Reliability Cleaning With Brands That Matter



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46th International Symposium on Microelectronics September 29-October 3, 2013

Scan QR Code For Product Brochure Advanced Products For Advanced Cleaning A Vantage Specialty Chemicals Business [email protected] 800-432-7187 Orlando, Florida 37










ANGEL - Los Angeles

Maurice Lowery

Northrop Grumman Corporation

[email protected]



Greg Clemons

Intel Corporation

[email protected]



Katrien Vanneste

University of Ghent - IMEC

[email protected]


Scott Morris

Skyworks Solutions, Inc.

[email protected]


Bennett Joiner

Joiner Consulting

[email protected]


Erica Folk

Northrop Grumman Corporation

[email protected]



Ken Burke

GE Healthcare

[email protected]



John Mazurowski

Pennsylvannia State University

[email protected]


EMPIRE - New York State

Benson Chan

Endicott Interconnect

[email protected]



Doug Bokil

Namark Process Design, LLC

[email protected]



Bradford Factor

ASE Europe

[email protected]


David Seeger

IBM Corporation

[email protected]


Markus Detert

Otto-von-Guericke University

[email protected]


Neal Thomas

Servoflo Corporation

[email protected]



Marta Daffara

Pragma Congressi

[email protected]



Kishio Yokouchi

Fujitsu Interconnect Technologies, LTD

[email protected]


KEYSTONE - Philadelphia

Tom Green

TJ Green Associates LLC

[email protected]



Tae Sung Oh

Hongik University

[email protected]


Scott Baldassarre


[email protected]


Michael Gervais

Geib Refining Corporation

[email protected]



Petri Savolainen

Nokia Corporation

[email protected]



Anwar Mohammed

Huawei Technologies

[email protected]



Steve Kirby

Kirby & Demarest

[email protected]

ORANGE South Los Angeles

William Gaines

Northrop Grumman Corporation

[email protected]



Tim LeClair

TC Consulting

[email protected]



Bill Ishii

Torrey Hills Technologies, LLC

[email protected]



Long-shien Lin

Industrial Technology Research Institute [email protected]


Andrew Holland

Cambridge Silicon Radio Ltd

[email protected]


VIKING - Minnesota and Dakotas

Mark Hoffmeyer

IBM Corporation

[email protected]














Rick Short


[email protected]


Master Bond

Robert Micheals


[email protected]


Mini-Systems, Inc.

Craig Tourgee


[email protected]

back cover


Dr. Michael C. Savidakis


[email protected]


Sikama International, Inc.

Phil Skeen


[email protected]


Torrey Hills

Ken Kuang


[email protected]


Advancing Microelectronics 2013 Editorial Schedule Issue


Copy Deadline


Assembly, OSATs, SMT


Ad Commitment I/Os Deadline

Sep. 20

IMAPS HEADQUARTERS WHO TO CALL Michael O’Donoghue, Executive Director, (919) 293-5000, [email protected], Strategic Planning, Contracts and Negotiations, Legal Issues, Policy Development, Intersociety Liaisons, Customer Satisfaction, Exhibits, Meetings Brian Schieman, Director of Programs, (412) 368-1621, [email protected], Development of Society Programs, Website Development, Database Management, Communication Tools and other Technology, Exhibits, Publications Ann Bell, Manager, Managing Editor, Advancing Microelectronics, (703) 860-5770, [email protected], Public Relations, Marketing, Fundraising, Advertising, Advancing Microelectronics Brianne Lamm, Membership & Events Coordinator, (919) 293-5000, [email protected], Member Relations and Services Administration, Dues Processing, Membership Invoicing, Foundation Contributions, Data Entry, Mail Processing, Address Changes, Telephone Support




start end


9-9-13 9-12-13 EMPC 2013 - European Microelectronics Packaging Conference & Exhibition Grenoble, France 9-29-13 10-3-13 IMAPS 2013 - 46th International Symposium on Microelectronics Orlando, FL


11-5-13 11-7-13 Thermal Management Los Gatos, California


1-21-14 1-22-14 Topical Workshop & Tabletop Exhibition on Wire Bonding San Jose, CA


3-10-14 3-14-14 Device Packaging 2014 Scottsdale/Fountain Hills, AZ


5-13-14 5-15-14 International Conference on High Temperature Electronics (HiTEC 2014) Albuquerque, NM


10-12-14 10-15-14 IMAPS 2014 - 47th International Symposium on Microelectronics San Diego, CA

Walt Disney World Discounted Advance Purchase Tickets IMAPS has teamed up with Disney for a special offer for those attending IMAPS 2013 in Orlando. Have a little fun while visiting Orlando for our 46th Symposium. If you’re planning a trip to Walt Disney World® Resort during your participation at IMAPS 2013 Orlando in September-October 2013,

please visit for information about ordering tickets in advance, at the special conference rate!