DRAM Memory System: Lecture 3 Spring 2003

Memory System Organization

Bruce Jacob David Wang

Dimm1 Dimm2

Dimm3 Dimm4

University of Maryland

Single Channel SDRAM Controller

“Mesh Topology”

Addr & Cmd Data Bus Chip (DIMM) Select

DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang

DRAM System Organization Where is the data?

University of Maryland

Rank? Bank? Row? Column?

CPU

Request (Read) (Physical Address) (Cachline length = 64B)

Data

Data Magic Memory Controller Command Sequence

Rank Address = ? Bank Address = ? Row address = ? Column Address ?

DRAM Memory System: Lecture 3 Spring 2003

Rank Part 1

Bruce Jacob David Wang

Bank

Rank

University of Maryland

Magic Memory Controller

It’s a “bank” of chips that responds to a single command and returns data. “Bank” terminology already used.

DRAM Memory System: Lecture 3 Spring 2003

Rank Part 2

Bruce Jacob David Wang

Rambus RIMM Rank Count is Number of Devices

University of Maryland

SDRAM Double Sided Dimm Two Ranks SDRAM Single Sided Dimm One Rank SDRAM/DDR SDRAM system: 4~6 ranks RDRAM system: