Memory Hierarchy Motivation, Definitions, Four Questions about Memory Hierarchy, Improving Performance. Admin

Memory Hierarchy— Motivation, Definitions, Four Questions about Memory Hierarchy, Improving Performance Professor Alvin R. Lebeck Computer Science 220...
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Memory Hierarchy— Motivation, Definitions, Four Questions about Memory Hierarchy, Improving Performance Professor Alvin R. Lebeck Computer Science 220 ECE 252 Fall 2008

Admin • Some stuff will be review…some will not • Projects… • Reading – – – –

H&P Appendix C & Chapter 5 NUCA Software Fully-Associative Continual Flow Pipelines

© Alvin R. Lebeck 2008

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Outline of Today’s Lecture • • • • • • • • •

Most of today should be review…later stuff will not The Memory Hierarchy Direct Mapped Cache. Two-Way Set Associative Cache Fully Associative cache Replacement Policies Write Strategies Memory Hierarchy Performance Improving Performance

© Alvin R. Lebeck 2008

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Cache • • • •

What is a cache? What is the motivation for a cache? Why do caches work? How do caches work?

© Alvin R. Lebeck 2008

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The Motivation for Caches Memory System

Processor

Cache

DRAM

• Motivation: – Large memories (DRAM) are slow – Small memories (SRAM) are fast

• Make the average access time small by: – Servicing most accesses from a small, fast memory.

• Reduce the bandwidth required of the large memory © Alvin R. Lebeck 2008

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Levels of the Memory Hierarchy Upper Level

Capacity Access Time Cost CPU Registers 100s Bytes 1 / DRAM write cycle – If this condition exist for a long period of time (CPU cycle time too quick and/or too many store instructions in a row): » Store buffer will overflow no matter how big you make it » The CPU Cycle Time

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