Master-Slave Sliding-Mode Control Design in Parallel-Connected Inverters

ISSN 0005−1144 ATKAAF 42(1−2), 37−44 (2001) Rafael Ramos, Domingo Biel, Francesc Guinjoan, Enric Fossas Master-Slave Sliding-Mode Control Design in P...
Author: Opal Knight
1 downloads 0 Views 262KB Size
ISSN 0005−1144 ATKAAF 42(1−2), 37−44 (2001) Rafael Ramos, Domingo Biel, Francesc Guinjoan, Enric Fossas

Master-Slave Sliding-Mode Control Design in Parallel-Connected Inverters UDK 621.311.68 IFAC IA 5.5.4;4.7.1 Original scientific paper This work presents the design of a master-slave sliding-mode control scheme for a modular inverter system composed of N parallel-connected Buck-based single inverters. AC output voltage regulation and balanced current-sharing among the single inverters is achieved by means of a set of switching surfaces and the corresponding sliding control laws. On the other hand, a set of design restrictions is established in terms of inverter parameters and AC output signal amplitude and frequency, this facilitating the subsequent design procedure. Simulation and experimental results for both resistive and nonlinear loads are provided to illustrate the application of the method. Key words: buck inverter, master-slave, parallel modules, sliding-mode control

1. INTRODUCTION

Power management flexibility and reliability of power inverter systems can be improved when a modular structure resulting from the paralleling of single inverter modules is adopted. On one hand, the modular structure enables the total power increase of the power inverter system by increasing the number of inverter modules. Furthermore, for a fixed power capability, device stresses can be reduced by adding inverter modules, since the power density handled by each module is reduced. On the other hand, redundant modules can be included, this leading to fault-tolerant modular structures in the case of inverter module failure. Accordingly, the power inverter system reliability is improved [8–10]. However, parallel inverter modules are usually nonidentical due to the finite tolerances in the power stage parameters, this resulting in an unbalanced current-sharing among the modules. Consequently, one or more modules may handle an excessive load current. In order to prevent this problem, the Master-Slave control technique is one of the several control policies ensuring both the output voltage amplitude regulation and the desired current distribution among the power inverter modules [8]. This technique is based on the principle of that one of the inverter modules is constrained to behave as a sinusoidal voltage source (Master inverter), while the other modules behave as balanced current sources (Slave inverters). These requirements can be fulfilled on one hand, by means of the design of a voltage con-

AUTOMATIKA 42(2001) 1−2, 37−44

trol loop for the master inverter ensuring the tracking of an external sinusoidal reference signal. On the other hand, the balanced current sources behavior is performed by designing a current-control loop for each of the slave inverters, where the inductor current of the Master inverter acts as a current reference. This control policy has been generally applied to PWM-based parallel inverters [9]. In this case, the design of all the aforementioned control loops is based on a linearized power stage model, this leading to output waveforms sensitive to power stage parameter variations, such as the output load. Alternatively to PWM control strategies, and based on their robustness properties in front of parameter variations, sliding-mode control techniques have been applied to the control loop design of several power systems such as single switching DC-DC converters [4, 6], single inverters [2, 7] and to a central-limit control scheme for parallel-connected switching DC-DC power supplies [10]. The work here reported presents the design of a master-slave sliding-mode control scheme for an inverter system of N buck-based parallel-connected inverters. The paper is organized as follows: based on the master-slave control approach, section two introduces a set of switching surfaces and their corresponding sliding control laws leading to the desired steady-state behavior in the sense of output voltage regulation and balanced current sharing. Subsequently, in section three, the obtention of the overall inverter system sliding domain is derived in terms of the output filter Bode diagrams of each converter and the output signal parameters (ampli37

R. Ramos, et al.

Master-Slave Sliding-Mode Control ...

tude and frequency), this facilitating the subsequent design. Experimental results obtained in an electronic prototype of two parallel-connected inverters loaded with a nonlinear load are shown in section four. Finally, the last section summarizes the conclusions of the work.

The main goal of the control policy is to provide both AC output voltage regulation and balanced current-sharing among the inverter modules. In this work the sliding mode control technique has been adopted to achieve these control features due to its robustness in from of perturbations, namely variations of the input voltage and/or in the load [2, 7].

2. INVERTER MASTER-SLAVE SLIDING CONTROL

As far as the voltage regulation is concerned, the following switching surface proposed by Carpita et. al. [7] has been applied due to its independence to the converter parameters:

Figure 1 shows a power inverter system composed by N parallel-connected Buck converters.

g FGH dVd t (t) − ddvt IJK = α ⋅ e(t) + ded(tt)

b

σ = α ⋅ Vref ( t ) − vo +

ref

o

where Vref ( t ) = A ⋅ sin(2πft ) .

(2)

This switching surface will be assigned to one of the Buck inverters in order to track the AC voltage reference signal.

Fig. 1 Electrical scheme of N parallel-connected Buck power converters

The balanced current-sharing among the inverter modules can be performed by means of a Master-Slave control algorithm, in the sense of that the inductor current of the voltage-controlled converter (acting as a Master) is considered as the inductor current reference for the other inverter modules (Slaves).

The dynamical behavior of this system can be represented by the following state equation:

In terms of sliding mode control the following switching surfaces can be proposed to achieve the previous requirements:

R| diL = − rL ⋅ iL − 1 ⋅ v + E ⋅ u L L || ddiLt rLL || dt = − L ⋅ iL − L1 ⋅ v + EL ⋅ u || M || S| diLdt = − rLL ⋅ iL − L1 ⋅ v + EL ⋅ u || dv = 1 ⋅ iL + 1 ⋅ iL +K || dt ∑ C ∑C || 1 1 ⋅ iL − ⋅v K+ || I F C ∑ GH ∑ C JK R T 1

1

1

2

1

2

2

N

N

N

1

N

i

N

i=1

N

(1)

2

N

i=1

N

N

i

o

N

i

i =1

i

L

where ui designates the control input of ith-converter. The control variable ui takes values in the discrete set ui ∈ {1, −1} corresponding to a full bridge switch, this ensuring the bipolarity of the AC output voltage. 38

(3)

σ N ( t ) = iL1 ( t ) − iLN ( t ) (Slave).

N

o

N

o

M

2

N

d e( t ) + α ⋅ e( t ) (Master) dt

σ 2 ( t ) = iL1 ( t ) − iL2 ( t ) (Slave)

2

o

2

2

σ 1 (t) =

1

1

2

i=1

1

o

1

Therefore, this sliding mode control considers a voltage loop (Master module) and N−1 current loops (Slave modules). It can be pointed out that, from the equations (2) and (3), proper control actions lead to the desired steady state sliding motion, that is: e( t ) → 0 ⇒ vo → V ref ( t ) and iL1 ( t ) = iL2 ( t ) = L = iLN ( t ).

These control actions can be obtained from the dσ 2i < 0 (i = Lyapunov stability criteria by imposing dt = 1 ... N), this leading to: AUTOMATIKA 42(2001) 1−2, 37−44

R. Ramos, et al.

Master-Slave Sliding-Mode Control ...

from the later, the steady state equivalent control is given by: ueq i = +

LM FG N H

IJ K OP PQ

Li rLi N ⋅ Vref + + N ⋅ Ei RL Li CT Li CT dVref dt

2

FG rL + 1 IJ + d V H L R C K dt

ref 2

i

i

L

T

(6)

N

CT = ∑ Ci .

where

i=1

The sliding domain can be obtained by imposing −1 < ueqi < 1, this leading to: A < γ ( ω) i Ei Fig. 2 Simulation results of a Master-Slave three parallel-connected Buck power converters

where

R|F L ω I F C L ω I S|H NR K + GH N − 1JK + T OU| rL L C rL ω rL + ⋅M + + 2 PV N N N NR R Q|W 2

γ i ( ω) = u1

uj

R +1 =S T −1 R +1 =S T −1

when

σ1 > 0

when

σ1 < 0

when

σj >0

when

σj