Machine Instructions • An individual machine code is called a Machine Instruction
Machine Code
– e.g. the machine instruction to add 1 to the value in accumulator A is 01001100
The commands the CPU understands
Week 2: Addressing Modes
• The set of all codes recognized by a particular CPU is known as its Instruction Set
1
Week 2: Addressing Modes
Machine Code
Machine Instructions
A set of binary codes that are recognised and executed directly by a particular CPU
• A typical machine instruction consists of an operation code (op-code), which specifies what operation the CPU is to do, plus a number of arguments, which specify what data the CPU is to operate on
3
– e.g. the machine instruction to add 2 to the value in accumulator A is 10001011 00000010
Week 2: Addressing Modes
2
Week 2: Addressing Modes
4
What Do/Can Machine Instructions Do?
Instructions: Computations • The arithmetic and logical operations, normally carried out by the ALU (Arithmetic Logic Unit) • What might this include?
• We can group the instructions according to function. The groups given here are generally applicable to most instruction sets (i.e. they apply to the machine code for most types of processor)
Week 2: Addressing Modes
– – – – – 5
Instructions: Data Transfer • • • • •
Week 2: Addressing Modes
7
Instructions: Flow Control
From where, to where? load (e.g. from memory to a register) store (e.g. from a register to memory) move (e.g. from register to register) …
Week 2: Addressing Modes
add subtract increment invert bits … and more
• A computer program is not a lot of use without loops, functions, etc. • We need to have machine codes to control the flow of execution through a machine code program • Branching, jumping to subroutines, returning from subroutines 6
Week 2: Addressing Modes
8
Instructions: Others
68HC11 Register Set
• You’ll come across other types of instruction as the course proceeds • The bulk, however, fall into the three categories already mentioned:
• Every CPU contains a set of registers which are available to the machine-code programmer • You’ve seen two of these already: – the Program Counter (PC) – the Accumulator
– Data transfer – Computations – Flow control
• You need to know about these registers before you can start writing machine-code programs Week 2: Addressing Modes
9
Example machine codes (68HC11 CPU)
• This is the way a programmer needs to view the CPU • As a programmer, you don’t necessarily need to know about what we’ve learnt before regarding the internals, but you need to know what’s sometimes termed the Programmer’s Model of the CPU
What does this mean? If you don’t know, it’s time to revise!
Week 2: Addressing Modes
11
The Programmer’s Model
• The 68HC11 CPU is the one we’ll be looking at in this course • The codes that follow apply to the whole 68HC11 family of microcontrollers • The CPU has the following characteristics: – an 8-bit word length – a 16-bit address space – memory-mapped I/O
Week 2: Addressing Modes
10
Week 2: Addressing Modes
12
68HC11 Architecture: Programmers Model 7 Accumulator A 0 15
7 Accumulator
Double accumulator D
B
0
0
D
15
Index register IX
0
IX
15
Index register IY
0
IY
15
Stack pointer
0
SP
15
Program counter
0
PC
S X H I N Z V C
Instruction: LDAA direct
A:B
mnemonic: op-code: operation:
Week 2: Addressing Modes
increasing addresses
CCR Condition Code Register Carry Overflow Zero Negative I interrupt mask Half-carry (from bit 3) X interrupt mask Stop disable
13
increasing addresses
86 dd
LDAA 86 (hex) Load accumulator A with the 8-bit value immediately following the op-code
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15
• They perform the same operation, but the source is different • We say they use different addressing modes • Customarily, the same mnemonic is used for all operations that perform essentially the same operation, and differ only in their addressing modes • It’s the syntax (in assembly code) which differentiates them
op code for LDAA data to be loaded
Week 2: Addressing Modes
op code for LDAA address of data to be loaded
Why two instructions with the same mnemonic?
Instruction: LDAA immediate mnemonic: op-code: operation:
96 dd
LDAA 96 (hex) Load accumulator A with the contents of memory location given by 8-bit number following the op-code
14
Week 2: Addressing Modes
16
Addressing Modes Example
Endian-ness
LDAA immediate to load the value (decimal) 30 into accumulator A would be written: LDAA #30
• 68HC11 is a big endian microprocessor. • When we write a 16 bit in a memory location, the first byte of memory contains the high portion of the 16 bit number. • Big Endian à Big End in First • Small Endian à Small end in First • Intel 80x86, Pentium processors are the examples of Small Endian machines.
LDAA direct to load the contents of address 30 into accumulator A would be written: LDAA 30 The # sign distinguishes between them Week 2: Addressing Modes
17
Week 2: Addressing Modes
19
Memory Addressing Memory consists of addressable locations. A memory location has 2 components: address
contents
Data transfer between CPU and memory involves address bus and data bus address bus lines CPU
Machine Language Execution How Machine Language Programs Are Executed on the CPU?
memory data bus lines
Week 2: Addressing Modes
Week 2: Addressing Modes
20
Assembly ßà Machine Code
Machine Language Execution
Assembly language facilitates to write programs for humans. Assembler converts assembly programs to machine code.
• Each machine language instruction consists of an operation code (opcode) and zero or more operands. • Operands are the data or the location of the data to be used in performing the specified operation. • Often some operands are implicit in the opcode. • Each instruction occupies some number of consecutive bytes of memory and the machine program consists of a sequence of instructions stored consecutively in memory. • A special register called the program counter (PC) in the control unit of the CPU contains the address of the next byte of instruction code to be fetched. • Unless the program directs otherwise, instructions are executed in the sequence they are stored in memory. Week 2: Addressing Modes
Machine code equivalent starting at $C000 Assembly language program LDAA
$D000
ADDA
$D001
STAA
$D000
Week 2: Addressing Modes
21
The Instruction Execution Cycle 68HC11 Example
Assembler
.. B6 D0 00 BB D0 01 B7 D0 00 ..
LDAA
ADDA $D001
STAA
$D000
23
Instruction Code and Operands
LOAD: copy the content of a memory location into a register in CPU LDAA $D000 load the content of memory at address $D000 into register A
instruction code operand instruction code
.. B6 D0 00 BB D0 01 B7 D0 00 ..
LDAA
$D000
ADDA $D001
ADD: add the content of a memory location to a register in CPU and store the result in register. ADDA $D001 add the content of memory at address $D001 to register A and store the result in register A.
instruction code
STORE: store the content of a register into a location in memory STAA $D000 store the content of accumulator/ register A into memory at address $D000.
Different instructions may need different number of operands or sometimes none at all. In the above program, all operands are two-byte numbers.
Week 2: Addressing Modes
$D000
operand operand
22
Week 2: Addressing Modes
STAA
$D000
24
LDAA $D000
LDAA $D000 ($B6 $D0 $00)
• Step 1: Assume PC=$C000. $C000 is placed on A-bus and READ issued. • Step 2: 8-bit content at location $C000 ($B6) is returned on data bus and place in the Instruction Decode Register (IDR) in the control unit.
• Step 3: Control unit (decoder) recognizes LOAD instruction. This instruction needs 2-byte value for operand address. – Issues two READ cycles: • address bus-READ-$C001 à data bus returns $D0 • address bus-READ-$C002 à data bus returns $00
– At the end PC becomes $C003
• Step 4: Execution of the instruction ($B6) needs the content of location $D000. A READ is issued with address = $D000 à data bus returns $19 and that is put into register A.
– PC is incremented by 1 to become $C001 – The machine instruction loaded into IDR will be analyzed to understand what to do next in the control unit. Week 2: Addressing Modes
CPU IDR
Step 2: $B6 is returned on D-bus. PC ß $C001 Week 2: Addressing Modes
.. $B6 $D0 $00 $BB $D0 $01 $B7 $D0 $00 .. $19 $37 ..
27
LDAA $D000 ($B6 $D0 $00)
LDAA $D000 ($B6 $D0 $00) Step 1: A-bus ($C000-READ)
Week 2: Addressing Modes
25
..
Step 3: A-bus ($C001 & $C002 READ) $B6
[$C000] [$C001] [$C002] [$C003] [$C004] [$C005] [$C006] [$C007] [$C008]
CPU IDR
[$D000] [$D001]
MAR
$D0 & $00 is returned on D-bus saperately and put into Memory Address Register (MAR) 26
Week 2: Addressing Modes
$D0 $00 $BB $D0 $01 $B7 $D0 $00 .. $19 $37 ..
[$C000] [$C001] [$C002] [$C003] [$C004] [$C005] [$C006] [$C007] [$C008] [$D000] [$D001]
28
LDAA $D000 ($B6 $D0 $00) Step 4: A-bus ($D000 - READ)
CPU IDR MAR ACCA $19 is returned on D-bus and put into register A (Accumulator A)
.. $B6 $D0 $00 $BB $D0 $01 $B7 $D0 $00 .. $19 $37 ..
ADDA $D001 ($BB $D0 $01)
[$C000] [$C001] [$C002] [$C003] [$C004] [$C005] [$C006] [$C007] [$C008]
• Step 4: Execution of the instruction needs the content of location $D001 • A READ is issued with address bus = $D001 and data bus returns $37 (put into MDR - Memory Data Register in the control unit). • Step 5: ALU adds the content of MDR ($37) to ACCA ($19) so that ACCA becomes $50.
[$D000] [$D001]
Week 2: Addressing Modes
29
Week 2: Addressing Modes
ADDA $D001 ($BB $D0 $01)
STAA $D001 ($B7 $D0 $01)
• Step 1: PC=$C003, $C003 is placed on A-bus and READ is issued. • Step 2: 8-bit content at location $C003=$BB is returned on data bus and place in IDR. PC is incremented by 1 to become $C004. • Step 3: Control unit (instruction decoder) recognizes ADD instruction. Needs a 2-byte value for operand address and it issues 2 READ cycles:
• Step 1: PC = $C006, $C006 is placed on address bus and READ is issued. • Step 2: 8-bit content at location $C006 = $B7 is returned on data bus and placed in IDR. PC is incremented by 1 to become $C007. • Step 3: Control unit (instruction decoder) recognizes STORE instruction. It needs a 2-byte value for operand address. It issues two separate READ cycles – address bus = $C007 à data bus = $D0 – address bus = $C008 à data bus = $01 – At the end PC becomes $C009 • Step 4: Execution of the instruction needs to issue a WRITE to memory with address bus = $D001 and data bus = $50
– address bus = $C004 à data bus = $D0 – address bus = $C005 à data bus = $01 – At the end, PC becomes $C006 Week 2: Addressing Modes
MAR
30
Week 2: Addressing Modes
31
32
Common Addressing Modes • Machine-code programmers need to know what addressing modes are provided by a given CPU • Not all processors implement all addressing modes • Here we list some of the most common addressing modes
Addressing Modes One instruction, multiple meanings
Week 2: Addressing Modes
33
35
Immediate
Addressing Modes
• The argument itself appears immediately after the op-code. • In other words, the address of the argument is the address of the next memory location after the op-code • This addressing mode is used only for input arguments (it’s meaningless for output arguments – think about it!)
• “Addressing Modes” is the technical term for the various different ways that arguments for machine instructions can be specified • It is common practice for CPUs to provide several machine codes for each basic operation: one code for each addressing mode that makes sense with this operation. Week 2: Addressing Modes
Week 2: Addressing Modes
34
Week 2: Addressing Modes
36
68HC11 Immediate
68HC11 Direct
• An 8-bit or 16-bit argument immediately follows the op-code LDAA #23
• An 8-bit address in the range 0…255 follows the op-code
The argument (specified in decimal, by default)
LDAA 23 LDAA $FF
# signifies immediate mode
Week 2: Addressing Modes
$ means it’s hex
37
Direct (or Absolute)
255, so it can’t be direct, and must therefore be extended
BRA $F8 BNE $21
255 hex = 597 decimal, so it’s extended
Week 2: Addressing Modes
41
Relative
Jump $21 bytes ahead [PC+$21]
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43
Indexed
• The relative address of the argument follows the op-code • Relative addresses specify where the argument is relative to the current value of the PC • The CPU calculates the actual address by adding together the relative address and the current value of the PC Week 2: Addressing Modes
Jump location at [PC – 8]
• The address of the argument is the value currently stored in a specified index register (or general-purpose register) plus an offset that immediately follows that op-code • 68HC11 has two index registers IX and IY • Useful for implementing arrays!
42
Week 2: Addressing Modes
44
Inherent
68HC11 Indexed
• The instruction is self contained. i.e. no operands are used. • They are generally one byte instructions with no operands. • These instructions are generally used to operate directly on registers. For example, clear accumulator A, B, X, etc.
• The address of the argument is worked out by adding the value of the IX or IY (index) registers to the number before the comma LDAA 1, X You can’t really make mistake with this one – LDAA 2, Y it’s the only one with a comma
If you were to put the address of the start of an array in IX, you could address the elements of it using the number Week 2: Addressing Modes
Week 2: Addressing Modes
45
68HC11 Inherent
68HC11 Indexed It loads the byte at address [X+offset]to Accu A
LDAA
47
• In these instructions, there is no argument. They generally operate on registers.
3,X
Aß0 Offset (unsigned 8 bit) 0 .. 255
Week 2: Addressing Modes
CLRA INX
Index Register to be used X or Y
46
XßX+1
Week 2: Addressing Modes
48
Patterns in Machine Code
Others (not 68HC11)
Machine codes are not chosen at random! LDAA imm LDAA dir LDAA ext LDAA ind, X LDAB imm LDAB dir LDAB ext LDAB ind, X
• register – The argument is the current contents of a specific register
• register-indirect – The address of the argument is the current value of a specified register
• register-autoincrement/decrement – As register-indirect, but adjust register to point to next/previous location before or after using its value
• Indirect – The number following the op-code is the address of a memory location that contains the address of the argument Week 2: Addressing Modes
49
imm
86 dd
Assemblycode syntax LDAA #dd
dir
96 dd
LDAA dd
ext
A6 dd dd
Machine codes
ind, X B6 dd ind, Y 18 B6 dd
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
Week 2: Addressing Modes
51
How is Addressing Mode Specified? • In most cases, set by bits from opcode • ADDA: $8B $9B $BB $AB • ADDB: $CB $DB $FB $EB Opcode (8bit) format
How can we LDAA dddd Differentiate Addressing Modes?
1
A/B AM1 AM0 1
LDAA dd, X
LDAA dd, Y Are These Numbers
Selects Register A for 0 or B for 1
Chosen Randomly? Week 2: Addressing Modes
1 1 1 1 1 1 1 1
defines the addressing mode
All of LDAA Instructions Mode
86 96 A6 B6 C6 D6 E6 F6
50
00 01 10 11
immediate Direct Extended Indexed
Week 2: Addressing Modes
0
1
1
code for ADD
52
Some Arithmetic Instructions ADDA ADDB ADDD ABA
add 8-bit word to accumulator A add 8-bit word to accumulator B add 16-bit word to double accumulator D add B to A
Conditionals Bits in Condition Code Register
Equivalent subtraction operations are: SUBA, SUBB, SUBD, SBA
Week 2: Addressing Modes
Other Instructions
55
Condition Code Register (CCR)
There are also instructions to:• Increment, decrement or negate a register or memory location • Perform bitwise logical operations such as AND, OR, XOR and NOT • Perform shifts, rotates, and many more logical and arithmetic operations Week 2: Addressing Modes
Week 2: Addressing Modes
53
• 5 status bits. – Certain bits in CCR indicate the situation after the operation. For instance, if previous operation yields a zero output, Z flag becomes one.
• 2 interrupt masking bits (later) • 1 stop disable bit (later)
54
Week 2: Addressing Modes
56
Condition Code Register CCR bit # 7 6 5 4 3 2 1 0
Bit Name S X H I N Z V C
Carry Flag (C)
Function Stop disable flag XIRQ interrupt mask Half carry from lower 4 bit Interrupt mask Negative Zero Overflow Carry
Week 2: Addressing Modes
• Indicates a carry from an addition or a borrow from a subtraction • For addition, – C = 1 if carry out exists – C = 0 if no carry out
Carry/Borrow (C) Overflow (V) Zero (Z) Negative (N) Half Carry (H)
59
Example 1
Status Bits • • • • •
Week 2: Addressing Modes
57
Add 53 and 67, and determine if carry bit is set or not. LDAA LDAB ABA Used by CPU’s branch instructions to make decisions
#53 #67 MSB
+
LSB
53
0
0
1
1
0
1
0
1
67
0
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
120
0
C The result fits into 8 bits, therefore no carry. Week 2: Addressing Modes
58
Week 2: Addressing Modes
60
Example 2
Handling of Signed Numbers
Add 130 and 163, and determine if carry bit is set or not. LDAA LDAB ABA
#130 #163 MSB
+
130
1
0
0
0
0
0
1
0
163
1
0
1
0
0
0
1
1
0
0
1
0
0
1
0
1
293
1
• 6811 handles signed numbers using the 2’s complement numbering system • Recall the most significant bit is the sign • You negate a number by taking its 2’s complement (e.g. complement all bits and add 1) • Review Digital Logic I and II courses
LSB
C The result is 9 bits, we use C flag as the 9th bit. Week 2: Addressing Modes
61
Example 3 (16 bit addition) LDD ADDD
+
• All arithmetic (addition/subtraction) performed on full binary number, including sign. • Hardware treats signed number as unsigned from perspective of requested operation • Benefit is that we do not need to do anything special to manage sign of operands or result • Disadvantage, seems counterintuitive.
LSB
50274
1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0
28712
0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0
78986
63
Arithmetic with Signed Numbers
#50274 #28712 MSB
Week 2: Addressing Modes
1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0
C The result is 17 bits (exceeds 65535), we use C flag as the 17th bit. Week 2: Addressing Modes
62
Week 2: Addressing Modes
64
Methods to Determine C Flag Value
2s Complement Ranges +3 = 00000011 +26 = 00011010 +40 = 00101000 +102= 01100110
Complement and add 1
• Method 1: more like how we do it hand –Explicitly monitor for carry or borrow,
-3 = 11111101 -26 = 11100110 -40 = 11011000 -102= 10011010
• Method 2: possible implementation –Express result expressed as 9/17 bit quantity –For addition, extra bit is the carry flag –For subtraction—carry determined from extra bit • borrow from fictitious 9th bit in first subtrahend that is always “1” • carry is the complement of the extra 9th/17th bit from result
Range of 2’s complement numbers: 8-bit Reg.
-128 to +127 decimal
16-bit reg.
-32,768 to 32,767 decimal Week 2: Addressing Modes
• Method 3: possible implementation—minimum hardware? –Examine operands and result, develop Boolean equations for C –Method 3 is how the carry is documented in the 68HC11 manual 67
Signed Addition Example
C Flag (for 2s Complement Numbers)
Add 56 and –53 ($CB), and determine if carry bit is set or not. LDAA LDAB ABA
• C flag set to ‘1’ if – Carry out from MSB for addition – Borrow from MSB for subtraction
#56 #-53 MSB
+
• C flag set to ‘0’ if neither of the above apply • Several hardware implementations possible to determine value of C
Week 2: Addressing Modes
Week 2: Addressing Modes
65
LSB
56
0
0
1
1
1
0
0
0
-53
1
1
0
0
1
0
1
1
0
0
0
0
0
0
1
1
3
1
C The result is 8 bits, we don't use C flag as the 9th bit since the numbers are taken as signed 66
Week 2: Addressing Modes
68
Signed Subtraction Example
Overflow Flag (V Flag)
Add 56 and –53 ($CB), and determine if carry bit is set or not. LDAA SUBA
For subtraction, a fictitous 9th bit is assumed.
#56 #-53 MSB
56
+
1
-53 3
1
• CPU sets V flag to a logic ‘1’ when the result of an operation is beyond of the range that can be represented • Known as 2’s complement overflow • CPU clears flag when the number is within range
LSB
0
0
1
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
1
1 C
complement For subtraction 9th bit is the complement of carry
The resultant C is 0 Week 2: Addressing Modes
Add 105 and 45, and determine if overflow bit is set or not.
Add 33 and –40, and determine if carry bit is set or not.
LDAA ADDA
#33 #-40 MSB
+
0
0
1
0
0
0
0
1
-40
1
1
0
1
1
0
0
0
1
1
1
1
1
0
0
1
0
Desired Value
LSB
33
-7
#105 #45
+
MSB
0
1
1
0
1
0
0
1
+45
0
0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
-106 how it is interpreted!
9th bit is the carry
70
LSB
105
150
C
Week 2: Addressing Modes
71
2s Complement Overflow Example
Signed Addition Example LDAA ADDA
Week 2: Addressing Modes
69
0
Result is Negative!! Week 2: Addressing Modes
Two positive numbers are added and a negative number is computed !!! OVERFLOW!!! 72
2s Complement Overflow Example 2
In More Simple Terms
Add -120 and -10, and determine if overflow bit is set or not. LDAA ADDA
#-120 #-10
+
MSB
LSB
-120
1
0
0
0
1
0
0
0
-10
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
-130
1
Range Limit
V Flag
Outside Inside
1 0
The result exceeds the range of 8 bit 2s complement numbers (i.e. less than -128) OVERFLOW!!! Week 2: Addressing Modes
Week 2: Addressing Modes
73
2s Complement Overflow Example 3
Negative Flag
Add 80 and 45, and determine if overflow bit is set or not. LDAA ADDA
#80 #45
+
MSB
80
1
0
1
0
0
0
0
45
1
1
1
1
0
1
1
0
0
1
1
0
1
1
0
125
0
• • • •
N-bit indicates state of msb of a result If msb = 1 => N-flag = 1 If msb = 0 => N-flag = 0 N-bit is used in 2’s complement arithmetic to indicate the sign of a number • So if V-flag = 0 => correct answer => N-flag valid sign
LSB
0
The result does NOT exceeds the range of 8 bit 2s complement number NO OVERFLOW!!! Week 2: Addressing Modes
75
74
Week 2: Addressing Modes
76
N Flag
Zero Flag (Z flag)
• 6811 treats all numbers as 2’s complement binary numbers • Subtraction is performed using 2’s complement arithmetic • N Flag is simply the MSB of the result
Value
Value of MSB
Value of N-flag
+
0
0
-
1
1
Week 2: Addressing Modes
Z bit is set to a logic ‘1’ when the result is ‘0’, otherwise Z=0.
Week 2: Addressing Modes
77
Zero Flag Example 1
Half Carry (H flag)
Add 50 and -50, and determine zero flag is set or not. LDAA ADDA
• Used only for BCD (Binary Coded Decimal) operations. (They will be discussed later) • H-flag updated only by ABA, ADDA, ADDB, ADCA, ADCB • To do decimal arithmetic, the 68HC11 does arithmetic in binary and then uses H and C to adjust the calculation to give a proper decimal result.
Week 2: Addressing Modes
79
#50 #-50
MSB
LSB
50
0
0
1
1
0
0
1
0
+ -50
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
The 8bit result is all zeros. Therefore, Z flag is set. Note also that C=1 and V=0. 78
Week 2: Addressing Modes
80
Zero Flag Example 2 Add 50 and -47, and determine zero flag is set or not. LDAA ADDA
#50 #-47
MSB
LSB
50
0
0
1
1
0
0
1
0
+ -47
1
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
3
1
First Assembly Language Example Adding five numbers at address $C100 - $C104 and put the result in location $C105
Some bits are not zeros, therefore, Z flag is clear. Note that C=1 and V=0 Week 2: Addressing Modes
Week 2: Addressing Modes
81
Picture
Z Flag
All bits zero Some bits are ones
1 0
increasing addresses
Results of operation
Status of Z Flag
Week 2: Addressing Modes
83
82
$C100
?
$C101
?
$C102
?
…..
?
$C105
?
Week 2: Addressing Modes
+
84
Coding
Design
Clear accumulator A. A Self contained instruction.
• We have to perform a running sum operation (i.e. add the incoming number to a variable in an iterative way) • What about accumulator A? • That is what accumulators are used for!
CLRA ADDA ADDA ADDA ADDA ADDA STAA
A ß A + [$C100] $C100 $C101 $C102 $C103 $C104 $C105
A ß A + [$C101] A ß A + [$C102] A ß A + [$C103] A ß A + [$C104] [$C105] ß A
opcodes Week 2: Addressing Modes
accumulator ans + [$C100] ans + [$C101] ans + [$C102] ans + [$C103] ans + [$C104] ans to $C105
Week 2: Addressing Modes
85
87
Machine Code Equivalent of the Assembly Program
Implementation clear ans = ans = ans = ans = ans = store
operands
...
Clear accumulator (running sum)
CLRA ADDA ADDA ADDA ADDA ADDA STAA
Add the contents of memory locations to accumulator Store the answer to $C105
$C100 $C101 $C102 $C103 $C104 $C105
$4F $BB $BB $BB $BB $BB $B7
$C1 $C1 $C1 $C1 $C1 $C1
$00 $01 $02 $03 $04 $05
opcodes operands Week 2: Addressing Modes
86
Week 2: Addressing Modes
$C000
$4F
$C001
$BB
$C002
$C1
$C003
$00
$C004
$BB
$C005
$C1 ... 88
Improvement - 1 CLRA ADDA ADDA ADDA ADDA ADDA STAA
LDAA $C100
$C100 $C101 $C102 $C103 $C104 $C105
START Saves 1 byte, which may be quite important for systems with limited memory
Week 2: Addressing Modes
Clear Accumulator #$C100 0,X START
Add the byte at location [X+0] to A XßX+1 Jump to the location labeled by START
91
Improvement: Using Loops START
CLRA LDX ADDA INX JMP
#$C100 0,X
Therefore, we need a comparison operation and a conditional branch
We have to use an Index Register (Indexed Addressing) 90
We need to compare X with $C105
START
Yes, we can!
Week 2: Addressing Modes
X ß $C100
Week 2: Addressing Modes
89
Can we iterate through the memory locations?
$C100 $C101 $C102 $C103 $C104 $C105
CLRA LDX ADDA INX JMP
We need to jump conditionally to START to deal with the infinite loop
Improvement - 2 LDAA ADDA ADDA ADDA ADDA STAA
Improvement : Using Loops
Well, well, well. We have a loop that never stops.
Week 2: Addressing Modes
If X = $C105 then we continue, otherwise we jump to label START
92
CLRA LDX #$C100 START ADDA 0,X INX CPX #$C105 ............
S X H I N Z V C
The Final Program
Comparison
We need a branch instruction that checks CCR
Condition Code Register set if operation makes carry set if operation makes overflow set if the operation's result is zero set if the result is a negative number ....... if 3rd bit is set (for BCD numbers) ...... .....
Compare X immediately with value $C105
Jump 8 bytes backward PC ß PC -8
Comparison is a non-destructive subtraction It sets the appropriate bit in Condition Code Register (CCR)
Week 2: Addressing Modes
S X H I N Z V C
Condition Code Register set if operation makes carry set if operation makes overflow set if the operation's result is zero set if the result is a negative number ....... if 3rd bit is set (for BCD numbers) ...... ..... Week 2: Addressing Modes
LDAA
$C100
LDX
#$C101
START ADDA
$F8 = -8 in 2s complement form You must start counting from the next instruction backward or forward
0,X
INX CPX
#$C105
BNE
START
STAA
0,X
Week 2: Addressing Modes
93
Comparison CLRA LDX #$C100 START ADDA 0,X INX CPX #$C105 BNE START ...........
$B6 $C1 $00 $CE $C1 $01 $AB $00 $08 $8C $C1 $05 $26 $F8 $A7 $00
95
Example Checks Z bit in CCR. If it is 0 jumps to START
Fill a page (256 bytes) of memory with value of address ($D000 = $D0, $D001 = $01, etc...)
If Z bit is 1, then continues (i.e. exits loop)
MEMORY OUTPUT
$D000
$D0
$D001 $D002
$00 $D0
$D003
$02
$D004
$D0
$D005
$04 .... ....
BNE stands for Branch If Not Equal 94
$D0FD
$FC
$D0FE
$D0
$D0FF
$FE
Week 2: Addressing Modes
96
Example
First Version We use index register X to point out the beginning of the memory block. We store the value of X to the location pointed by X and increment X twice to move on.
LOOP
.... LDX STX INX INX CPX BNE ....
#$D000 $0,X
Move a page of memory from $D000 to $D200
X ß Starting address
$33
$D002
$55
$D0FF
$23
$D200
$73
$D201
$33
$D202
$55
$D2FF
$23
XßX+1 XßX+1
#$D100 LOOP
X ?= $D100, changes Z flag if Z bit = 0, go to the address labeled as LOOP
Week 2: Addressing Modes
97
Second Version (better) LOOP
$73
$D001
[X + 0] ß X
Week 2: Addressing Modes
LDAB LDX STX ABX CPX BNE ....
$D000
#$02 #$D000 $0,X
The First Version We need two pointers. 68HC11 has two index registers IX and IY. Use one of them for target, the other for source.
Bß2 X ß Starting address [X + 0] ß X XßX+B
#$D100 LOOP
X ?= $D100, changes Z flag if Z bit = 0, go to the address labeled as LOOP
LOOP
This version is better than the first one, since ABX is faster than two INX instructions. Week 2: Addressing Modes
99
98
LDX LDY LDAA STAA INX INY CPX BNE ....
#$D000 #$D200 $0,X $0,Y
X ß source address Y ß destination address A ß [X + 0] [Y + 0] ß A XßX+1 YßY+1
#$D100 LOOP
Week 2: Addressing Modes
X ?= $D100, changes Z flag if Z bit == 0, go to the address labeled as LOOP
100
